OSCL-LXR linux-6.0.1/​drivers/​misc/​habanalabs/​include/​gaudi2/​asic_reg/​cpu_if_regs.h	Source navigation Diff markup Identifier search General search
	Version: linux-6.0.1 spark-3.0.0 hadoop-3.2.0-src hadoop-3.3.0-src spark-2.4.7 linux-4.15.13 hadoop-2.7.4-src Revert   Change

 /* SPDX-License-Identifier: GPL-2.0
  *
  * Copyright 2016-2020 HabanaLabs, Ltd.
  * All Rights Reserved.
  *
  */
 
 /************************************
  ** This is an auto-generated file **
  **       DO NOT EDIT BELOW        **
  ************************************/
 
 #ifndef ASIC_REG_CPU_IF_REGS_H_
 #define ASIC_REG_CPU_IF_REGS_H_
 
 /*
  *****************************************
  *   CPU_IF
  *   (Prototype: CPU_IF)
  *****************************************
  */
 
 #define mmCPU_IF_ARUSER_OVR 0x4CC1104
 
 #define mmCPU_IF_ARUSER_OVR_EN 0x4CC1108
 
 #define mmCPU_IF_AWUSER_OVR 0x4CC110C
 
 #define mmCPU_IF_AWUSER_OVR_EN 0x4CC1110
 
 #define mmCPU_IF_ARUSER_MSB_OVR 0x4CC1114
 
 #define mmCPU_IF_AWUSER_MSB_OVR 0x4CC1120
 
 #define mmCPU_IF_AXCACHE_OVR 0x4CC1128
 
 #define mmCPU_IF_LOCK_OVR 0x4CC112C
 
 #define mmCPU_IF_PROT_OVR 0x4CC1130
 
 #define mmCPU_IF_MAX_OUTSTANDING 0x4CC1134
 
 #define mmCPU_IF_EARLY_BRESP_EN 0x4CC1138
 
 #define mmCPU_IF_FORCE_RSP_OK 0x4CC113C
 
 #define mmCPU_IF_CPU_SEI_INTR_STS 0x4CC1140
 
 #define mmCPU_IF_CPU_SEI_INTR_CLR 0x4CC1144
 
 #define mmCPU_IF_CPU_SEI_INTR_MASK 0x4CC1148
 
 #define mmCPU_IF_AXI_SPLIT_NO_WR_INFLIGHT 0x4CC114C
 
 #define mmCPU_IF_AXI_SPLIT_SEI_INTR_ID 0x4CC1150
 
 #define mmCPU_IF_TOTAL_WR_CNT 0x4CC1154
 
 #define mmCPU_IF_INFLIGHT_WR_CNT 0x4CC1158
 
 #define mmCPU_IF_TOTAL_RD_CNT 0x4CC115C
 
 #define mmCPU_IF_INFLIGHT_RD_CNT 0x4CC1160
 
 #define mmCPU_IF_SRAM_MSB_ADDR 0x4CC1164
 
 #define mmCPU_IF_CFG_MSB_ADDR 0x4CC1168
 
 #define mmCPU_IF_HBM_MSB_ADDR 0x4CC116C
 
 #define mmCPU_IF_PCIE_MSB_ADDR 0x4CC1170
 
 #define mmCPU_IF_KMD_HW_DIRTY_STATUS 0x4CC1174
 
 #define mmCPU_IF_MSTR_IF_E2E_FORCE_BP 0x4CC1188
 
 #define mmCPU_IF_MSTR_IF_E2E_GRCFL_CLR 0x4CC118C
 
 #define mmCPU_IF_LBW_TERMINATE_AWADDR_ERR 0x4CC11A0
 
 #define mmCPU_IF_LBW_TERMINATE_ARADDR_ERR 0x4CC11A4
 
 #define mmCPU_IF_CFG_LBW_TERMINATE_BRESP 0x4CC11A8
 
 #define mmCPU_IF_CFG_LBW_TERMINATE_RRESP 0x4CC11AC
 
 #define mmCPU_IF_PF_PQ_PI 0x4CC1200
 
 #define mmCPU_IF_PQ_BASE_ADDR_LOW 0x4CC1204
 
 #define mmCPU_IF_PQ_BASE_ADDR_HIGH 0x4CC1208
 
 #define mmCPU_IF_PQ_LENGTH 0x4CC120C
 
 #define mmCPU_IF_CQ_BASE_ADDR_LOW 0x4CC1210
 
 #define mmCPU_IF_CQ_BASE_ADDR_HIGH 0x4CC1214
 
 #define mmCPU_IF_CQ_LENGTH 0x4CC1218
 
 #define mmCPU_IF_EQ_BASE_ADDR_LOW 0x4CC1220
 
 #define mmCPU_IF_EQ_BASE_ADDR_HIGH 0x4CC1224
 
 #define mmCPU_IF_EQ_LENGTH 0x4CC1228
 
 #define mmCPU_IF_EQ_RD_OFFS 0x4CC122C
 
 #define mmCPU_IF_QUEUE_INIT 0x4CC1230
 
 #define mmCPU_IF_TPC_SERR_INTR_STS 0x4CC1300
 
 #define mmCPU_IF_TPC_SERR_INTR_CLR 0x4CC1304
 
 #define mmCPU_IF_TPC_SERR_INTR_MASK 0x4CC1308
 
 #define mmCPU_IF_TPC_DERR_INTR_STS 0x4CC1310
 
 #define mmCPU_IF_TPC_DERR_INTR_CLR 0x4CC1314
 
 #define mmCPU_IF_TPC_DERR_INTR_MASK 0x4CC1318
 
 #define mmCPU_IF_MME_SERR_INTR_STS_0 0x4CC1320
 
 #define mmCPU_IF_MME_SERR_INTR_STS_1 0x4CC1324
 
 #define mmCPU_IF_MME_SERR_INTR_STS_2 0x4CC1328
 
 #define mmCPU_IF_MME_SERR_INTR_STS_3 0x4CC132C
 
 #define mmCPU_IF_MME_SERR_INTR_CLR_0 0x4CC1330
 
 #define mmCPU_IF_MME_SERR_INTR_CLR_1 0x4CC1334
 
 #define mmCPU_IF_MME_SERR_INTR_CLR_2 0x4CC1338
 
 #define mmCPU_IF_MME_SERR_INTR_CLR_3 0x4CC133C
 
 #define mmCPU_IF_MME_SERR_INTR_MASK_0 0x4CC1340
 
 #define mmCPU_IF_MME_SERR_INTR_MASK_1 0x4CC1344
 
 #define mmCPU_IF_MME_SERR_INTR_MASK_2 0x4CC1348
 
 #define mmCPU_IF_MME_SERR_INTR_MASK_3 0x4CC134C
 
 #define mmCPU_IF_MME_DERR_INTR_STS_0 0x4CC1350
 
 #define mmCPU_IF_MME_DERR_INTR_STS_1 0x4CC1354
 
 #define mmCPU_IF_MME_DERR_INTR_STS_2 0x4CC1358
 
 #define mmCPU_IF_MME_DERR_INTR_STS_3 0x4CC135C
 
 #define mmCPU_IF_MME_DERR_INTR_CLR_0 0x4CC1360
 
 #define mmCPU_IF_MME_DERR_INTR_CLR_1 0x4CC1364
 
 #define mmCPU_IF_MME_DERR_INTR_CLR_2 0x4CC1368
 
 #define mmCPU_IF_MME_DERR_INTR_CLR_3 0x4CC136C
 
 #define mmCPU_IF_MME_DERR_INTR_MASK_0 0x4CC1370
 
 #define mmCPU_IF_MME_DERR_INTR_MASK_1 0x4CC1374
 
 #define mmCPU_IF_MME_DERR_INTR_MASK_2 0x4CC1378
 
 #define mmCPU_IF_MME_DERR_INTR_MASK_3 0x4CC137C
 
 #define mmCPU_IF_HDMA_SERR_INTR_STS 0x4CC1380
 
 #define mmCPU_IF_HDMA_SERR_INTR_CLR 0x4CC1384
 
 #define mmCPU_IF_HDMA_SERR_INTR_MASK 0x4CC1388
 
 #define mmCPU_IF_HDMA_DERR_INTR_STS 0x4CC1390
 
 #define mmCPU_IF_HDMA_DERR_INTR_CLR 0x4CC1394
 
 #define mmCPU_IF_HDMA_DERR_INTR_MASK 0x4CC1398
 
 #define mmCPU_IF_PDMA_SERR_INTR_STS 0x4CC13A0
 
 #define mmCPU_IF_PDMA_SERR_INTR_CLR 0x4CC13A4
 
 #define mmCPU_IF_PDMA_SERR_INTR_MASK 0x4CC13A8
 
 #define mmCPU_IF_PDMA_DERR_INTR_STS 0x4CC13B0
 
 #define mmCPU_IF_PDMA_DERR_INTR_CLR 0x4CC13B4
 
 #define mmCPU_IF_PDMA_DERR_INTR_MASK 0x4CC13B8
 
 #define mmCPU_IF_SRAM_SERR_INTR_STS 0x4CC13C0
 
 #define mmCPU_IF_SRAM_SERR_INTR_CLR 0x4CC13C4
 
 #define mmCPU_IF_SRAM_SERR_INTR_MASK 0x4CC13C8
 
 #define mmCPU_IF_SRAM_DERR_INTR_STS 0x4CC13D0
 
 #define mmCPU_IF_SRAM_DERR_INTR_CLR 0x4CC13D4
 
 #define mmCPU_IF_SRAM_DERR_INTR_MASK 0x4CC13D8
 
 #define mmCPU_IF_HBM_SERR_INTR_STS 0x4CC13E0
 
 #define mmCPU_IF_HBM_SERR_INTR_CLR 0x4CC13E4
 
 #define mmCPU_IF_HBM_SERR_INTR_MASK 0x4CC13E8
 
 #define mmCPU_IF_HBM_DERR_INTR_STS 0x4CC13F0
 
 #define mmCPU_IF_HBM_DERR_INTR_CLR 0x4CC13F4
 
 #define mmCPU_IF_HBM_DERR_INTR_MASK 0x4CC13F8
 
 #define mmCPU_IF_HMMU_SERR_INTR_STS 0x4CC1400
 
 #define mmCPU_IF_HMMU_SERR_INTR_CLR 0x4CC1404
 
 #define mmCPU_IF_HMMU_SERR_INTR_MASK 0x4CC1408
 
 #define mmCPU_IF_HMMU_DERR_INTR_STS 0x4CC1410
 
 #define mmCPU_IF_HMMU_DERR_INTR_CLR 0x4CC1414
 
 #define mmCPU_IF_HMMU_DERR_INTR_MASK 0x4CC1418
 
 #define mmCPU_IF_DEC_SERR_INTR_STS 0x4CC1420
 
 #define mmCPU_IF_DEC_SERR_INTR_CLR 0x4CC1424
 
 #define mmCPU_IF_DEC_SERR_INTR_MASK 0x4CC1428
 
 #define mmCPU_IF_DEC_DERR_INTR_STS 0x4CC1430
 
 #define mmCPU_IF_DEC_DERR_INTR_CLR 0x4CC1434
 
 #define mmCPU_IF_DEC_DERR_INTR_MASK 0x4CC1438
 
 #define mmCPU_IF_NIC_SERR_INTR_STS 0x4CC1440
 
 #define mmCPU_IF_NIC_SERR_INTR_CLR 0x4CC1444
 
 #define mmCPU_IF_NIC_SERR_INTR_MASK 0x4CC1448
 
 #define mmCPU_IF_NIC_DERR_INTR_STS 0x4CC1450
 
 #define mmCPU_IF_NIC_DERR_INTR_CLR 0x4CC1454
 
 #define mmCPU_IF_NIC_DERR_INTR_MASK 0x4CC1458
 
 #define mmCPU_IF_SYNC_MNGR_SERR_INTR_STS 0x4CC1460
 
 #define mmCPU_IF_SYNC_MNGR_SERR_INTR_CLR 0x4CC1464
 
 #define mmCPU_IF_SYNC_MNGR_SERR_INTR_MASK 0x4CC1468
 
 #define mmCPU_IF_SYNC_MNGR_DERR_INTR_STS 0x4CC1470
 
 #define mmCPU_IF_SYNC_MNGR_DERR_INTR_CLR 0x4CC1474
 
 #define mmCPU_IF_SYNC_MNGR_DERR_INTR_MASK 0x4CC1478
 
 #define mmCPU_IF_HIF_SERR_INTR_STS 0x4CC1480
 
 #define mmCPU_IF_HIF_SERR_INTR_CLR 0x4CC1484
 
 #define mmCPU_IF_HIF_SERR_INTR_MASK 0x4CC1488
 
 #define mmCPU_IF_HIF_DERR_INTR_STS 0x4CC1490
 
 #define mmCPU_IF_HIF_DERR_INTR_CLR 0x4CC1494
 
 #define mmCPU_IF_HIF_DERR_INTR_MASK 0x4CC1498
 
 #define mmCPU_IF_XBAR_SERR_INTR_STS 0x4CC14A0
 
 #define mmCPU_IF_XBAR_SERR_INTR_CLR 0x4CC14A4
 
 #define mmCPU_IF_XBAR_SERR_INTR_MASK 0x4CC14A8
 
 #define mmCPU_IF_XBAR_DERR_INTR_STS 0x4CC14B0
 
 #define mmCPU_IF_XBAR_DERR_INTR_CLR 0x4CC14B4
 
 #define mmCPU_IF_XBAR_DERR_INTR_MASK 0x4CC14B8
 
 #define mmCPU_IF_TPC_SEI_INTR_STS 0x4CC14C0
 
 #define mmCPU_IF_TPC_SEI_INTR_CLR 0x4CC14C4
 
 #define mmCPU_IF_TPC_SEI_INTR_MASK 0x4CC14C8
 
 #define mmCPU_IF_MME_SEI_INTR_STS_0 0x4CC14D0
 
 #define mmCPU_IF_MME_SEI_INTR_STS_1 0x4CC14D4
 
 #define mmCPU_IF_MME_SEI_INTR_STS_2 0x4CC14D8
 
 #define mmCPU_IF_MME_SEI_INTR_STS_3 0x4CC14DC
 
 #define mmCPU_IF_MME_SEI_INTR_CLR_0 0x4CC14E0
 
 #define mmCPU_IF_MME_SEI_INTR_CLR_1 0x4CC14E4
 
 #define mmCPU_IF_MME_SEI_INTR_CLR_2 0x4CC14E8
 
 #define mmCPU_IF_MME_SEI_INTR_CLR_3 0x4CC14EC
 
 #define mmCPU_IF_MME_SEI_INTR_MASK_0 0x4CC14F0
 
 #define mmCPU_IF_MME_SEI_INTR_MASK_1 0x4CC14F4
 
 #define mmCPU_IF_MME_SEI_INTR_MASK_2 0x4CC14F8
 
 #define mmCPU_IF_MME_SEI_INTR_MASK_3 0x4CC14FC
 
 #define mmCPU_IF_PLL_LSB_SEI_INTR_STS 0x4CC1500
 
 #define mmCPU_IF_PLL_LSB_SEI_INTR_CLR 0x4CC1504
 
 #define mmCPU_IF_PLL_LSB_SEI_INTR_MASK 0x4CC1508
 
 #define mmCPU_IF_PLL_MSB_SEI_INTR_STS 0x4CC1510
 
 #define mmCPU_IF_PLL_MSB_SEI_INTR_CLR 0x4CC1514
 
 #define mmCPU_IF_PLL_MSB_SEI_INTR_MASK 0x4CC1518
 
 #define mmCPU_IF_HMMU_SEI_INTR_STS 0x4CC1520
 
 #define mmCPU_IF_HMMU_SEI_INTR_CLR 0x4CC1524
 
 #define mmCPU_IF_HMMU_SEI_INTR_MASK 0x4CC1528
 
 #define mmCPU_IF_HDMA_SEI_INTR_STS 0x4CC1530
 
 #define mmCPU_IF_HDMA_SEI_INTR_CLR 0x4CC1534
 
 #define mmCPU_IF_HDMA_SEI_INTR_MASK 0x4CC1538
 
 #define mmCPU_IF_PDMA_SEI_INTR_STS 0x4CC1540
 
 #define mmCPU_IF_PDMA_SEI_INTR_CLR 0x4CC1544
 
 #define mmCPU_IF_PDMA_SEI_INTR_MASK 0x4CC1548
 
 #define mmCPU_IF_HBM_SEI_INTR_STS 0x4CC1550
 
 #define mmCPU_IF_HBM_SEI_INTR_CLR 0x4CC1554
 
 #define mmCPU_IF_HBM_SEI_INTR_MASK 0x4CC1558
 
 #define mmCPU_IF_DEC_SEI_INTR_STS 0x4CC1560
 
 #define mmCPU_IF_DEC_SEI_INTR_CLR 0x4CC1564
 
 #define mmCPU_IF_DEC_SEI_INTR_MASK 0x4CC1568
 
 #define mmCPU_IF_HIF_SEI_INTR_STS 0x4CC1570
 
 #define mmCPU_IF_HIF_SEI_INTR_CLR 0x4CC1574
 
 #define mmCPU_IF_HIF_SEI_INTR_MASK 0x4CC1578
 
 #define mmCPU_IF_SYNC_MNGR_SEI_INTR_STS 0x4CC1580
 
 #define mmCPU_IF_SYNC_MNGR_SEI_INTR_CLR 0x4CC1584
 
 #define mmCPU_IF_SYNC_MNGR_SEI_INTR_MASK 0x4CC1588
 
 #define mmCPU_IF_NIC_SEI_INTR_STS 0x4CC1590
 
 #define mmCPU_IF_NIC_SEI_INTR_CLR 0x4CC1594
 
 #define mmCPU_IF_NIC_SEI_INTR_MASK 0x4CC1598
 
 #define mmCPU_IF_PCIE_SPI_INTR_STS 0x4CC1600
 
 #define mmCPU_IF_PCIE_SPI_INTR_CLR 0x4CC1604
 
 #define mmCPU_IF_PCIE_SPI_INTR_MASK 0x4CC1608
 
 #define mmCPU_IF_MME_SPI_INTR_STS_0 0x4CC1610
 
 #define mmCPU_IF_MME_SPI_INTR_STS_1 0x4CC1614
 
 #define mmCPU_IF_MME_SPI_INTR_STS_2 0x4CC1618
 
 #define mmCPU_IF_MME_SPI_INTR_STS_3 0x4CC161C
 
 #define mmCPU_IF_MME_SPI_INTR_CLR_0 0x4CC1620
 
 #define mmCPU_IF_MME_SPI_INTR_CLR_1 0x4CC1624
 
 #define mmCPU_IF_MME_SPI_INTR_CLR_2 0x4CC1628
 
 #define mmCPU_IF_MME_SPI_INTR_CLR_3 0x4CC162C
 
 #define mmCPU_IF_MME_SPI_INTR_MASK_0 0x4CC1630
 
 #define mmCPU_IF_MME_SPI_INTR_MASK_1 0x4CC1634
 
 #define mmCPU_IF_MME_SPI_INTR_MASK_2 0x4CC1638
 
 #define mmCPU_IF_MME_SPI_INTR_MASK_3 0x4CC163C
 
 #define mmCPU_IF_HMMU_SPI_INTR_STS_0 0x4CC1640
 
 #define mmCPU_IF_HMMU_SPI_INTR_STS_1 0x4CC1644
 
 #define mmCPU_IF_HMMU_SPI_INTR_STS_2 0x4CC1648
 
 #define mmCPU_IF_HMMU_SPI_INTR_STS_3 0x4CC164C
 
 #define mmCPU_IF_HMMU_SPI_INTR_STS_4 0x4CC1650
 
 #define mmCPU_IF_HMMU_SPI_INTR_STS_5 0x4CC1654
 
 #define mmCPU_IF_HMMU_SPI_INTR_STS_6 0x4CC1658
 
 #define mmCPU_IF_HMMU_SPI_INTR_STS_7 0x4CC165C
 
 #define mmCPU_IF_HMMU_SPI_INTR_STS_8 0x4CC1660
 
 #define mmCPU_IF_HMMU_SPI_INTR_STS_9 0x4CC1664
 
 #define mmCPU_IF_HMMU_SPI_INTR_STS_10 0x4CC1668
 
 #define mmCPU_IF_HMMU_SPI_INTR_STS_11 0x4CC166C
 
 #define mmCPU_IF_HMMU_SPI_INTR_STS_12 0x4CC1670
 
 #define mmCPU_IF_HMMU_SPI_INTR_STS_13 0x4CC1674
 
 #define mmCPU_IF_HMMU_SPI_INTR_STS_14 0x4CC1678
 
 #define mmCPU_IF_HMMU_SPI_INTR_STS_15 0x4CC167C
 
 #define mmCPU_IF_HMMU_SPI_INTR_CLR_0 0x4CC1680
 
 #define mmCPU_IF_HMMU_SPI_INTR_CLR_1 0x4CC1684
 
 #define mmCPU_IF_HMMU_SPI_INTR_CLR_2 0x4CC1688
 
 #define mmCPU_IF_HMMU_SPI_INTR_CLR_3 0x4CC168C
 
 #define mmCPU_IF_HMMU_SPI_INTR_CLR_4 0x4CC1690
 
 #define mmCPU_IF_HMMU_SPI_INTR_CLR_5 0x4CC1694
 
 #define mmCPU_IF_HMMU_SPI_INTR_CLR_6 0x4CC1698
 
 #define mmCPU_IF_HMMU_SPI_INTR_CLR_7 0x4CC169C
 
 #define mmCPU_IF_HMMU_SPI_INTR_CLR_8 0x4CC16A0
 
 #define mmCPU_IF_HMMU_SPI_INTR_CLR_9 0x4CC16A4
 
 #define mmCPU_IF_HMMU_SPI_INTR_CLR_10 0x4CC16A8
 
 #define mmCPU_IF_HMMU_SPI_INTR_CLR_11 0x4CC16AC
 
 #define mmCPU_IF_HMMU_SPI_INTR_CLR_12 0x4CC16B0
 
 #define mmCPU_IF_HMMU_SPI_INTR_CLR_13 0x4CC16B4
 
 #define mmCPU_IF_HMMU_SPI_INTR_CLR_14 0x4CC16B8
 
 #define mmCPU_IF_HMMU_SPI_INTR_CLR_15 0x4CC16BC
 
 #define mmCPU_IF_HMMU_SPI_INTR_MASK_0 0x4CC16C0
 
 #define mmCPU_IF_HMMU_SPI_INTR_MASK_1 0x4CC16C4
 
 #define mmCPU_IF_HMMU_SPI_INTR_MASK_2 0x4CC16C8
 
 #define mmCPU_IF_HMMU_SPI_INTR_MASK_3 0x4CC16CC
 
 #define mmCPU_IF_HMMU_SPI_INTR_MASK_4 0x4CC16D0
 
 #define mmCPU_IF_HMMU_SPI_INTR_MASK_5 0x4CC16D4
 
 #define mmCPU_IF_HMMU_SPI_INTR_MASK_6 0x4CC16D8
 
 #define mmCPU_IF_HMMU_SPI_INTR_MASK_7 0x4CC16DC
 
 #define mmCPU_IF_HMMU_SPI_INTR_MASK_8 0x4CC16E0
 
 #define mmCPU_IF_HMMU_SPI_INTR_MASK_9 0x4CC16E4
 
 #define mmCPU_IF_HMMU_SPI_INTR_MASK_10 0x4CC16E8
 
 #define mmCPU_IF_HMMU_SPI_INTR_MASK_11 0x4CC16EC
 
 #define mmCPU_IF_HMMU_SPI_INTR_MASK_12 0x4CC16F0
 
 #define mmCPU_IF_HMMU_SPI_INTR_MASK_13 0x4CC16F4
 
 #define mmCPU_IF_HMMU_SPI_INTR_MASK_14 0x4CC16F8
 
 #define mmCPU_IF_HMMU_SPI_INTR_MASK_15 0x4CC16FC
 
 #define mmCPU_IF_DEC_SPI_INTR_STS_0 0x4CC1700
 
 #define mmCPU_IF_DEC_SPI_INTR_STS_1 0x4CC1704
 
 #define mmCPU_IF_DEC_SPI_INTR_STS_2 0x4CC1708
 
 #define mmCPU_IF_DEC_SPI_INTR_STS_3 0x4CC170C
 
 #define mmCPU_IF_DEC_SPI_INTR_STS_4 0x4CC1710
 
 #define mmCPU_IF_DEC_SPI_INTR_STS_5 0x4CC1714
 
 #define mmCPU_IF_DEC_SPI_INTR_STS_6 0x4CC1718
 
 #define mmCPU_IF_DEC_SPI_INTR_STS_7 0x4CC171C
 
 #define mmCPU_IF_DEC_SPI_INTR_STS_8 0x4CC1720
 
 #define mmCPU_IF_DEC_SPI_INTR_STS_9 0x4CC1724
 
 #define mmCPU_IF_DEC_SPI_INTR_CLR_0 0x4CC1730
 
 #define mmCPU_IF_DEC_SPI_INTR_CLR_1 0x4CC1734
 
 #define mmCPU_IF_DEC_SPI_INTR_CLR_2 0x4CC1738
 
 #define mmCPU_IF_DEC_SPI_INTR_CLR_3 0x4CC173C
 
 #define mmCPU_IF_DEC_SPI_INTR_CLR_4 0x4CC1740
 
 #define mmCPU_IF_DEC_SPI_INTR_CLR_5 0x4CC1744
 
 #define mmCPU_IF_DEC_SPI_INTR_CLR_6 0x4CC1748
 
 #define mmCPU_IF_DEC_SPI_INTR_CLR_7 0x4CC174C
 
 #define mmCPU_IF_DEC_SPI_INTR_CLR_8 0x4CC1750
 
 #define mmCPU_IF_DEC_SPI_INTR_CLR_9 0x4CC1754
 
 #define mmCPU_IF_DEC_SPI_INTR_MASK_0 0x4CC1760
 
 #define mmCPU_IF_DEC_SPI_INTR_MASK_1 0x4CC1764
 
 #define mmCPU_IF_DEC_SPI_INTR_MASK_2 0x4CC1768
 
 #define mmCPU_IF_DEC_SPI_INTR_MASK_3 0x4CC176C
 
 #define mmCPU_IF_DEC_SPI_INTR_MASK_4 0x4CC1770
 
 #define mmCPU_IF_DEC_SPI_INTR_MASK_5 0x4CC1774
 
 #define mmCPU_IF_DEC_SPI_INTR_MASK_6 0x4CC1778
 
 #define mmCPU_IF_DEC_SPI_INTR_MASK_7 0x4CC177C
 
 #define mmCPU_IF_DEC_SPI_INTR_MASK_8 0x4CC1780
 
 #define mmCPU_IF_DEC_SPI_INTR_MASK_9 0x4CC1784
 
 #define mmCPU_IF_HIF_SPI_INTR_STS 0x4CC17A0
 
 #define mmCPU_IF_HIF_SPI_INTR_CLR 0x4CC17A4
 
 #define mmCPU_IF_HIF_SPI_INTR_MASK 0x4CC17A8
 
 #define mmCPU_IF_NIC_SPI_INTR_STS_0 0x4CC17B0
 
 #define mmCPU_IF_NIC_SPI_INTR_STS_1 0x4CC17B4
 
 #define mmCPU_IF_NIC_SPI_INTR_STS_2 0x4CC17B8
 
 #define mmCPU_IF_NIC_SPI_INTR_STS_3 0x4CC17BC
 
 #define mmCPU_IF_NIC_SPI_INTR_STS_4 0x4CC17C0
 
 #define mmCPU_IF_NIC_SPI_INTR_STS_5 0x4CC17C4
 
 #define mmCPU_IF_NIC_SPI_INTR_STS_6 0x4CC17C8
 
 #define mmCPU_IF_NIC_SPI_INTR_STS_7 0x4CC17CC
 
 #define mmCPU_IF_NIC_SPI_INTR_STS_8 0x4CC17D0
 
 #define mmCPU_IF_NIC_SPI_INTR_STS_9 0x4CC17D4
 
 #define mmCPU_IF_NIC_SPI_INTR_STS_10 0x4CC17D8
 
 #define mmCPU_IF_NIC_SPI_INTR_STS_11 0x4CC17DC
 
 #define mmCPU_IF_NIC_SPI_INTR_CLR_0 0x4CC17E0
 
 #define mmCPU_IF_NIC_SPI_INTR_CLR_1 0x4CC17E4
 
 #define mmCPU_IF_NIC_SPI_INTR_CLR_2 0x4CC17E8
 
 #define mmCPU_IF_NIC_SPI_INTR_CLR_3 0x4CC17EC
 
 #define mmCPU_IF_NIC_SPI_INTR_CLR_4 0x4CC17F0
 
 #define mmCPU_IF_NIC_SPI_INTR_CLR_5 0x4CC17F4
 
 #define mmCPU_IF_NIC_SPI_INTR_CLR_6 0x4CC17F8
 
 #define mmCPU_IF_NIC_SPI_INTR_CLR_7 0x4CC17FC
 
 #define mmCPU_IF_NIC_SPI_INTR_CLR_8 0x4CC1800
 
 #define mmCPU_IF_NIC_SPI_INTR_CLR_9 0x4CC1804
 
 #define mmCPU_IF_NIC_SPI_INTR_CLR_10 0x4CC1808
 
 #define mmCPU_IF_NIC_SPI_INTR_CLR_11 0x4CC180C
 
 #define mmCPU_IF_NIC_SPI_INTR_MASK_0 0x4CC1810
 
 #define mmCPU_IF_NIC_SPI_INTR_MASK_1 0x4CC1814
 
 #define mmCPU_IF_NIC_SPI_INTR_MASK_2 0x4CC1818
 
 #define mmCPU_IF_NIC_SPI_INTR_MASK_3 0x4CC181C
 
 #define mmCPU_IF_NIC_SPI_INTR_MASK_4 0x4CC1820
 
 #define mmCPU_IF_NIC_SPI_INTR_MASK_5 0x4CC1824
 
 #define mmCPU_IF_NIC_SPI_INTR_MASK_6 0x4CC1828
 
 #define mmCPU_IF_NIC_SPI_INTR_MASK_7 0x4CC182C
 
 #define mmCPU_IF_NIC_SPI_INTR_MASK_8 0x4CC1830
 
 #define mmCPU_IF_NIC_SPI_INTR_MASK_9 0x4CC1834
 
 #define mmCPU_IF_NIC_SPI_INTR_MASK_10 0x4CC1838
 
 #define mmCPU_IF_NIC_SPI_INTR_MASK_11 0x4CC183C
 
 #define mmCPU_IF_DEC_ECO_INTR_STS 0x4CC1840
 
 #define mmCPU_IF_DEC_ECO_INTR_CLR 0x4CC1844
 
 #define mmCPU_IF_DEC_ECO_INTR_MASK 0x4CC1848
 
 #define mmCPU_IF_HIF_ECO_INTR_STS 0x4CC1850
 
 #define mmCPU_IF_HIF_ECO_INTR_CLR 0x4CC1854
 
 #define mmCPU_IF_HIF_ECO_INTR_MASK 0x4CC1858
 
 #define mmCPU_IF_HMMU_ECO_INTR_STS 0x4CC1860
 
 #define mmCPU_IF_HMMU_ECO_INTR_CLR 0x4CC1864
 
 #define mmCPU_IF_HMMU_ECO_INTR_MASK 0x4CC1868
 
 #define mmCPU_IF_NIC_ECO_INTR_STS 0x4CC1870
 
 #define mmCPU_IF_NIC_ECO_INTR_CLR 0x4CC1874
 
 #define mmCPU_IF_NIC_ECO_INTR_MASK 0x4CC1878
 
 #define mmCPU_IF_MSI_X_INTR_STS_0 0x4CC1900
 
 #define mmCPU_IF_MSI_X_INTR_STS_1 0x4CC1904
 
 #define mmCPU_IF_MSI_X_INTR_STS_2 0x4CC1908
 
 #define mmCPU_IF_MSI_X_INTR_STS_3 0x4CC190C
 
 #define mmCPU_IF_MSI_X_INTR_STS_4 0x4CC1910
 
 #define mmCPU_IF_MSI_X_INTR_STS_5 0x4CC1914
 
 #define mmCPU_IF_MSI_X_INTR_STS_6 0x4CC1918
 
 #define mmCPU_IF_MSI_X_INTR_STS_7 0x4CC191C
 
 #define mmCPU_IF_MSI_X_INTR_STS_8 0x4CC1920
 
 #define mmCPU_IF_MSI_X_INTR_STS_9 0x4CC1924
 
 #define mmCPU_IF_MSI_X_INTR_STS_10 0x4CC1928
 
 #define mmCPU_IF_MSI_X_INTR_STS_11 0x4CC192C
 
 #define mmCPU_IF_MSI_X_INTR_STS_12 0x4CC1930
 
 #define mmCPU_IF_MSI_X_INTR_STS_13 0x4CC1934
 
 #define mmCPU_IF_MSI_X_INTR_STS_14 0x4CC1938
 
 #define mmCPU_IF_MSI_X_INTR_STS_15 0x4CC193C
 
 #define mmCPU_IF_MSI_X_INTR_CLR_0 0x4CC1940
 
 #define mmCPU_IF_MSI_X_INTR_CLR_1 0x4CC1944
 
 #define mmCPU_IF_MSI_X_INTR_CLR_2 0x4CC1948
 
 #define mmCPU_IF_MSI_X_INTR_CLR_3 0x4CC194C
 
 #define mmCPU_IF_MSI_X_INTR_CLR_4 0x4CC1950
 
 #define mmCPU_IF_MSI_X_INTR_CLR_5 0x4CC1954
 
 #define mmCPU_IF_MSI_X_INTR_CLR_6 0x4CC1958
 
 #define mmCPU_IF_MSI_X_INTR_CLR_7 0x4CC195C
 
 #define mmCPU_IF_MSI_X_INTR_CLR_8 0x4CC1960
 
 #define mmCPU_IF_MSI_X_INTR_CLR_9 0x4CC1964
 
 #define mmCPU_IF_MSI_X_INTR_CLR_10 0x4CC1968
 
 #define mmCPU_IF_MSI_X_INTR_CLR_11 0x4CC196C
 
 #define mmCPU_IF_MSI_X_INTR_CLR_12 0x4CC1970
 
 #define mmCPU_IF_MSI_X_INTR_CLR_13 0x4CC1974
 
 #define mmCPU_IF_MSI_X_INTR_CLR_14 0x4CC1978
 
 #define mmCPU_IF_MSI_X_INTR_CLR_15 0x4CC197C
 
 #define mmCPU_IF_MSI_X_INTR_MASK_0 0x4CC1980
 
 #define mmCPU_IF_MSI_X_INTR_MASK_1 0x4CC1984
 
 #define mmCPU_IF_MSI_X_INTR_MASK_2 0x4CC1988
 
 #define mmCPU_IF_MSI_X_INTR_MASK_3 0x4CC198C
 
 #define mmCPU_IF_MSI_X_INTR_MASK_4 0x4CC1990
 
 #define mmCPU_IF_MSI_X_INTR_MASK_5 0x4CC1994
 
 #define mmCPU_IF_MSI_X_INTR_MASK_6 0x4CC1998
 
 #define mmCPU_IF_MSI_X_INTR_MASK_7 0x4CC199C
 
 #define mmCPU_IF_MSI_X_INTR_MASK_8 0x4CC19A0
 
 #define mmCPU_IF_MSI_X_INTR_MASK_9 0x4CC19A4
 
 #define mmCPU_IF_MSI_X_INTR_MASK_10 0x4CC19A8
 
 #define mmCPU_IF_MSI_X_INTR_MASK_11 0x4CC19AC
 
 #define mmCPU_IF_MSI_X_INTR_MASK_12 0x4CC19B0
 
 #define mmCPU_IF_MSI_X_INTR_MASK_13 0x4CC19B4
 
 #define mmCPU_IF_MSI_X_INTR_MASK_14 0x4CC19B8
 
 #define mmCPU_IF_MSI_X_INTR_MASK_15 0x4CC19BC
 
 #define mmCPU_IF_MSI_X_BUSY_INTR_STS 0x4CC19C0
 
 #define mmCPU_IF_MSI_X_BUSY_INTR_CLR 0x4CC19C4
 
 #define mmCPU_IF_MSI_X_BUSY_INTR_MASK 0x4CC19C8
 
 #define mmCPU_IF_MSI_X_GEN_ADDR 0x4CC19D0
 
 #define mmCPU_IF_MSI_X_GEN_DATA 0x4CC19D4
 
 #define mmCPU_IF_MSI_X_GEN_AWPROT 0x4CC19D8
 
 #endif /* ASIC_REG_CPU_IF_REGS_H_ */

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