gaudi2/arc/gaudi2_arc_common_packets.h

0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * Copyright (C) 2020 HabanaLabs Ltd.
0004  * All Rights Reserved.
0005  */
0006
0007 #ifndef __GAUDI2_ARC_COMMON_PACKETS_H__
0008 #define __GAUDI2_ARC_COMMON_PACKETS_H__
0009
0010 /*
0011  * CPU IDs for each ARC CPUs
0012  */
0013
0014 #define CPU_ID_SCHED_ARC0       0   /* FARM_ARC0 */
0015 #define CPU_ID_SCHED_ARC1       1   /* FARM_ARC1 */
0016 #define CPU_ID_SCHED_ARC2       2   /* FARM_ARC2 */
0017 #define CPU_ID_SCHED_ARC3       3   /* FARM_ARC3 */
0018 /* Dcore1 MME Engine ARC instance used as scheduler */
0019 #define CPU_ID_SCHED_ARC4       4   /* DCORE1_MME0 */
0020 /* Dcore3 MME Engine ARC instance used as scheduler */
0021 #define CPU_ID_SCHED_ARC5       5   /* DCORE3_MME0 */
0022
0023 #define CPU_ID_TPC_QMAN_ARC0        6   /* DCORE0_TPC0 */
0024 #define CPU_ID_TPC_QMAN_ARC1        7   /* DCORE0_TPC1 */
0025 #define CPU_ID_TPC_QMAN_ARC2        8   /* DCORE0_TPC2 */
0026 #define CPU_ID_TPC_QMAN_ARC3        9   /* DCORE0_TPC3 */
0027 #define CPU_ID_TPC_QMAN_ARC4        10  /* DCORE0_TPC4 */
0028 #define CPU_ID_TPC_QMAN_ARC5        11  /* DCORE0_TPC5 */
0029 #define CPU_ID_TPC_QMAN_ARC6        12  /* DCORE1_TPC0 */
0030 #define CPU_ID_TPC_QMAN_ARC7        13  /* DCORE1_TPC1 */
0031 #define CPU_ID_TPC_QMAN_ARC8        14  /* DCORE1_TPC2 */
0032 #define CPU_ID_TPC_QMAN_ARC9        15  /* DCORE1_TPC3 */
0033 #define CPU_ID_TPC_QMAN_ARC10       16  /* DCORE1_TPC4 */
0034 #define CPU_ID_TPC_QMAN_ARC11       17  /* DCORE1_TPC5 */
0035 #define CPU_ID_TPC_QMAN_ARC12       18  /* DCORE2_TPC0 */
0036 #define CPU_ID_TPC_QMAN_ARC13       19  /* DCORE2_TPC1 */
0037 #define CPU_ID_TPC_QMAN_ARC14       20  /* DCORE2_TPC2 */
0038 #define CPU_ID_TPC_QMAN_ARC15       21  /* DCORE2_TPC3 */
0039 #define CPU_ID_TPC_QMAN_ARC16       22  /* DCORE2_TPC4 */
0040 #define CPU_ID_TPC_QMAN_ARC17       23  /* DCORE2_TPC5 */
0041 #define CPU_ID_TPC_QMAN_ARC18       24  /* DCORE3_TPC0 */
0042 #define CPU_ID_TPC_QMAN_ARC19       25  /* DCORE3_TPC1 */
0043 #define CPU_ID_TPC_QMAN_ARC20       26  /* DCORE3_TPC2 */
0044 #define CPU_ID_TPC_QMAN_ARC21       27  /* DCORE3_TPC3 */
0045 #define CPU_ID_TPC_QMAN_ARC22       28  /* DCORE3_TPC4 */
0046 #define CPU_ID_TPC_QMAN_ARC23       29  /* DCORE3_TPC5 */
0047 #define CPU_ID_TPC_QMAN_ARC24       30  /* DCORE0_TPC6 - Never present */
0048
0049 #define CPU_ID_MME_QMAN_ARC0        31  /* DCORE0_MME0 */
0050 #define CPU_ID_MME_QMAN_ARC1        32  /* DCORE2_MME0 */
0051
0052 #define CPU_ID_EDMA_QMAN_ARC0       33  /* DCORE0_EDMA0 */
0053 #define CPU_ID_EDMA_QMAN_ARC1       34  /* DCORE0_EDMA1 */
0054 #define CPU_ID_EDMA_QMAN_ARC2       35  /* DCORE1_EDMA0 */
0055 #define CPU_ID_EDMA_QMAN_ARC3       36  /* DCORE1_EDMA1 */
0056 #define CPU_ID_EDMA_QMAN_ARC4       37  /* DCORE2_EDMA0 */
0057 #define CPU_ID_EDMA_QMAN_ARC5       38  /* DCORE2_EDMA1 */
0058 #define CPU_ID_EDMA_QMAN_ARC6       39  /* DCORE3_EDMA0 */
0059 #define CPU_ID_EDMA_QMAN_ARC7       40  /* DCORE3_EDMA1 */
0060
0061 #define CPU_ID_PDMA_QMAN_ARC0       41  /* DCORE0_PDMA0 */
0062 #define CPU_ID_PDMA_QMAN_ARC1       42  /* DCORE0_PDMA1 */
0063
0064 #define CPU_ID_ROT_QMAN_ARC0        43  /* ROT0 */
0065 #define CPU_ID_ROT_QMAN_ARC1        44  /* ROT1 */
0066
0067 #define CPU_ID_NIC_QMAN_ARC0        45  /* NIC0_0 */
0068 #define CPU_ID_NIC_QMAN_ARC1        46  /* NIC0_1 */
0069 #define CPU_ID_NIC_QMAN_ARC2        47  /* NIC1_0 */
0070 #define CPU_ID_NIC_QMAN_ARC3        48  /* NIC1_1 */
0071 #define CPU_ID_NIC_QMAN_ARC4        49  /* NIC2_0 */
0072 #define CPU_ID_NIC_QMAN_ARC5        50  /* NIC2_1 */
0073 #define CPU_ID_NIC_QMAN_ARC6        51  /* NIC3_0 */
0074 #define CPU_ID_NIC_QMAN_ARC7        52  /* NIC3_1 */
0075 #define CPU_ID_NIC_QMAN_ARC8        53  /* NIC4_0 */
0076 #define CPU_ID_NIC_QMAN_ARC9        54  /* NIC4_1 */
0077 #define CPU_ID_NIC_QMAN_ARC10       55  /* NIC5_0 */
0078 #define CPU_ID_NIC_QMAN_ARC11       56  /* NIC5_1 */
0079 #define CPU_ID_NIC_QMAN_ARC12       57  /* NIC6_0 */
0080 #define CPU_ID_NIC_QMAN_ARC13       58  /* NIC6_1 */
0081 #define CPU_ID_NIC_QMAN_ARC14       59  /* NIC7_0 */
0082 #define CPU_ID_NIC_QMAN_ARC15       60  /* NIC7_1 */
0083 #define CPU_ID_NIC_QMAN_ARC16       61  /* NIC8_0 */
0084 #define CPU_ID_NIC_QMAN_ARC17       62  /* NIC8_1 */
0085 #define CPU_ID_NIC_QMAN_ARC18       63  /* NIC9_0 */
0086 #define CPU_ID_NIC_QMAN_ARC19       64  /* NIC9_1 */
0087 #define CPU_ID_NIC_QMAN_ARC20       65  /* NIC10_0 */
0088 #define CPU_ID_NIC_QMAN_ARC21       66  /* NIC10_1 */
0089 #define CPU_ID_NIC_QMAN_ARC22       67  /* NIC11_0 */
0090 #define CPU_ID_NIC_QMAN_ARC23       68  /* NIC11_1 */
0091
0092 #define CPU_ID_MAX          69
0093 #define CPU_ID_SCHED_MAX        6
0094
0095 #define CPU_ID_ALL          0xFE
0096 #define CPU_ID_INVALID          0xFF
0097
0098 enum arc_regions_t {
0099     ARC_REGION0_UNSED  = 0,
0100     /*
0101      * Extension registers
0102      * None
0103      */
0104     ARC_REGION1_SRAM = 1,
0105     /*
0106      * Extension registers
0107      * AUX_SRAM_LSB_ADDR
0108      * AUX_SRAM_MSB_ADDR
0109      * ARC Address: 0x1000_0000
0110      */
0111     ARC_REGION2_CFG = 2,
0112     /*
0113      * Extension registers
0114      * AUX_CFG_LSB_ADDR
0115      * AUX_CFG_MSB_ADDR
0116      * ARC Address: 0x2000_0000
0117      */
0118     ARC_REGION3_GENERAL = 3,
0119     /*
0120      * Extension registers
0121      * AUX_GENERAL_PURPOSE_LSB_ADDR_0
0122      * AUX_GENERAL_PURPOSE_MSB_ADDR_0
0123      * ARC Address: 0x3000_0000
0124      */
0125     ARC_REGION4_HBM0_FW = 4,
0126     /*
0127      * Extension registers
0128      * AUX_HBM0_LSB_ADDR
0129      * AUX_HBM0_MSB_ADDR
0130      * AUX_HBM0_OFFSET
0131      * ARC Address: 0x4000_0000
0132      */
0133     ARC_REGION5_HBM1_GC_DATA = 5,
0134     /*
0135      * Extension registers
0136      * AUX_HBM1_LSB_ADDR
0137      * AUX_HBM1_MSB_ADDR
0138      * AUX_HBM1_OFFSET
0139      * ARC Address: 0x5000_0000
0140      */
0141     ARC_REGION6_HBM2_GC_DATA = 6,
0142     /*
0143      * Extension registers
0144      * AUX_HBM2_LSB_ADDR
0145      * AUX_HBM2_MSB_ADDR
0146      * AUX_HBM2_OFFSET
0147      * ARC Address: 0x6000_0000
0148      */
0149     ARC_REGION7_HBM3_GC_DATA = 7,
0150     /*
0151      * Extension registers
0152      * AUX_HBM3_LSB_ADDR
0153      * AUX_HBM3_MSB_ADDR
0154      * AUX_HBM3_OFFSET
0155      * ARC Address: 0x7000_0000
0156      */
0157     ARC_REGION8_DCCM = 8,
0158     /*
0159      * Extension registers
0160      * None
0161      * ARC Address: 0x8000_0000
0162      */
0163     ARC_REGION9_PCIE = 9,
0164     /*
0165      * Extension registers
0166      * AUX_PCIE_LSB_ADDR
0167      * AUX_PCIE_MSB_ADDR
0168      * ARC Address: 0x9000_0000
0169      */
0170     ARC_REGION10_GENERAL = 10,
0171     /*
0172      * Extension registers
0173      * AUX_GENERAL_PURPOSE_LSB_ADDR_1
0174      * AUX_GENERAL_PURPOSE_MSB_ADDR_1
0175      * ARC Address: 0xA000_0000
0176      */
0177     ARC_REGION11_GENERAL = 11,
0178     /*
0179      * Extension registers
0180      * AUX_GENERAL_PURPOSE_LSB_ADDR_2
0181      * AUX_GENERAL_PURPOSE_MSB_ADDR_2
0182      * ARC Address: 0xB000_0000
0183      */
0184     ARC_REGION12_GENERAL = 12,
0185     /*
0186      * Extension registers
0187      * AUX_GENERAL_PURPOSE_LSB_ADDR_3
0188      * AUX_GENERAL_PURPOSE_MSB_ADDR_3
0189      * ARC Address: 0xC000_0000
0190      */
0191     ARC_REGION13_GENERAL = 13,
0192     /*
0193      * Extension registers
0194      * AUX_GENERAL_PURPOSE_LSB_ADDR_4
0195      * AUX_GENERAL_PURPOSE_MSB_ADDR_4
0196      * ARC Address: 0xD000_0000
0197      */
0198     ARC_REGION14_GENERAL = 14,
0199     /*
0200      * Extension registers
0201      * AUX_GENERAL_PURPOSE_LSB_ADDR_5
0202      * AUX_GENERAL_PURPOSE_MSB_ADDR_5
0203      * ARC Address: 0xE000_0000
0204      */
0205     ARC_REGION15_LBU = 15
0206     /*
0207      * Extension registers
0208      * None
0209      * ARC Address: 0xF000_0000
0210      */
0211 };
0212
0213 #endif /* __GAUDI2_ARC_COMMON_PACKETS_H__ */