Back to home page

OSCL-LXR

 
 

    


0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * Copyright 2018-2020 HabanaLabs, Ltd.
0004  * All Rights Reserved.
0005  *
0006  */
0007 
0008 #ifndef GAUDI_H
0009 #define GAUDI_H
0010 
0011 #define SRAM_BAR_ID     0
0012 #define CFG_BAR_ID      2
0013 #define HBM_BAR_ID      4
0014 
0015 #define SRAM_BAR_SIZE       0x4000000ull        /* 64MB */
0016 #define CFG_BAR_SIZE        0x8000000ull        /* 128MB */
0017 
0018 #define CFG_BASE        0x7FFC000000ull
0019 #define CFG_SIZE        0x4000000       /* 32MB CFG + 32MB DBG*/
0020 
0021 #define SRAM_BASE_ADDR      0x7FF0000000ull
0022 #define SRAM_SIZE       0x1400000       /* 20MB */
0023 
0024 #define SPI_FLASH_BASE_ADDR 0x7FF8000000ull
0025 
0026 #define PSOC_SCRATCHPAD_ADDR    0x7FFBFE0000ull
0027 #define PSOC_SCRATCHPAD_SIZE    0x10000         /* 64KB */
0028 
0029 #define PCIE_FW_SRAM_ADDR   0x7FFBFF0000ull
0030 #define PCIE_FW_SRAM_SIZE   0x8000          /* 32KB */
0031 
0032 #define DRAM_PHYS_BASE      0x0ull
0033 
0034 #define HOST_PHYS_BASE      0x8000000000ull     /* 0.5TB */
0035 #define HOST_PHYS_SIZE      0x1000000000000ull  /* 0.25PB (48 bits) */
0036 
0037 #define GAUDI_MSI_ENTRIES   32
0038 
0039 #define QMAN_PQ_ENTRY_SIZE  16          /* Bytes */
0040 
0041 #define MAX_ASID        2
0042 
0043 #define PROT_BITS_OFFS      0xF80
0044 
0045 #define MME_NUMBER_OF_MASTER_ENGINES    2
0046 
0047 #define MME_NUMBER_OF_SLAVE_ENGINES 2
0048 
0049 #define TPC_NUMBER_OF_ENGINES   8
0050 
0051 #define DMA_NUMBER_OF_CHANNELS  8
0052 
0053 #define NIC_NUMBER_OF_MACROS    5
0054 
0055 #define NIC_NUMBER_OF_ENGINES   (NIC_NUMBER_OF_MACROS * 2)
0056 
0057 #define NUMBER_OF_IF        8
0058 
0059 #define DEVICE_CACHE_LINE_SIZE  128
0060 
0061 #endif /* GAUDI_H */