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0013 #ifndef ASIC_REG_TPC3_QM_REGS_H_
0014 #define ASIC_REG_TPC3_QM_REGS_H_
0015
0016
0017
0018
0019
0020
0021
0022 #define mmTPC3_QM_GLBL_CFG0 0xEC8000
0023
0024 #define mmTPC3_QM_GLBL_CFG1 0xEC8004
0025
0026 #define mmTPC3_QM_GLBL_PROT 0xEC8008
0027
0028 #define mmTPC3_QM_GLBL_ERR_CFG 0xEC800C
0029
0030 #define mmTPC3_QM_GLBL_SECURE_PROPS_0 0xEC8010
0031
0032 #define mmTPC3_QM_GLBL_SECURE_PROPS_1 0xEC8014
0033
0034 #define mmTPC3_QM_GLBL_SECURE_PROPS_2 0xEC8018
0035
0036 #define mmTPC3_QM_GLBL_SECURE_PROPS_3 0xEC801C
0037
0038 #define mmTPC3_QM_GLBL_SECURE_PROPS_4 0xEC8020
0039
0040 #define mmTPC3_QM_GLBL_NON_SECURE_PROPS_0 0xEC8024
0041
0042 #define mmTPC3_QM_GLBL_NON_SECURE_PROPS_1 0xEC8028
0043
0044 #define mmTPC3_QM_GLBL_NON_SECURE_PROPS_2 0xEC802C
0045
0046 #define mmTPC3_QM_GLBL_NON_SECURE_PROPS_3 0xEC8030
0047
0048 #define mmTPC3_QM_GLBL_NON_SECURE_PROPS_4 0xEC8034
0049
0050 #define mmTPC3_QM_GLBL_STS0 0xEC8038
0051
0052 #define mmTPC3_QM_GLBL_STS1_0 0xEC8040
0053
0054 #define mmTPC3_QM_GLBL_STS1_1 0xEC8044
0055
0056 #define mmTPC3_QM_GLBL_STS1_2 0xEC8048
0057
0058 #define mmTPC3_QM_GLBL_STS1_3 0xEC804C
0059
0060 #define mmTPC3_QM_GLBL_STS1_4 0xEC8050
0061
0062 #define mmTPC3_QM_GLBL_MSG_EN_0 0xEC8054
0063
0064 #define mmTPC3_QM_GLBL_MSG_EN_1 0xEC8058
0065
0066 #define mmTPC3_QM_GLBL_MSG_EN_2 0xEC805C
0067
0068 #define mmTPC3_QM_GLBL_MSG_EN_3 0xEC8060
0069
0070 #define mmTPC3_QM_GLBL_MSG_EN_4 0xEC8068
0071
0072 #define mmTPC3_QM_PQ_BASE_LO_0 0xEC8070
0073
0074 #define mmTPC3_QM_PQ_BASE_LO_1 0xEC8074
0075
0076 #define mmTPC3_QM_PQ_BASE_LO_2 0xEC8078
0077
0078 #define mmTPC3_QM_PQ_BASE_LO_3 0xEC807C
0079
0080 #define mmTPC3_QM_PQ_BASE_HI_0 0xEC8080
0081
0082 #define mmTPC3_QM_PQ_BASE_HI_1 0xEC8084
0083
0084 #define mmTPC3_QM_PQ_BASE_HI_2 0xEC8088
0085
0086 #define mmTPC3_QM_PQ_BASE_HI_3 0xEC808C
0087
0088 #define mmTPC3_QM_PQ_SIZE_0 0xEC8090
0089
0090 #define mmTPC3_QM_PQ_SIZE_1 0xEC8094
0091
0092 #define mmTPC3_QM_PQ_SIZE_2 0xEC8098
0093
0094 #define mmTPC3_QM_PQ_SIZE_3 0xEC809C
0095
0096 #define mmTPC3_QM_PQ_PI_0 0xEC80A0
0097
0098 #define mmTPC3_QM_PQ_PI_1 0xEC80A4
0099
0100 #define mmTPC3_QM_PQ_PI_2 0xEC80A8
0101
0102 #define mmTPC3_QM_PQ_PI_3 0xEC80AC
0103
0104 #define mmTPC3_QM_PQ_CI_0 0xEC80B0
0105
0106 #define mmTPC3_QM_PQ_CI_1 0xEC80B4
0107
0108 #define mmTPC3_QM_PQ_CI_2 0xEC80B8
0109
0110 #define mmTPC3_QM_PQ_CI_3 0xEC80BC
0111
0112 #define mmTPC3_QM_PQ_CFG0_0 0xEC80C0
0113
0114 #define mmTPC3_QM_PQ_CFG0_1 0xEC80C4
0115
0116 #define mmTPC3_QM_PQ_CFG0_2 0xEC80C8
0117
0118 #define mmTPC3_QM_PQ_CFG0_3 0xEC80CC
0119
0120 #define mmTPC3_QM_PQ_CFG1_0 0xEC80D0
0121
0122 #define mmTPC3_QM_PQ_CFG1_1 0xEC80D4
0123
0124 #define mmTPC3_QM_PQ_CFG1_2 0xEC80D8
0125
0126 #define mmTPC3_QM_PQ_CFG1_3 0xEC80DC
0127
0128 #define mmTPC3_QM_PQ_ARUSER_31_11_0 0xEC80E0
0129
0130 #define mmTPC3_QM_PQ_ARUSER_31_11_1 0xEC80E4
0131
0132 #define mmTPC3_QM_PQ_ARUSER_31_11_2 0xEC80E8
0133
0134 #define mmTPC3_QM_PQ_ARUSER_31_11_3 0xEC80EC
0135
0136 #define mmTPC3_QM_PQ_STS0_0 0xEC80F0
0137
0138 #define mmTPC3_QM_PQ_STS0_1 0xEC80F4
0139
0140 #define mmTPC3_QM_PQ_STS0_2 0xEC80F8
0141
0142 #define mmTPC3_QM_PQ_STS0_3 0xEC80FC
0143
0144 #define mmTPC3_QM_PQ_STS1_0 0xEC8100
0145
0146 #define mmTPC3_QM_PQ_STS1_1 0xEC8104
0147
0148 #define mmTPC3_QM_PQ_STS1_2 0xEC8108
0149
0150 #define mmTPC3_QM_PQ_STS1_3 0xEC810C
0151
0152 #define mmTPC3_QM_CQ_CFG0_0 0xEC8110
0153
0154 #define mmTPC3_QM_CQ_CFG0_1 0xEC8114
0155
0156 #define mmTPC3_QM_CQ_CFG0_2 0xEC8118
0157
0158 #define mmTPC3_QM_CQ_CFG0_3 0xEC811C
0159
0160 #define mmTPC3_QM_CQ_CFG0_4 0xEC8120
0161
0162 #define mmTPC3_QM_CQ_CFG1_0 0xEC8124
0163
0164 #define mmTPC3_QM_CQ_CFG1_1 0xEC8128
0165
0166 #define mmTPC3_QM_CQ_CFG1_2 0xEC812C
0167
0168 #define mmTPC3_QM_CQ_CFG1_3 0xEC8130
0169
0170 #define mmTPC3_QM_CQ_CFG1_4 0xEC8134
0171
0172 #define mmTPC3_QM_CQ_ARUSER_31_11_0 0xEC8138
0173
0174 #define mmTPC3_QM_CQ_ARUSER_31_11_1 0xEC813C
0175
0176 #define mmTPC3_QM_CQ_ARUSER_31_11_2 0xEC8140
0177
0178 #define mmTPC3_QM_CQ_ARUSER_31_11_3 0xEC8144
0179
0180 #define mmTPC3_QM_CQ_ARUSER_31_11_4 0xEC8148
0181
0182 #define mmTPC3_QM_CQ_STS0_0 0xEC814C
0183
0184 #define mmTPC3_QM_CQ_STS0_1 0xEC8150
0185
0186 #define mmTPC3_QM_CQ_STS0_2 0xEC8154
0187
0188 #define mmTPC3_QM_CQ_STS0_3 0xEC8158
0189
0190 #define mmTPC3_QM_CQ_STS0_4 0xEC815C
0191
0192 #define mmTPC3_QM_CQ_STS1_0 0xEC8160
0193
0194 #define mmTPC3_QM_CQ_STS1_1 0xEC8164
0195
0196 #define mmTPC3_QM_CQ_STS1_2 0xEC8168
0197
0198 #define mmTPC3_QM_CQ_STS1_3 0xEC816C
0199
0200 #define mmTPC3_QM_CQ_STS1_4 0xEC8170
0201
0202 #define mmTPC3_QM_CQ_PTR_LO_0 0xEC8174
0203
0204 #define mmTPC3_QM_CQ_PTR_HI_0 0xEC8178
0205
0206 #define mmTPC3_QM_CQ_TSIZE_0 0xEC817C
0207
0208 #define mmTPC3_QM_CQ_CTL_0 0xEC8180
0209
0210 #define mmTPC3_QM_CQ_PTR_LO_1 0xEC8184
0211
0212 #define mmTPC3_QM_CQ_PTR_HI_1 0xEC8188
0213
0214 #define mmTPC3_QM_CQ_TSIZE_1 0xEC818C
0215
0216 #define mmTPC3_QM_CQ_CTL_1 0xEC8190
0217
0218 #define mmTPC3_QM_CQ_PTR_LO_2 0xEC8194
0219
0220 #define mmTPC3_QM_CQ_PTR_HI_2 0xEC8198
0221
0222 #define mmTPC3_QM_CQ_TSIZE_2 0xEC819C
0223
0224 #define mmTPC3_QM_CQ_CTL_2 0xEC81A0
0225
0226 #define mmTPC3_QM_CQ_PTR_LO_3 0xEC81A4
0227
0228 #define mmTPC3_QM_CQ_PTR_HI_3 0xEC81A8
0229
0230 #define mmTPC3_QM_CQ_TSIZE_3 0xEC81AC
0231
0232 #define mmTPC3_QM_CQ_CTL_3 0xEC81B0
0233
0234 #define mmTPC3_QM_CQ_PTR_LO_4 0xEC81B4
0235
0236 #define mmTPC3_QM_CQ_PTR_HI_4 0xEC81B8
0237
0238 #define mmTPC3_QM_CQ_TSIZE_4 0xEC81BC
0239
0240 #define mmTPC3_QM_CQ_CTL_4 0xEC81C0
0241
0242 #define mmTPC3_QM_CQ_PTR_LO_STS_0 0xEC81C4
0243
0244 #define mmTPC3_QM_CQ_PTR_LO_STS_1 0xEC81C8
0245
0246 #define mmTPC3_QM_CQ_PTR_LO_STS_2 0xEC81CC
0247
0248 #define mmTPC3_QM_CQ_PTR_LO_STS_3 0xEC81D0
0249
0250 #define mmTPC3_QM_CQ_PTR_LO_STS_4 0xEC81D4
0251
0252 #define mmTPC3_QM_CQ_PTR_HI_STS_0 0xEC81D8
0253
0254 #define mmTPC3_QM_CQ_PTR_HI_STS_1 0xEC81DC
0255
0256 #define mmTPC3_QM_CQ_PTR_HI_STS_2 0xEC81E0
0257
0258 #define mmTPC3_QM_CQ_PTR_HI_STS_3 0xEC81E4
0259
0260 #define mmTPC3_QM_CQ_PTR_HI_STS_4 0xEC81E8
0261
0262 #define mmTPC3_QM_CQ_TSIZE_STS_0 0xEC81EC
0263
0264 #define mmTPC3_QM_CQ_TSIZE_STS_1 0xEC81F0
0265
0266 #define mmTPC3_QM_CQ_TSIZE_STS_2 0xEC81F4
0267
0268 #define mmTPC3_QM_CQ_TSIZE_STS_3 0xEC81F8
0269
0270 #define mmTPC3_QM_CQ_TSIZE_STS_4 0xEC81FC
0271
0272 #define mmTPC3_QM_CQ_CTL_STS_0 0xEC8200
0273
0274 #define mmTPC3_QM_CQ_CTL_STS_1 0xEC8204
0275
0276 #define mmTPC3_QM_CQ_CTL_STS_2 0xEC8208
0277
0278 #define mmTPC3_QM_CQ_CTL_STS_3 0xEC820C
0279
0280 #define mmTPC3_QM_CQ_CTL_STS_4 0xEC8210
0281
0282 #define mmTPC3_QM_CQ_IFIFO_CNT_0 0xEC8214
0283
0284 #define mmTPC3_QM_CQ_IFIFO_CNT_1 0xEC8218
0285
0286 #define mmTPC3_QM_CQ_IFIFO_CNT_2 0xEC821C
0287
0288 #define mmTPC3_QM_CQ_IFIFO_CNT_3 0xEC8220
0289
0290 #define mmTPC3_QM_CQ_IFIFO_CNT_4 0xEC8224
0291
0292 #define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_0 0xEC8228
0293
0294 #define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_1 0xEC822C
0295
0296 #define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_2 0xEC8230
0297
0298 #define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_3 0xEC8234
0299
0300 #define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_4 0xEC8238
0301
0302 #define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_0 0xEC823C
0303
0304 #define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_1 0xEC8240
0305
0306 #define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_2 0xEC8244
0307
0308 #define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_3 0xEC8248
0309
0310 #define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_4 0xEC824C
0311
0312 #define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_0 0xEC8250
0313
0314 #define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_1 0xEC8254
0315
0316 #define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_2 0xEC8258
0317
0318 #define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_3 0xEC825C
0319
0320 #define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_4 0xEC8260
0321
0322 #define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_0 0xEC8264
0323
0324 #define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_1 0xEC8268
0325
0326 #define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_2 0xEC826C
0327
0328 #define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_3 0xEC8270
0329
0330 #define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_4 0xEC8274
0331
0332 #define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_0 0xEC8278
0333
0334 #define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_1 0xEC827C
0335
0336 #define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_2 0xEC8280
0337
0338 #define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_3 0xEC8284
0339
0340 #define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_4 0xEC8288
0341
0342 #define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_0 0xEC828C
0343
0344 #define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_1 0xEC8290
0345
0346 #define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_2 0xEC8294
0347
0348 #define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_3 0xEC8298
0349
0350 #define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_4 0xEC829C
0351
0352 #define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_0 0xEC82A0
0353
0354 #define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_1 0xEC82A4
0355
0356 #define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_2 0xEC82A8
0357
0358 #define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_3 0xEC82AC
0359
0360 #define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_4 0xEC82B0
0361
0362 #define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_0 0xEC82B4
0363
0364 #define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_1 0xEC82B8
0365
0366 #define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_2 0xEC82BC
0367
0368 #define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_3 0xEC82C0
0369
0370 #define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_4 0xEC82C4
0371
0372 #define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_0 0xEC82C8
0373
0374 #define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_1 0xEC82CC
0375
0376 #define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_2 0xEC82D0
0377
0378 #define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_3 0xEC82D4
0379
0380 #define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_4 0xEC82D8
0381
0382 #define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xEC82E0
0383
0384 #define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xEC82E4
0385
0386 #define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xEC82E8
0387
0388 #define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xEC82EC
0389
0390 #define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xEC82F0
0391
0392 #define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xEC82F4
0393
0394 #define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xEC82F8
0395
0396 #define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xEC82FC
0397
0398 #define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xEC8300
0399
0400 #define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xEC8304
0401
0402 #define mmTPC3_QM_CP_FENCE0_RDATA_0 0xEC8308
0403
0404 #define mmTPC3_QM_CP_FENCE0_RDATA_1 0xEC830C
0405
0406 #define mmTPC3_QM_CP_FENCE0_RDATA_2 0xEC8310
0407
0408 #define mmTPC3_QM_CP_FENCE0_RDATA_3 0xEC8314
0409
0410 #define mmTPC3_QM_CP_FENCE0_RDATA_4 0xEC8318
0411
0412 #define mmTPC3_QM_CP_FENCE1_RDATA_0 0xEC831C
0413
0414 #define mmTPC3_QM_CP_FENCE1_RDATA_1 0xEC8320
0415
0416 #define mmTPC3_QM_CP_FENCE1_RDATA_2 0xEC8324
0417
0418 #define mmTPC3_QM_CP_FENCE1_RDATA_3 0xEC8328
0419
0420 #define mmTPC3_QM_CP_FENCE1_RDATA_4 0xEC832C
0421
0422 #define mmTPC3_QM_CP_FENCE2_RDATA_0 0xEC8330
0423
0424 #define mmTPC3_QM_CP_FENCE2_RDATA_1 0xEC8334
0425
0426 #define mmTPC3_QM_CP_FENCE2_RDATA_2 0xEC8338
0427
0428 #define mmTPC3_QM_CP_FENCE2_RDATA_3 0xEC833C
0429
0430 #define mmTPC3_QM_CP_FENCE2_RDATA_4 0xEC8340
0431
0432 #define mmTPC3_QM_CP_FENCE3_RDATA_0 0xEC8344
0433
0434 #define mmTPC3_QM_CP_FENCE3_RDATA_1 0xEC8348
0435
0436 #define mmTPC3_QM_CP_FENCE3_RDATA_2 0xEC834C
0437
0438 #define mmTPC3_QM_CP_FENCE3_RDATA_3 0xEC8350
0439
0440 #define mmTPC3_QM_CP_FENCE3_RDATA_4 0xEC8354
0441
0442 #define mmTPC3_QM_CP_FENCE0_CNT_0 0xEC8358
0443
0444 #define mmTPC3_QM_CP_FENCE0_CNT_1 0xEC835C
0445
0446 #define mmTPC3_QM_CP_FENCE0_CNT_2 0xEC8360
0447
0448 #define mmTPC3_QM_CP_FENCE0_CNT_3 0xEC8364
0449
0450 #define mmTPC3_QM_CP_FENCE0_CNT_4 0xEC8368
0451
0452 #define mmTPC3_QM_CP_FENCE1_CNT_0 0xEC836C
0453
0454 #define mmTPC3_QM_CP_FENCE1_CNT_1 0xEC8370
0455
0456 #define mmTPC3_QM_CP_FENCE1_CNT_2 0xEC8374
0457
0458 #define mmTPC3_QM_CP_FENCE1_CNT_3 0xEC8378
0459
0460 #define mmTPC3_QM_CP_FENCE1_CNT_4 0xEC837C
0461
0462 #define mmTPC3_QM_CP_FENCE2_CNT_0 0xEC8380
0463
0464 #define mmTPC3_QM_CP_FENCE2_CNT_1 0xEC8384
0465
0466 #define mmTPC3_QM_CP_FENCE2_CNT_2 0xEC8388
0467
0468 #define mmTPC3_QM_CP_FENCE2_CNT_3 0xEC838C
0469
0470 #define mmTPC3_QM_CP_FENCE2_CNT_4 0xEC8390
0471
0472 #define mmTPC3_QM_CP_FENCE3_CNT_0 0xEC8394
0473
0474 #define mmTPC3_QM_CP_FENCE3_CNT_1 0xEC8398
0475
0476 #define mmTPC3_QM_CP_FENCE3_CNT_2 0xEC839C
0477
0478 #define mmTPC3_QM_CP_FENCE3_CNT_3 0xEC83A0
0479
0480 #define mmTPC3_QM_CP_FENCE3_CNT_4 0xEC83A4
0481
0482 #define mmTPC3_QM_CP_STS_0 0xEC83A8
0483
0484 #define mmTPC3_QM_CP_STS_1 0xEC83AC
0485
0486 #define mmTPC3_QM_CP_STS_2 0xEC83B0
0487
0488 #define mmTPC3_QM_CP_STS_3 0xEC83B4
0489
0490 #define mmTPC3_QM_CP_STS_4 0xEC83B8
0491
0492 #define mmTPC3_QM_CP_CURRENT_INST_LO_0 0xEC83BC
0493
0494 #define mmTPC3_QM_CP_CURRENT_INST_LO_1 0xEC83C0
0495
0496 #define mmTPC3_QM_CP_CURRENT_INST_LO_2 0xEC83C4
0497
0498 #define mmTPC3_QM_CP_CURRENT_INST_LO_3 0xEC83C8
0499
0500 #define mmTPC3_QM_CP_CURRENT_INST_LO_4 0xEC83CC
0501
0502 #define mmTPC3_QM_CP_CURRENT_INST_HI_0 0xEC83D0
0503
0504 #define mmTPC3_QM_CP_CURRENT_INST_HI_1 0xEC83D4
0505
0506 #define mmTPC3_QM_CP_CURRENT_INST_HI_2 0xEC83D8
0507
0508 #define mmTPC3_QM_CP_CURRENT_INST_HI_3 0xEC83DC
0509
0510 #define mmTPC3_QM_CP_CURRENT_INST_HI_4 0xEC83E0
0511
0512 #define mmTPC3_QM_CP_BARRIER_CFG_0 0xEC83F4
0513
0514 #define mmTPC3_QM_CP_BARRIER_CFG_1 0xEC83F8
0515
0516 #define mmTPC3_QM_CP_BARRIER_CFG_2 0xEC83FC
0517
0518 #define mmTPC3_QM_CP_BARRIER_CFG_3 0xEC8400
0519
0520 #define mmTPC3_QM_CP_BARRIER_CFG_4 0xEC8404
0521
0522 #define mmTPC3_QM_CP_DBG_0_0 0xEC8408
0523
0524 #define mmTPC3_QM_CP_DBG_0_1 0xEC840C
0525
0526 #define mmTPC3_QM_CP_DBG_0_2 0xEC8410
0527
0528 #define mmTPC3_QM_CP_DBG_0_3 0xEC8414
0529
0530 #define mmTPC3_QM_CP_DBG_0_4 0xEC8418
0531
0532 #define mmTPC3_QM_CP_ARUSER_31_11_0 0xEC841C
0533
0534 #define mmTPC3_QM_CP_ARUSER_31_11_1 0xEC8420
0535
0536 #define mmTPC3_QM_CP_ARUSER_31_11_2 0xEC8424
0537
0538 #define mmTPC3_QM_CP_ARUSER_31_11_3 0xEC8428
0539
0540 #define mmTPC3_QM_CP_ARUSER_31_11_4 0xEC842C
0541
0542 #define mmTPC3_QM_CP_AWUSER_31_11_0 0xEC8430
0543
0544 #define mmTPC3_QM_CP_AWUSER_31_11_1 0xEC8434
0545
0546 #define mmTPC3_QM_CP_AWUSER_31_11_2 0xEC8438
0547
0548 #define mmTPC3_QM_CP_AWUSER_31_11_3 0xEC843C
0549
0550 #define mmTPC3_QM_CP_AWUSER_31_11_4 0xEC8440
0551
0552 #define mmTPC3_QM_ARB_CFG_0 0xEC8A00
0553
0554 #define mmTPC3_QM_ARB_CHOISE_Q_PUSH 0xEC8A04
0555
0556 #define mmTPC3_QM_ARB_WRR_WEIGHT_0 0xEC8A08
0557
0558 #define mmTPC3_QM_ARB_WRR_WEIGHT_1 0xEC8A0C
0559
0560 #define mmTPC3_QM_ARB_WRR_WEIGHT_2 0xEC8A10
0561
0562 #define mmTPC3_QM_ARB_WRR_WEIGHT_3 0xEC8A14
0563
0564 #define mmTPC3_QM_ARB_CFG_1 0xEC8A18
0565
0566 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_0 0xEC8A20
0567
0568 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_1 0xEC8A24
0569
0570 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_2 0xEC8A28
0571
0572 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_3 0xEC8A2C
0573
0574 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_4 0xEC8A30
0575
0576 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_5 0xEC8A34
0577
0578 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_6 0xEC8A38
0579
0580 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_7 0xEC8A3C
0581
0582 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_8 0xEC8A40
0583
0584 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_9 0xEC8A44
0585
0586 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_10 0xEC8A48
0587
0588 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_11 0xEC8A4C
0589
0590 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_12 0xEC8A50
0591
0592 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_13 0xEC8A54
0593
0594 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_14 0xEC8A58
0595
0596 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_15 0xEC8A5C
0597
0598 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_16 0xEC8A60
0599
0600 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_17 0xEC8A64
0601
0602 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_18 0xEC8A68
0603
0604 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_19 0xEC8A6C
0605
0606 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_20 0xEC8A70
0607
0608 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_21 0xEC8A74
0609
0610 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_22 0xEC8A78
0611
0612 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_23 0xEC8A7C
0613
0614 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_24 0xEC8A80
0615
0616 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_25 0xEC8A84
0617
0618 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_26 0xEC8A88
0619
0620 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_27 0xEC8A8C
0621
0622 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_28 0xEC8A90
0623
0624 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_29 0xEC8A94
0625
0626 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_30 0xEC8A98
0627
0628 #define mmTPC3_QM_ARB_MST_AVAIL_CRED_31 0xEC8A9C
0629
0630 #define mmTPC3_QM_ARB_MST_CRED_INC 0xEC8AA0
0631
0632 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xEC8AA4
0633
0634 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xEC8AA8
0635
0636 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xEC8AAC
0637
0638 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xEC8AB0
0639
0640 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xEC8AB4
0641
0642 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xEC8AB8
0643
0644 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xEC8ABC
0645
0646 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xEC8AC0
0647
0648 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xEC8AC4
0649
0650 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xEC8AC8
0651
0652 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xEC8ACC
0653
0654 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xEC8AD0
0655
0656 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xEC8AD4
0657
0658 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xEC8AD8
0659
0660 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xEC8ADC
0661
0662 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xEC8AE0
0663
0664 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xEC8AE4
0665
0666 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xEC8AE8
0667
0668 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xEC8AEC
0669
0670 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xEC8AF0
0671
0672 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xEC8AF4
0673
0674 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xEC8AF8
0675
0676 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xEC8AFC
0677
0678 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xEC8B00
0679
0680 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xEC8B04
0681
0682 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xEC8B08
0683
0684 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xEC8B0C
0685
0686 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xEC8B10
0687
0688 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xEC8B14
0689
0690 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xEC8B18
0691
0692 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xEC8B1C
0693
0694 #define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xEC8B20
0695
0696 #define mmTPC3_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xEC8B28
0697
0698 #define mmTPC3_QM_ARB_MST_SLAVE_EN 0xEC8B2C
0699
0700 #define mmTPC3_QM_ARB_MST_QUIET_PER 0xEC8B34
0701
0702 #define mmTPC3_QM_ARB_SLV_CHOISE_WDT 0xEC8B38
0703
0704 #define mmTPC3_QM_ARB_SLV_ID 0xEC8B3C
0705
0706 #define mmTPC3_QM_ARB_MSG_MAX_INFLIGHT 0xEC8B44
0707
0708 #define mmTPC3_QM_ARB_MSG_AWUSER_31_11 0xEC8B48
0709
0710 #define mmTPC3_QM_ARB_MSG_AWUSER_SEC_PROP 0xEC8B4C
0711
0712 #define mmTPC3_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xEC8B50
0713
0714 #define mmTPC3_QM_ARB_BASE_LO 0xEC8B54
0715
0716 #define mmTPC3_QM_ARB_BASE_HI 0xEC8B58
0717
0718 #define mmTPC3_QM_ARB_STATE_STS 0xEC8B80
0719
0720 #define mmTPC3_QM_ARB_CHOISE_FULLNESS_STS 0xEC8B84
0721
0722 #define mmTPC3_QM_ARB_MSG_STS 0xEC8B88
0723
0724 #define mmTPC3_QM_ARB_SLV_CHOISE_Q_HEAD 0xEC8B8C
0725
0726 #define mmTPC3_QM_ARB_ERR_CAUSE 0xEC8B9C
0727
0728 #define mmTPC3_QM_ARB_ERR_MSG_EN 0xEC8BA0
0729
0730 #define mmTPC3_QM_ARB_ERR_STS_DRP 0xEC8BA8
0731
0732 #define mmTPC3_QM_ARB_MST_CRED_STS_0 0xEC8BB0
0733
0734 #define mmTPC3_QM_ARB_MST_CRED_STS_1 0xEC8BB4
0735
0736 #define mmTPC3_QM_ARB_MST_CRED_STS_2 0xEC8BB8
0737
0738 #define mmTPC3_QM_ARB_MST_CRED_STS_3 0xEC8BBC
0739
0740 #define mmTPC3_QM_ARB_MST_CRED_STS_4 0xEC8BC0
0741
0742 #define mmTPC3_QM_ARB_MST_CRED_STS_5 0xEC8BC4
0743
0744 #define mmTPC3_QM_ARB_MST_CRED_STS_6 0xEC8BC8
0745
0746 #define mmTPC3_QM_ARB_MST_CRED_STS_7 0xEC8BCC
0747
0748 #define mmTPC3_QM_ARB_MST_CRED_STS_8 0xEC8BD0
0749
0750 #define mmTPC3_QM_ARB_MST_CRED_STS_9 0xEC8BD4
0751
0752 #define mmTPC3_QM_ARB_MST_CRED_STS_10 0xEC8BD8
0753
0754 #define mmTPC3_QM_ARB_MST_CRED_STS_11 0xEC8BDC
0755
0756 #define mmTPC3_QM_ARB_MST_CRED_STS_12 0xEC8BE0
0757
0758 #define mmTPC3_QM_ARB_MST_CRED_STS_13 0xEC8BE4
0759
0760 #define mmTPC3_QM_ARB_MST_CRED_STS_14 0xEC8BE8
0761
0762 #define mmTPC3_QM_ARB_MST_CRED_STS_15 0xEC8BEC
0763
0764 #define mmTPC3_QM_ARB_MST_CRED_STS_16 0xEC8BF0
0765
0766 #define mmTPC3_QM_ARB_MST_CRED_STS_17 0xEC8BF4
0767
0768 #define mmTPC3_QM_ARB_MST_CRED_STS_18 0xEC8BF8
0769
0770 #define mmTPC3_QM_ARB_MST_CRED_STS_19 0xEC8BFC
0771
0772 #define mmTPC3_QM_ARB_MST_CRED_STS_20 0xEC8C00
0773
0774 #define mmTPC3_QM_ARB_MST_CRED_STS_21 0xEC8C04
0775
0776 #define mmTPC3_QM_ARB_MST_CRED_STS_22 0xEC8C08
0777
0778 #define mmTPC3_QM_ARB_MST_CRED_STS_23 0xEC8C0C
0779
0780 #define mmTPC3_QM_ARB_MST_CRED_STS_24 0xEC8C10
0781
0782 #define mmTPC3_QM_ARB_MST_CRED_STS_25 0xEC8C14
0783
0784 #define mmTPC3_QM_ARB_MST_CRED_STS_26 0xEC8C18
0785
0786 #define mmTPC3_QM_ARB_MST_CRED_STS_27 0xEC8C1C
0787
0788 #define mmTPC3_QM_ARB_MST_CRED_STS_28 0xEC8C20
0789
0790 #define mmTPC3_QM_ARB_MST_CRED_STS_29 0xEC8C24
0791
0792 #define mmTPC3_QM_ARB_MST_CRED_STS_30 0xEC8C28
0793
0794 #define mmTPC3_QM_ARB_MST_CRED_STS_31 0xEC8C2C
0795
0796 #define mmTPC3_QM_CGM_CFG 0xEC8C70
0797
0798 #define mmTPC3_QM_CGM_STS 0xEC8C74
0799
0800 #define mmTPC3_QM_CGM_CFG1 0xEC8C78
0801
0802 #define mmTPC3_QM_LOCAL_RANGE_BASE 0xEC8C80
0803
0804 #define mmTPC3_QM_LOCAL_RANGE_SIZE 0xEC8C84
0805
0806 #define mmTPC3_QM_CSMR_STRICT_PRIO_CFG 0xEC8C90
0807
0808 #define mmTPC3_QM_HBW_RD_RATE_LIM_CFG_1 0xEC8C94
0809
0810 #define mmTPC3_QM_LBW_WR_RATE_LIM_CFG_0 0xEC8C98
0811
0812 #define mmTPC3_QM_LBW_WR_RATE_LIM_CFG_1 0xEC8C9C
0813
0814 #define mmTPC3_QM_HBW_RD_RATE_LIM_CFG_0 0xEC8CA0
0815
0816 #define mmTPC3_QM_GLBL_AXCACHE 0xEC8CA4
0817
0818 #define mmTPC3_QM_IND_GW_APB_CFG 0xEC8CB0
0819
0820 #define mmTPC3_QM_IND_GW_APB_WDATA 0xEC8CB4
0821
0822 #define mmTPC3_QM_IND_GW_APB_RDATA 0xEC8CB8
0823
0824 #define mmTPC3_QM_IND_GW_APB_STATUS 0xEC8CBC
0825
0826 #define mmTPC3_QM_GLBL_ERR_ADDR_LO 0xEC8CD0
0827
0828 #define mmTPC3_QM_GLBL_ERR_ADDR_HI 0xEC8CD4
0829
0830 #define mmTPC3_QM_GLBL_ERR_WDATA 0xEC8CD8
0831
0832 #define mmTPC3_QM_GLBL_MEM_INIT_BUSY 0xEC8D00
0833
0834 #endif