OSCL-LXR linux-6.0.1/​drivers/​misc/​habanalabs/​include/​gaudi/​asic_reg/​tpc0_cfg_masks.h	Source navigation Diff markup Identifier search General search
	Version: linux-6.0.1 spark-3.0.0 hadoop-3.2.0-src hadoop-3.3.0-src spark-2.4.7 linux-4.15.13 hadoop-2.7.4-src Revert   Change

 /* SPDX-License-Identifier: GPL-2.0
  *
  * Copyright 2016-2018 HabanaLabs, Ltd.
  * All Rights Reserved.
  *
  */
 
 /************************************
  ** This is an auto-generated file **
  **       DO NOT EDIT BELOW        **
  ************************************/
 
 #ifndef ASIC_REG_TPC0_CFG_MASKS_H_
 #define ASIC_REG_TPC0_CFG_MASKS_H_
 
 /*
  *****************************************
  *   TPC0_CFG (Prototype: TPC)
  *****************************************
  */
 
 /* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW */
 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH */
 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE */
 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG */
 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT        16
 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_SET_SHIFT         19
 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_SET_MASK          0x80000
 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_OP_SHIFT          21
 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_OP_MASK           0x600000
 
 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW */
 #define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH */
 #define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE */
 #define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG */
 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT        16
 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_SET_SHIFT         19
 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_SET_MASK          0x80000
 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_OP_SHIFT          21
 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_OP_MASK           0x600000
 
 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW */
 #define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH */
 #define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE */
 #define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG */
 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT        16
 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_SET_SHIFT         19
 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_SET_MASK          0x80000
 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_OP_SHIFT          21
 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_OP_MASK           0x600000
 
 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW */
 #define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH */
 #define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE */
 #define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG */
 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT        16
 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_SET_SHIFT         19
 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_SET_MASK          0x80000
 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_OP_SHIFT          21
 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_OP_MASK           0x600000
 
 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW */
 #define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH */
 #define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE */
 #define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG */
 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT        16
 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_SET_SHIFT         19
 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_SET_MASK          0x80000
 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_OP_SHIFT          21
 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_OP_MASK           0x600000
 
 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW */
 #define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH */
 #define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE */
 #define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG */
 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT        16
 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_SET_SHIFT         19
 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_SET_MASK          0x80000
 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_OP_SHIFT          21
 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_OP_MASK           0x600000
 
 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW */
 #define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH */
 #define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE */
 #define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG */
 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT        16
 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_SET_SHIFT         19
 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_SET_MASK          0x80000
 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_OP_SHIFT          21
 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_OP_MASK           0x600000
 
 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW */
 #define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH */
 #define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE */
 #define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG */
 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT        16
 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_SET_SHIFT         19
 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_SET_MASK          0x80000
 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_OP_SHIFT          21
 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_OP_MASK           0x600000
 
 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW */
 #define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH */
 #define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE */
 #define TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG */
 #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
 #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
 #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
 #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
 #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_LAST_DIM_SHIFT        16
 #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
 #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_SET_SHIFT         19
 #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_SET_MASK          0x80000
 #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
 #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
 #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_OP_SHIFT          21
 #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_OP_MASK           0x600000
 
 /* TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW */
 #define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH */
 #define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE */
 #define TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG */
 #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
 #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_MASK        0x7
 #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
 #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
 #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_LAST_DIM_SHIFT        16
 #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
 #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_SET_SHIFT         19
 #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_SET_MASK          0x80000
 #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_SHIFT      20
 #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_MASK       0x100000
 #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_OP_SHIFT          21
 #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_OP_MASK           0x600000
 
 /* TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW */
 #define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH */
 #define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH_V_SHIFT             0
 #define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH_V_MASK              0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE */
 #define TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG */
 #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_SHIFT      0
 #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_MASK       0x7
 #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
 #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_MASK  0x1F00
 #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_LAST_DIM_SHIFT       16
 #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_LAST_DIM_MASK        0x70000
 #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_SET_SHIFT        19
 #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_SET_MASK         0x80000
 #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_SHIFT     20
 #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_MASK      0x100000
 #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_OP_SHIFT         21
 #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_OP_MASK          0x600000
 
 /* TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW */
 #define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH */
 #define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH_V_SHIFT             0
 #define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH_V_MASK              0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE */
 #define TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG */
 #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_SHIFT      0
 #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_MASK       0x7
 #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
 #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_MASK  0x1F00
 #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_LAST_DIM_SHIFT       16
 #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_LAST_DIM_MASK        0x70000
 #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_SET_SHIFT        19
 #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_SET_MASK         0x80000
 #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_SHIFT     20
 #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_MASK      0x100000
 #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_OP_SHIFT         21
 #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_OP_MASK          0x600000
 
 /* TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW */
 #define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH */
 #define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH_V_SHIFT             0
 #define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH_V_MASK              0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE */
 #define TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG */
 #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_SHIFT      0
 #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_MASK       0x7
 #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
 #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_MASK  0x1F00
 #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_LAST_DIM_SHIFT       16
 #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_LAST_DIM_MASK        0x70000
 #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_SET_SHIFT        19
 #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_SET_MASK         0x80000
 #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_SHIFT     20
 #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_MASK      0x100000
 #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_OP_SHIFT         21
 #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_OP_MASK          0x600000
 
 /* TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW */
 #define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH */
 #define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH_V_SHIFT             0
 #define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH_V_MASK              0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE */
 #define TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG */
 #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_SHIFT      0
 #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_MASK       0x7
 #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
 #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_MASK  0x1F00
 #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_LAST_DIM_SHIFT       16
 #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_LAST_DIM_MASK        0x70000
 #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_SET_SHIFT        19
 #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_SET_MASK         0x80000
 #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_SHIFT     20
 #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_MASK      0x100000
 #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_OP_SHIFT         21
 #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_OP_MASK          0x600000
 
 /* TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW */
 #define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH */
 #define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH_V_SHIFT             0
 #define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH_V_MASK              0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE */
 #define TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG */
 #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_SHIFT      0
 #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_MASK       0x7
 #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
 #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_MASK  0x1F00
 #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_LAST_DIM_SHIFT       16
 #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_LAST_DIM_MASK        0x70000
 #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_SET_SHIFT        19
 #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_SET_MASK         0x80000
 #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_SHIFT     20
 #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_MASK      0x100000
 #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_OP_SHIFT         21
 #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_OP_MASK          0x600000
 
 /* TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW */
 #define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH */
 #define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH_V_SHIFT             0
 #define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH_V_MASK              0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE */
 #define TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG */
 #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_SHIFT      0
 #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_MASK       0x7
 #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8
 #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_MASK  0x1F00
 #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_LAST_DIM_SHIFT       16
 #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_LAST_DIM_MASK        0x70000
 #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_SET_SHIFT        19
 #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_SET_MASK         0x80000
 #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_SHIFT     20
 #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_MASK      0x100000
 #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_OP_SHIFT         21
 #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_OP_MASK          0x600000
 
 /* TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE_V_SHIFT                 0
 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE */
 #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT     0
 #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK      0xFFFF
 #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_RSV_SHIFT                16
 #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_RSV_MASK                 0x1FFF0000
 #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT       29
 #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK        0xE0000000
 
 /* TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR */
 #define TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR_V_SHIFT                     0
 #define TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW */
 #define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_SHIFT              0
 #define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH */
 #define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT             0
 #define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_MASK              0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TID_BASE_DIM_0 */
 #define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_SHIFT                       0
 #define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_MASK                        0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TID_SIZE_DIM_0 */
 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_SHIFT                       0
 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_MASK                        0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TID_BASE_DIM_1 */
 #define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_SHIFT                       0
 #define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_MASK                        0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TID_SIZE_DIM_1 */
 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_SHIFT                       0
 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_MASK                        0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TID_BASE_DIM_2 */
 #define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_SHIFT                       0
 #define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_MASK                        0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TID_SIZE_DIM_2 */
 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_SHIFT                       0
 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_MASK                        0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TID_BASE_DIM_3 */
 #define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_SHIFT                       0
 #define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_MASK                        0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TID_SIZE_DIM_3 */
 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_SHIFT                       0
 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_MASK                        0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TID_BASE_DIM_4 */
 #define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_SHIFT                       0
 #define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_MASK                        0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TID_SIZE_DIM_4 */
 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_SHIFT                       0
 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_MASK                        0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_KERNEL_CONFIG */
 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_SHIFT                0
 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_MASK                 0x1
 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT             1
 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_MASK              0x2
 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT           2
 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_MASK            0xFC
 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_SHIFT  8
 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_MASK   0xFF00
 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_SHIFT  16
 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_MASK   0xFF0000
 
 /* TPC0_CFG_KERNEL_KERNEL_ID */
 #define TPC0_CFG_KERNEL_KERNEL_ID_V_SHIFT                            0
 #define TPC0_CFG_KERNEL_KERNEL_ID_V_MASK                             0xFFFF
 
 /* TPC0_CFG_KERNEL_SRF */
 #define TPC0_CFG_KERNEL_SRF_V_SHIFT                                  0
 #define TPC0_CFG_KERNEL_SRF_V_MASK                                   0xFFFFFFFF
 
 /* TPC0_CFG_ROUND_CSR */
 #define TPC0_CFG_ROUND_CSR_MODE_SHIFT                                0
 #define TPC0_CFG_ROUND_CSR_MODE_MASK                                 0x7
 
 /* TPC0_CFG_PROT */
 #define TPC0_CFG_PROT_AWPROT_SHIFT                                   0
 #define TPC0_CFG_PROT_AWPROT_MASK                                    0x7
 #define TPC0_CFG_PROT_ARPROT_SHIFT                                   3
 #define TPC0_CFG_PROT_ARPROT_MASK                                    0x38
 
 /* TPC0_CFG_SEMAPHORE */
 #define TPC0_CFG_SEMAPHORE_V_SHIFT                                   0
 #define TPC0_CFG_SEMAPHORE_V_MASK                                    0xFFFFFFFF
 
 /* TPC0_CFG_VFLAGS */
 #define TPC0_CFG_VFLAGS_V_SHIFT                                      0
 #define TPC0_CFG_VFLAGS_V_MASK                                       0xF
 
 /* TPC0_CFG_SFLAGS */
 #define TPC0_CFG_SFLAGS_V_SHIFT                                      0
 #define TPC0_CFG_SFLAGS_V_MASK                                       0xF
 
 /* TPC0_CFG_LFSR_POLYNOM */
 #define TPC0_CFG_LFSR_POLYNOM_V_SHIFT                                0
 #define TPC0_CFG_LFSR_POLYNOM_V_MASK                                 0xFFFFFFFF
 
 /* TPC0_CFG_STATUS */
 #define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT                      1
 #define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK                       0x2
 #define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT                      2
 #define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK                       0x4
 #define TPC0_CFG_STATUS_IQ_EMPTY_SHIFT                               3
 #define TPC0_CFG_STATUS_IQ_EMPTY_MASK                                0x8
 #define TPC0_CFG_STATUS_SB_EMPTY_SHIFT                               5
 #define TPC0_CFG_STATUS_SB_EMPTY_MASK                                0x20
 #define TPC0_CFG_STATUS_QM_IDLE_SHIFT                                6
 #define TPC0_CFG_STATUS_QM_IDLE_MASK                                 0x40
 #define TPC0_CFG_STATUS_QM_RDY_SHIFT                                 7
 #define TPC0_CFG_STATUS_QM_RDY_MASK                                  0x80
 
 /* TPC0_CFG_CFG_BASE_ADDRESS_HIGH */
 #define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_SHIFT                       0
 #define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_MASK                        0xFFFFFFFF
 
 /* TPC0_CFG_CFG_SUBTRACT_VALUE */
 #define TPC0_CFG_CFG_SUBTRACT_VALUE_V_SHIFT                          0
 #define TPC0_CFG_CFG_SUBTRACT_VALUE_V_MASK                           0xFFFFFFFF
 
 /* TPC0_CFG_SM_BASE_ADDRESS_HIGH */
 #define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_SHIFT                        0
 #define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_MASK                         0xFFFFFFFF
 
 /* TPC0_CFG_TPC_CMD */
 #define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_SHIFT                     0
 #define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_MASK                      0x1
 #define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_SHIFT                     1
 #define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_MASK                      0x2
 #define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_SHIFT                     2
 #define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_MASK                      0x4
 #define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_SHIFT                     3
 #define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_MASK                      0x8
 #define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT                  4
 #define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_MASK                   0x10
 #define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_SHIFT                  5
 #define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_MASK                   0x20
 #define TPC0_CFG_TPC_CMD_QMAN_STOP_SHIFT                             6
 #define TPC0_CFG_TPC_CMD_QMAN_STOP_MASK                              0x40
 
 /* TPC0_CFG_TPC_EXECUTE */
 #define TPC0_CFG_TPC_EXECUTE_V_SHIFT                                 0
 #define TPC0_CFG_TPC_EXECUTE_V_MASK                                  0x1
 
 /* TPC0_CFG_TPC_STALL */
 #define TPC0_CFG_TPC_STALL_V_SHIFT                                   0
 #define TPC0_CFG_TPC_STALL_V_MASK                                    0x1
 
 /* TPC0_CFG_ICACHE_BASE_ADDERESS_LOW */
 #define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_SHIFT                    0
 #define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH */
 #define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_SHIFT                   0
 #define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_RD_RATE_LIMIT */
 #define TPC0_CFG_RD_RATE_LIMIT_ENABLE_SHIFT                          0
 #define TPC0_CFG_RD_RATE_LIMIT_ENABLE_MASK                           0x1
 #define TPC0_CFG_RD_RATE_LIMIT_SATURATION_SHIFT                      1
 #define TPC0_CFG_RD_RATE_LIMIT_SATURATION_MASK                       0x1FE
 #define TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_SHIFT                         9
 #define TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_MASK                          0x1FE00
 
 /* TPC0_CFG_WR_RATE_LIMIT */
 #define TPC0_CFG_WR_RATE_LIMIT_ENABLE_SHIFT                          0
 #define TPC0_CFG_WR_RATE_LIMIT_ENABLE_MASK                           0x1
 #define TPC0_CFG_WR_RATE_LIMIT_SATURATION_SHIFT                      1
 #define TPC0_CFG_WR_RATE_LIMIT_SATURATION_MASK                       0x1FE
 #define TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_SHIFT                         9
 #define TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_MASK                          0x1FE00
 
 /* TPC0_CFG_MSS_CONFIG */
 #define TPC0_CFG_MSS_CONFIG_AWCACHE_SHIFT                            0
 #define TPC0_CFG_MSS_CONFIG_AWCACHE_MASK                             0xF
 #define TPC0_CFG_MSS_CONFIG_ARCACHE_SHIFT                            4
 #define TPC0_CFG_MSS_CONFIG_ARCACHE_MASK                             0xF0
 #define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_SHIFT              8
 #define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_MASK               0x300
 #define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_SHIFT                   10
 #define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_MASK                    0x400
 #define TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_SHIFT                11
 #define TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_MASK                 0x800
 
 /* TPC0_CFG_TPC_INTR_CAUSE */
 #define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_SHIFT                          0
 #define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK                           0xFFFFF
 
 /* TPC0_CFG_TPC_INTR_MASK */
 #define TPC0_CFG_TPC_INTR_MASK_MASK_SHIFT                            0
 #define TPC0_CFG_TPC_INTR_MASK_MASK_MASK                             0xFFFFF
 
 /* TPC0_CFG_WQ_CREDITS */
 #define TPC0_CFG_WQ_CREDITS_ST_G_SHIFT                               0
 #define TPC0_CFG_WQ_CREDITS_ST_G_MASK                                0xF
 #define TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_SHIFT                        4
 #define TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_MASK                         0x70
 
 /* TPC0_CFG_ARUSER_LO */
 #define TPC0_CFG_ARUSER_LO_V_SHIFT                                   0
 #define TPC0_CFG_ARUSER_LO_V_MASK                                    0x7FF
 
 /* TPC0_CFG_ARUSER_HI */
 #define TPC0_CFG_ARUSER_HI_V_SHIFT                                   11
 #define TPC0_CFG_ARUSER_HI_V_MASK                                    0x1800
 #define TPC0_CFG_ARUSER_HI_RSRV_SHIFT                                13
 #define TPC0_CFG_ARUSER_HI_RSRV_MASK                                 0xFFFFE000
 
 /* TPC0_CFG_AWUSER_LO */
 #define TPC0_CFG_AWUSER_LO_V_SHIFT                                   0
 #define TPC0_CFG_AWUSER_LO_V_MASK                                    0x7FF
 
 /* TPC0_CFG_AWUSER_HI */
 #define TPC0_CFG_AWUSER_HI_V_SHIFT                                   11
 #define TPC0_CFG_AWUSER_HI_V_MASK                                    0x1800
 #define TPC0_CFG_AWUSER_HI_RSRV_SHIFT                                13
 #define TPC0_CFG_AWUSER_HI_RSRV_MASK                                 0xFFFFE000
 
 /* TPC0_CFG_OPCODE_EXEC */
 #define TPC0_CFG_OPCODE_EXEC_SPU_OP_SHIFT                            0
 #define TPC0_CFG_OPCODE_EXEC_SPU_OP_MASK                             0x7F
 #define TPC0_CFG_OPCODE_EXEC_SPU_EN_SHIFT                            7
 #define TPC0_CFG_OPCODE_EXEC_SPU_EN_MASK                             0x80
 #define TPC0_CFG_OPCODE_EXEC_VPU_OP_SHIFT                            8
 #define TPC0_CFG_OPCODE_EXEC_VPU_OP_MASK                             0x7F00
 #define TPC0_CFG_OPCODE_EXEC_VPU_EN_SHIFT                            15
 #define TPC0_CFG_OPCODE_EXEC_VPU_EN_MASK                             0x8000
 #define TPC0_CFG_OPCODE_EXEC_LD_OP_SHIFT                             16
 #define TPC0_CFG_OPCODE_EXEC_LD_OP_MASK                              0x7F0000
 #define TPC0_CFG_OPCODE_EXEC_LD_EN_SHIFT                             23
 #define TPC0_CFG_OPCODE_EXEC_LD_EN_MASK                              0x800000
 #define TPC0_CFG_OPCODE_EXEC_ST_OP_SHIFT                             24
 #define TPC0_CFG_OPCODE_EXEC_ST_OP_MASK                              0x7F000000
 #define TPC0_CFG_OPCODE_EXEC_ST_EN_SHIFT                             31
 #define TPC0_CFG_OPCODE_EXEC_ST_EN_MASK                              0x80000000
 
 /* TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO */
 #define TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_SHIFT                     0
 #define TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI */
 #define TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_SHIFT                     0
 #define TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO */
 #define TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_SHIFT                     0
 #define TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI */
 #define TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_SHIFT                     0
 #define TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO */
 #define TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_SHIFT                    0
 #define TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI */
 #define TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_SHIFT                    0
 #define TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO */
 #define TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_SHIFT                    0
 #define TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI */
 #define TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_SHIFT                    0
 #define TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_TSB_CFG_MAX_SIZE */
 #define TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_SHIFT                         0
 #define TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_MASK                          0xFFFF
 #define TPC0_CFG_TSB_CFG_MAX_SIZE_MD_SHIFT                           16
 #define TPC0_CFG_TSB_CFG_MAX_SIZE_MD_MASK                            0xFFFF0000
 
 /* TPC0_CFG_TSB_CFG */
 #define TPC0_CFG_TSB_CFG_FORCE_MISS_SHIFT                            0
 #define TPC0_CFG_TSB_CFG_FORCE_MISS_MASK                             0x1
 #define TPC0_CFG_TSB_CFG_MAX_OS_SHIFT                                1
 #define TPC0_CFG_TSB_CFG_MAX_OS_MASK                                 0x1FFFE
 
 /* TPC0_CFG_DBGMEM_ADD */
 #define TPC0_CFG_DBGMEM_ADD_V_SHIFT                                  0
 #define TPC0_CFG_DBGMEM_ADD_V_MASK                                   0xFFFFFFFF
 
 /* TPC0_CFG_DBGMEM_DATA_WR */
 #define TPC0_CFG_DBGMEM_DATA_WR_V_SHIFT                              0
 #define TPC0_CFG_DBGMEM_DATA_WR_V_MASK                               0xFFFFFFFF
 
 /* TPC0_CFG_DBGMEM_DATA_RD */
 #define TPC0_CFG_DBGMEM_DATA_RD_V_SHIFT                              0
 #define TPC0_CFG_DBGMEM_DATA_RD_V_MASK                               0xFFFFFFFF
 
 /* TPC0_CFG_DBGMEM_CTRL */
 #define TPC0_CFG_DBGMEM_CTRL_WR_NRD_SHIFT                            0
 #define TPC0_CFG_DBGMEM_CTRL_WR_NRD_MASK                             0x1
 
 /* TPC0_CFG_DBGMEM_RC */
 #define TPC0_CFG_DBGMEM_RC_VALID_SHIFT                               0
 #define TPC0_CFG_DBGMEM_RC_VALID_MASK                                0x1
 
 /* TPC0_CFG_TSB_INFLIGHT_CNTR */
 #define TPC0_CFG_TSB_INFLIGHT_CNTR_V_SHIFT                           0
 #define TPC0_CFG_TSB_INFLIGHT_CNTR_V_MASK                            0xFFFFFFFF
 
 /* TPC0_CFG_WQ_INFLIGHT_CNTR */
 #define TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_SHIFT                          0
 #define TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_MASK                           0xFFFF
 #define TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_SHIFT                          16
 #define TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_MASK                           0xF0000
 
 /* TPC0_CFG_WQ_LBW_TOTAL_CNTR */
 #define TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_SHIFT                           0
 #define TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_MASK                            0xFFFFFFFF
 
 /* TPC0_CFG_WQ_HBW_TOTAL_CNTR */
 #define TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_SHIFT                           0
 #define TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_MASK                            0xFFFFFFFF
 
 /* TPC0_CFG_IRQ_OCCOUPY_CNTR */
 #define TPC0_CFG_IRQ_OCCOUPY_CNTR_V_SHIFT                            0
 #define TPC0_CFG_IRQ_OCCOUPY_CNTR_V_MASK                             0xFFFFFFFF
 
 /* TPC0_CFG_FUNC_MBIST_CNTRL */
 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT                  0
 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_MASK                   0x1
 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_SHIFT                   1
 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK                    0x2
 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_SHIFT                 2
 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK                  0x4
 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_SHIFT                 16
 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_MASK                  0x3FF0000
 
 /* TPC0_CFG_FUNC_MBIST_PAT */
 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_SHIFT            0
 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_MASK             0x3
 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_SHIFT             2
 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_MASK              0xC
 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_SHIFT            4
 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_MASK             0x30
 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_SHIFT             6
 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_MASK              0xC0
 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_SHIFT            8
 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_MASK             0x300
 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_SHIFT             10
 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_MASK              0xC00
 
 /* TPC0_CFG_FUNC_MBIST_MEM */
 #define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_SHIFT                       0
 #define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_MASK                        0x7FF
 #define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_SHIFT                     12
 #define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_MASK                      0x7000
 #define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_SHIFT               16
 #define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_MASK                0x7FF0000
 #define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_SHIFT            28
 #define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_MASK             0x70000000
 
 /* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW */
 #define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH */
 #define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_PADDING_VALUE */
 #define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG */
 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT            16
 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_SET_SHIFT             19
 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_SET_MASK              0x80000
 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_OP_SHIFT              21
 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_OP_MASK               0x600000
 
 /* TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE */
 #define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE */
 #define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE */
 #define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE */
 #define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE */
 #define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE */
 #define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE */
 #define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE */
 #define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE */
 #define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE */
 #define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW */
 #define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH */
 #define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_PADDING_VALUE */
 #define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG */
 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT            16
 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_SET_SHIFT             19
 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_SET_MASK              0x80000
 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_OP_SHIFT              21
 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_OP_MASK               0x600000
 
 /* TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE */
 #define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE */
 #define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE */
 #define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE */
 #define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE */
 #define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE */
 #define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE */
 #define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE */
 #define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE */
 #define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE */
 #define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW */
 #define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH */
 #define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_PADDING_VALUE */
 #define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG */
 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT            16
 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_SET_SHIFT             19
 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_SET_MASK              0x80000
 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_OP_SHIFT              21
 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_OP_MASK               0x600000
 
 /* TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE */
 #define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE */
 #define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE */
 #define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE */
 #define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE */
 #define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE */
 #define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE */
 #define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE */
 #define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE */
 #define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE */
 #define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW */
 #define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH */
 #define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_PADDING_VALUE */
 #define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG */
 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT            16
 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_SET_SHIFT             19
 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_SET_MASK              0x80000
 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_OP_SHIFT              21
 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_OP_MASK               0x600000
 
 /* TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE */
 #define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE */
 #define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE */
 #define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE */
 #define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE */
 #define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE */
 #define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE */
 #define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE */
 #define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE */
 #define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE */
 #define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW */
 #define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH */
 #define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_PADDING_VALUE */
 #define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG */
 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT            16
 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_SET_SHIFT             19
 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_SET_MASK              0x80000
 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_OP_SHIFT              21
 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_OP_MASK               0x600000
 
 /* TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE */
 #define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE */
 #define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE */
 #define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE */
 #define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE */
 #define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE */
 #define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE */
 #define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE */
 #define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE */
 #define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE */
 #define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW */
 #define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH */
 #define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_PADDING_VALUE */
 #define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG */
 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT            16
 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_SET_SHIFT             19
 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_SET_MASK              0x80000
 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_OP_SHIFT              21
 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_OP_MASK               0x600000
 
 /* TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE */
 #define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE */
 #define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE */
 #define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE */
 #define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE */
 #define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE */
 #define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE */
 #define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE */
 #define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE */
 #define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE */
 #define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW */
 #define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH */
 #define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_PADDING_VALUE */
 #define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG */
 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT            16
 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_SET_SHIFT             19
 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_SET_MASK              0x80000
 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_OP_SHIFT              21
 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_OP_MASK               0x600000
 
 /* TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE */
 #define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE */
 #define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE */
 #define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE */
 #define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE */
 #define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE */
 #define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE */
 #define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE */
 #define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE */
 #define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE */
 #define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW */
 #define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH */
 #define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_PADDING_VALUE */
 #define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG */
 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT            16
 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_SET_SHIFT             19
 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_SET_MASK              0x80000
 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_OP_SHIFT              21
 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_OP_MASK               0x600000
 
 /* TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE */
 #define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE */
 #define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE */
 #define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE */
 #define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE */
 #define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE */
 #define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE */
 #define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE */
 #define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE */
 #define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE */
 #define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW */
 #define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH */
 #define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_8_PADDING_VALUE */
 #define TPC0_CFG_QM_TENSOR_8_PADDING_VALUE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_8_PADDING_VALUE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG */
 #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
 #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
 #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
 #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
 #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_LAST_DIM_SHIFT            16
 #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
 #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_SET_SHIFT             19
 #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_SET_MASK              0x80000
 #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
 #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
 #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_OP_SHIFT              21
 #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_OP_MASK               0x600000
 
 /* TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE */
 #define TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE */
 #define TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE */
 #define TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE */
 #define TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE */
 #define TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE */
 #define TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE */
 #define TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE */
 #define TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE */
 #define TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE */
 #define TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW */
 #define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH */
 #define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_9_PADDING_VALUE */
 #define TPC0_CFG_QM_TENSOR_9_PADDING_VALUE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_9_PADDING_VALUE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG */
 #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
 #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_MASK            0x7
 #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
 #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
 #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_LAST_DIM_SHIFT            16
 #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
 #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_SET_SHIFT             19
 #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_SET_MASK              0x80000
 #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_SHIFT          20
 #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_MASK           0x100000
 #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_OP_SHIFT              21
 #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_OP_MASK               0x600000
 
 /* TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE */
 #define TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE */
 #define TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE */
 #define TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE */
 #define TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE */
 #define TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE */
 #define TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE */
 #define TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE */
 #define TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE */
 #define TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE */
 #define TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW */
 #define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH */
 #define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH_V_SHIFT                 0
 #define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_10_PADDING_VALUE */
 #define TPC0_CFG_QM_TENSOR_10_PADDING_VALUE_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_10_PADDING_VALUE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG */
 #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_SHIFT          0
 #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_MASK           0x7
 #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT     8
 #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_MASK      0x1F00
 #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_LAST_DIM_SHIFT           16
 #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_LAST_DIM_MASK            0x70000
 #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_SET_SHIFT            19
 #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_SET_MASK             0x80000
 #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_SHIFT         20
 #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_MASK          0x100000
 #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_OP_SHIFT             21
 #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_OP_MASK              0x600000
 
 /* TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE */
 #define TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE */
 #define TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE */
 #define TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE */
 #define TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE */
 #define TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE */
 #define TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE */
 #define TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE */
 #define TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE */
 #define TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE */
 #define TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW */
 #define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH */
 #define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH_V_SHIFT                 0
 #define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_11_PADDING_VALUE */
 #define TPC0_CFG_QM_TENSOR_11_PADDING_VALUE_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_11_PADDING_VALUE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG */
 #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_SHIFT          0
 #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_MASK           0x7
 #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT     8
 #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_MASK      0x1F00
 #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_LAST_DIM_SHIFT           16
 #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_LAST_DIM_MASK            0x70000
 #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_SET_SHIFT            19
 #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_SET_MASK             0x80000
 #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_SHIFT         20
 #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_MASK          0x100000
 #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_OP_SHIFT             21
 #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_OP_MASK              0x600000
 
 /* TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE */
 #define TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE */
 #define TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE */
 #define TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE */
 #define TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE */
 #define TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE */
 #define TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE */
 #define TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE */
 #define TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE */
 #define TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE */
 #define TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW */
 #define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH */
 #define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH_V_SHIFT                 0
 #define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_12_PADDING_VALUE */
 #define TPC0_CFG_QM_TENSOR_12_PADDING_VALUE_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_12_PADDING_VALUE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG */
 #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_SHIFT          0
 #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_MASK           0x7
 #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT     8
 #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_MASK      0x1F00
 #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_LAST_DIM_SHIFT           16
 #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_LAST_DIM_MASK            0x70000
 #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_SET_SHIFT            19
 #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_SET_MASK             0x80000
 #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_SHIFT         20
 #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_MASK          0x100000
 #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_OP_SHIFT             21
 #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_OP_MASK              0x600000
 
 /* TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE */
 #define TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE */
 #define TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE */
 #define TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE */
 #define TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE */
 #define TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE */
 #define TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE */
 #define TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE */
 #define TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE */
 #define TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE */
 #define TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW */
 #define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH */
 #define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH_V_SHIFT                 0
 #define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_13_PADDING_VALUE */
 #define TPC0_CFG_QM_TENSOR_13_PADDING_VALUE_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_13_PADDING_VALUE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG */
 #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_SHIFT          0
 #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_MASK           0x7
 #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT     8
 #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_MASK      0x1F00
 #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_LAST_DIM_SHIFT           16
 #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_LAST_DIM_MASK            0x70000
 #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_SET_SHIFT            19
 #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_SET_MASK             0x80000
 #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_SHIFT         20
 #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_MASK          0x100000
 #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_OP_SHIFT             21
 #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_OP_MASK              0x600000
 
 /* TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE */
 #define TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE */
 #define TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE */
 #define TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE */
 #define TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE */
 #define TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE */
 #define TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE */
 #define TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE */
 #define TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE */
 #define TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE */
 #define TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW */
 #define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH */
 #define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH_V_SHIFT                 0
 #define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_14_PADDING_VALUE */
 #define TPC0_CFG_QM_TENSOR_14_PADDING_VALUE_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_14_PADDING_VALUE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG */
 #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_SHIFT          0
 #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_MASK           0x7
 #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT     8
 #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_MASK      0x1F00
 #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_LAST_DIM_SHIFT           16
 #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_LAST_DIM_MASK            0x70000
 #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_SET_SHIFT            19
 #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_SET_MASK             0x80000
 #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_SHIFT         20
 #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_MASK          0x100000
 #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_OP_SHIFT             21
 #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_OP_MASK              0x600000
 
 /* TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE */
 #define TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE */
 #define TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE */
 #define TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE */
 #define TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE */
 #define TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE */
 #define TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE */
 #define TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE */
 #define TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE */
 #define TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE */
 #define TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW */
 #define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH */
 #define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH_V_SHIFT                 0
 #define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_15_PADDING_VALUE */
 #define TPC0_CFG_QM_TENSOR_15_PADDING_VALUE_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_15_PADDING_VALUE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG */
 #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_SHIFT          0
 #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_MASK           0x7
 #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT     8
 #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_MASK      0x1F00
 #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_LAST_DIM_SHIFT           16
 #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_LAST_DIM_MASK            0x70000
 #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_SET_SHIFT            19
 #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_SET_MASK             0x80000
 #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_SHIFT         20
 #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_MASK          0x100000
 #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_OP_SHIFT             21
 #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_OP_MASK              0x600000
 
 /* TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE */
 #define TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE */
 #define TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE */
 #define TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE */
 #define TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE */
 #define TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE */
 #define TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE */
 #define TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE */
 #define TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE */
 #define TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE_V_SHIFT                     0
 #define TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE_V_MASK                      0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE */
 #define TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_SYNC_OBJECT_MESSAGE */
 #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT         0
 #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK          0xFFFF
 #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_RSV_SHIFT                    16
 #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_RSV_MASK                     0x1FFF0000
 #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT           29
 #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK            0xE0000000
 
 /* TPC0_CFG_QM_SYNC_OBJECT_ADDR */
 #define TPC0_CFG_QM_SYNC_OBJECT_ADDR_V_SHIFT                         0
 #define TPC0_CFG_QM_SYNC_OBJECT_ADDR_V_MASK                          0xFFFFFFFF
 
 /* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW */
 #define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_SHIFT                  0
 #define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH */
 #define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT                 0
 #define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_QM_TID_BASE_DIM_0 */
 #define TPC0_CFG_QM_TID_BASE_DIM_0_V_SHIFT                           0
 #define TPC0_CFG_QM_TID_BASE_DIM_0_V_MASK                            0xFFFFFFFF
 
 /* TPC0_CFG_QM_TID_SIZE_DIM_0 */
 #define TPC0_CFG_QM_TID_SIZE_DIM_0_V_SHIFT                           0
 #define TPC0_CFG_QM_TID_SIZE_DIM_0_V_MASK                            0xFFFFFFFF
 
 /* TPC0_CFG_QM_TID_BASE_DIM_1 */
 #define TPC0_CFG_QM_TID_BASE_DIM_1_V_SHIFT                           0
 #define TPC0_CFG_QM_TID_BASE_DIM_1_V_MASK                            0xFFFFFFFF
 
 /* TPC0_CFG_QM_TID_SIZE_DIM_1 */
 #define TPC0_CFG_QM_TID_SIZE_DIM_1_V_SHIFT                           0
 #define TPC0_CFG_QM_TID_SIZE_DIM_1_V_MASK                            0xFFFFFFFF
 
 /* TPC0_CFG_QM_TID_BASE_DIM_2 */
 #define TPC0_CFG_QM_TID_BASE_DIM_2_V_SHIFT                           0
 #define TPC0_CFG_QM_TID_BASE_DIM_2_V_MASK                            0xFFFFFFFF
 
 /* TPC0_CFG_QM_TID_SIZE_DIM_2 */
 #define TPC0_CFG_QM_TID_SIZE_DIM_2_V_SHIFT                           0
 #define TPC0_CFG_QM_TID_SIZE_DIM_2_V_MASK                            0xFFFFFFFF
 
 /* TPC0_CFG_QM_TID_BASE_DIM_3 */
 #define TPC0_CFG_QM_TID_BASE_DIM_3_V_SHIFT                           0
 #define TPC0_CFG_QM_TID_BASE_DIM_3_V_MASK                            0xFFFFFFFF
 
 /* TPC0_CFG_QM_TID_SIZE_DIM_3 */
 #define TPC0_CFG_QM_TID_SIZE_DIM_3_V_SHIFT                           0
 #define TPC0_CFG_QM_TID_SIZE_DIM_3_V_MASK                            0xFFFFFFFF
 
 /* TPC0_CFG_QM_TID_BASE_DIM_4 */
 #define TPC0_CFG_QM_TID_BASE_DIM_4_V_SHIFT                           0
 #define TPC0_CFG_QM_TID_BASE_DIM_4_V_MASK                            0xFFFFFFFF
 
 /* TPC0_CFG_QM_TID_SIZE_DIM_4 */
 #define TPC0_CFG_QM_TID_SIZE_DIM_4_V_SHIFT                           0
 #define TPC0_CFG_QM_TID_SIZE_DIM_4_V_MASK                            0xFFFFFFFF
 
 /* TPC0_CFG_QM_KERNEL_CONFIG */
 #define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_SHIFT                    0
 #define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_MASK                     0x1
 #define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT                 1
 #define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_MASK                  0x2
 #define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT               2
 #define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_MASK                0xFC
 #define TPC0_CFG_QM_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_SHIFT      8
 #define TPC0_CFG_QM_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_MASK       0xFF00
 #define TPC0_CFG_QM_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_SHIFT      16
 #define TPC0_CFG_QM_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_MASK       0xFF0000
 
 /* TPC0_CFG_QM_KERNEL_ID */
 #define TPC0_CFG_QM_KERNEL_ID_V_SHIFT                                0
 #define TPC0_CFG_QM_KERNEL_ID_V_MASK                                 0xFFFF
 
 /* TPC0_CFG_QM_SRF */
 #define TPC0_CFG_QM_SRF_V_SHIFT                                      0
 #define TPC0_CFG_QM_SRF_V_MASK                                       0xFFFFFFFF
 
 #endif /* ASIC_REG_TPC0_CFG_MASKS_H_ */

This page was automatically generated by the 2.1.0 LXR engine. The LXR team