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0013 #ifndef ASIC_REG_NIC1_QM1_REGS_H_
0014 #define ASIC_REG_NIC1_QM1_REGS_H_
0015
0016
0017
0018
0019
0020
0021
0022 #define mmNIC1_QM1_GLBL_CFG0 0xD22000
0023
0024 #define mmNIC1_QM1_GLBL_CFG1 0xD22004
0025
0026 #define mmNIC1_QM1_GLBL_PROT 0xD22008
0027
0028 #define mmNIC1_QM1_GLBL_ERR_CFG 0xD2200C
0029
0030 #define mmNIC1_QM1_GLBL_SECURE_PROPS_0 0xD22010
0031
0032 #define mmNIC1_QM1_GLBL_SECURE_PROPS_1 0xD22014
0033
0034 #define mmNIC1_QM1_GLBL_SECURE_PROPS_2 0xD22018
0035
0036 #define mmNIC1_QM1_GLBL_SECURE_PROPS_3 0xD2201C
0037
0038 #define mmNIC1_QM1_GLBL_SECURE_PROPS_4 0xD22020
0039
0040 #define mmNIC1_QM1_GLBL_NON_SECURE_PROPS_0 0xD22024
0041
0042 #define mmNIC1_QM1_GLBL_NON_SECURE_PROPS_1 0xD22028
0043
0044 #define mmNIC1_QM1_GLBL_NON_SECURE_PROPS_2 0xD2202C
0045
0046 #define mmNIC1_QM1_GLBL_NON_SECURE_PROPS_3 0xD22030
0047
0048 #define mmNIC1_QM1_GLBL_NON_SECURE_PROPS_4 0xD22034
0049
0050 #define mmNIC1_QM1_GLBL_STS0 0xD22038
0051
0052 #define mmNIC1_QM1_GLBL_STS1_0 0xD22040
0053
0054 #define mmNIC1_QM1_GLBL_STS1_1 0xD22044
0055
0056 #define mmNIC1_QM1_GLBL_STS1_2 0xD22048
0057
0058 #define mmNIC1_QM1_GLBL_STS1_3 0xD2204C
0059
0060 #define mmNIC1_QM1_GLBL_STS1_4 0xD22050
0061
0062 #define mmNIC1_QM1_GLBL_MSG_EN_0 0xD22054
0063
0064 #define mmNIC1_QM1_GLBL_MSG_EN_1 0xD22058
0065
0066 #define mmNIC1_QM1_GLBL_MSG_EN_2 0xD2205C
0067
0068 #define mmNIC1_QM1_GLBL_MSG_EN_3 0xD22060
0069
0070 #define mmNIC1_QM1_GLBL_MSG_EN_4 0xD22068
0071
0072 #define mmNIC1_QM1_PQ_BASE_LO_0 0xD22070
0073
0074 #define mmNIC1_QM1_PQ_BASE_LO_1 0xD22074
0075
0076 #define mmNIC1_QM1_PQ_BASE_LO_2 0xD22078
0077
0078 #define mmNIC1_QM1_PQ_BASE_LO_3 0xD2207C
0079
0080 #define mmNIC1_QM1_PQ_BASE_HI_0 0xD22080
0081
0082 #define mmNIC1_QM1_PQ_BASE_HI_1 0xD22084
0083
0084 #define mmNIC1_QM1_PQ_BASE_HI_2 0xD22088
0085
0086 #define mmNIC1_QM1_PQ_BASE_HI_3 0xD2208C
0087
0088 #define mmNIC1_QM1_PQ_SIZE_0 0xD22090
0089
0090 #define mmNIC1_QM1_PQ_SIZE_1 0xD22094
0091
0092 #define mmNIC1_QM1_PQ_SIZE_2 0xD22098
0093
0094 #define mmNIC1_QM1_PQ_SIZE_3 0xD2209C
0095
0096 #define mmNIC1_QM1_PQ_PI_0 0xD220A0
0097
0098 #define mmNIC1_QM1_PQ_PI_1 0xD220A4
0099
0100 #define mmNIC1_QM1_PQ_PI_2 0xD220A8
0101
0102 #define mmNIC1_QM1_PQ_PI_3 0xD220AC
0103
0104 #define mmNIC1_QM1_PQ_CI_0 0xD220B0
0105
0106 #define mmNIC1_QM1_PQ_CI_1 0xD220B4
0107
0108 #define mmNIC1_QM1_PQ_CI_2 0xD220B8
0109
0110 #define mmNIC1_QM1_PQ_CI_3 0xD220BC
0111
0112 #define mmNIC1_QM1_PQ_CFG0_0 0xD220C0
0113
0114 #define mmNIC1_QM1_PQ_CFG0_1 0xD220C4
0115
0116 #define mmNIC1_QM1_PQ_CFG0_2 0xD220C8
0117
0118 #define mmNIC1_QM1_PQ_CFG0_3 0xD220CC
0119
0120 #define mmNIC1_QM1_PQ_CFG1_0 0xD220D0
0121
0122 #define mmNIC1_QM1_PQ_CFG1_1 0xD220D4
0123
0124 #define mmNIC1_QM1_PQ_CFG1_2 0xD220D8
0125
0126 #define mmNIC1_QM1_PQ_CFG1_3 0xD220DC
0127
0128 #define mmNIC1_QM1_PQ_ARUSER_31_11_0 0xD220E0
0129
0130 #define mmNIC1_QM1_PQ_ARUSER_31_11_1 0xD220E4
0131
0132 #define mmNIC1_QM1_PQ_ARUSER_31_11_2 0xD220E8
0133
0134 #define mmNIC1_QM1_PQ_ARUSER_31_11_3 0xD220EC
0135
0136 #define mmNIC1_QM1_PQ_STS0_0 0xD220F0
0137
0138 #define mmNIC1_QM1_PQ_STS0_1 0xD220F4
0139
0140 #define mmNIC1_QM1_PQ_STS0_2 0xD220F8
0141
0142 #define mmNIC1_QM1_PQ_STS0_3 0xD220FC
0143
0144 #define mmNIC1_QM1_PQ_STS1_0 0xD22100
0145
0146 #define mmNIC1_QM1_PQ_STS1_1 0xD22104
0147
0148 #define mmNIC1_QM1_PQ_STS1_2 0xD22108
0149
0150 #define mmNIC1_QM1_PQ_STS1_3 0xD2210C
0151
0152 #define mmNIC1_QM1_CQ_CFG0_0 0xD22110
0153
0154 #define mmNIC1_QM1_CQ_CFG0_1 0xD22114
0155
0156 #define mmNIC1_QM1_CQ_CFG0_2 0xD22118
0157
0158 #define mmNIC1_QM1_CQ_CFG0_3 0xD2211C
0159
0160 #define mmNIC1_QM1_CQ_CFG0_4 0xD22120
0161
0162 #define mmNIC1_QM1_CQ_CFG1_0 0xD22124
0163
0164 #define mmNIC1_QM1_CQ_CFG1_1 0xD22128
0165
0166 #define mmNIC1_QM1_CQ_CFG1_2 0xD2212C
0167
0168 #define mmNIC1_QM1_CQ_CFG1_3 0xD22130
0169
0170 #define mmNIC1_QM1_CQ_CFG1_4 0xD22134
0171
0172 #define mmNIC1_QM1_CQ_ARUSER_31_11_0 0xD22138
0173
0174 #define mmNIC1_QM1_CQ_ARUSER_31_11_1 0xD2213C
0175
0176 #define mmNIC1_QM1_CQ_ARUSER_31_11_2 0xD22140
0177
0178 #define mmNIC1_QM1_CQ_ARUSER_31_11_3 0xD22144
0179
0180 #define mmNIC1_QM1_CQ_ARUSER_31_11_4 0xD22148
0181
0182 #define mmNIC1_QM1_CQ_STS0_0 0xD2214C
0183
0184 #define mmNIC1_QM1_CQ_STS0_1 0xD22150
0185
0186 #define mmNIC1_QM1_CQ_STS0_2 0xD22154
0187
0188 #define mmNIC1_QM1_CQ_STS0_3 0xD22158
0189
0190 #define mmNIC1_QM1_CQ_STS0_4 0xD2215C
0191
0192 #define mmNIC1_QM1_CQ_STS1_0 0xD22160
0193
0194 #define mmNIC1_QM1_CQ_STS1_1 0xD22164
0195
0196 #define mmNIC1_QM1_CQ_STS1_2 0xD22168
0197
0198 #define mmNIC1_QM1_CQ_STS1_3 0xD2216C
0199
0200 #define mmNIC1_QM1_CQ_STS1_4 0xD22170
0201
0202 #define mmNIC1_QM1_CQ_PTR_LO_0 0xD22174
0203
0204 #define mmNIC1_QM1_CQ_PTR_HI_0 0xD22178
0205
0206 #define mmNIC1_QM1_CQ_TSIZE_0 0xD2217C
0207
0208 #define mmNIC1_QM1_CQ_CTL_0 0xD22180
0209
0210 #define mmNIC1_QM1_CQ_PTR_LO_1 0xD22184
0211
0212 #define mmNIC1_QM1_CQ_PTR_HI_1 0xD22188
0213
0214 #define mmNIC1_QM1_CQ_TSIZE_1 0xD2218C
0215
0216 #define mmNIC1_QM1_CQ_CTL_1 0xD22190
0217
0218 #define mmNIC1_QM1_CQ_PTR_LO_2 0xD22194
0219
0220 #define mmNIC1_QM1_CQ_PTR_HI_2 0xD22198
0221
0222 #define mmNIC1_QM1_CQ_TSIZE_2 0xD2219C
0223
0224 #define mmNIC1_QM1_CQ_CTL_2 0xD221A0
0225
0226 #define mmNIC1_QM1_CQ_PTR_LO_3 0xD221A4
0227
0228 #define mmNIC1_QM1_CQ_PTR_HI_3 0xD221A8
0229
0230 #define mmNIC1_QM1_CQ_TSIZE_3 0xD221AC
0231
0232 #define mmNIC1_QM1_CQ_CTL_3 0xD221B0
0233
0234 #define mmNIC1_QM1_CQ_PTR_LO_4 0xD221B4
0235
0236 #define mmNIC1_QM1_CQ_PTR_HI_4 0xD221B8
0237
0238 #define mmNIC1_QM1_CQ_TSIZE_4 0xD221BC
0239
0240 #define mmNIC1_QM1_CQ_CTL_4 0xD221C0
0241
0242 #define mmNIC1_QM1_CQ_PTR_LO_STS_0 0xD221C4
0243
0244 #define mmNIC1_QM1_CQ_PTR_LO_STS_1 0xD221C8
0245
0246 #define mmNIC1_QM1_CQ_PTR_LO_STS_2 0xD221CC
0247
0248 #define mmNIC1_QM1_CQ_PTR_LO_STS_3 0xD221D0
0249
0250 #define mmNIC1_QM1_CQ_PTR_LO_STS_4 0xD221D4
0251
0252 #define mmNIC1_QM1_CQ_PTR_HI_STS_0 0xD221D8
0253
0254 #define mmNIC1_QM1_CQ_PTR_HI_STS_1 0xD221DC
0255
0256 #define mmNIC1_QM1_CQ_PTR_HI_STS_2 0xD221E0
0257
0258 #define mmNIC1_QM1_CQ_PTR_HI_STS_3 0xD221E4
0259
0260 #define mmNIC1_QM1_CQ_PTR_HI_STS_4 0xD221E8
0261
0262 #define mmNIC1_QM1_CQ_TSIZE_STS_0 0xD221EC
0263
0264 #define mmNIC1_QM1_CQ_TSIZE_STS_1 0xD221F0
0265
0266 #define mmNIC1_QM1_CQ_TSIZE_STS_2 0xD221F4
0267
0268 #define mmNIC1_QM1_CQ_TSIZE_STS_3 0xD221F8
0269
0270 #define mmNIC1_QM1_CQ_TSIZE_STS_4 0xD221FC
0271
0272 #define mmNIC1_QM1_CQ_CTL_STS_0 0xD22200
0273
0274 #define mmNIC1_QM1_CQ_CTL_STS_1 0xD22204
0275
0276 #define mmNIC1_QM1_CQ_CTL_STS_2 0xD22208
0277
0278 #define mmNIC1_QM1_CQ_CTL_STS_3 0xD2220C
0279
0280 #define mmNIC1_QM1_CQ_CTL_STS_4 0xD22210
0281
0282 #define mmNIC1_QM1_CQ_IFIFO_CNT_0 0xD22214
0283
0284 #define mmNIC1_QM1_CQ_IFIFO_CNT_1 0xD22218
0285
0286 #define mmNIC1_QM1_CQ_IFIFO_CNT_2 0xD2221C
0287
0288 #define mmNIC1_QM1_CQ_IFIFO_CNT_3 0xD22220
0289
0290 #define mmNIC1_QM1_CQ_IFIFO_CNT_4 0xD22224
0291
0292 #define mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_0 0xD22228
0293
0294 #define mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_1 0xD2222C
0295
0296 #define mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_2 0xD22230
0297
0298 #define mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_3 0xD22234
0299
0300 #define mmNIC1_QM1_CP_MSG_BASE0_ADDR_LO_4 0xD22238
0301
0302 #define mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_0 0xD2223C
0303
0304 #define mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_1 0xD22240
0305
0306 #define mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_2 0xD22244
0307
0308 #define mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_3 0xD22248
0309
0310 #define mmNIC1_QM1_CP_MSG_BASE0_ADDR_HI_4 0xD2224C
0311
0312 #define mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_0 0xD22250
0313
0314 #define mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_1 0xD22254
0315
0316 #define mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_2 0xD22258
0317
0318 #define mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_3 0xD2225C
0319
0320 #define mmNIC1_QM1_CP_MSG_BASE1_ADDR_LO_4 0xD22260
0321
0322 #define mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_0 0xD22264
0323
0324 #define mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_1 0xD22268
0325
0326 #define mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_2 0xD2226C
0327
0328 #define mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_3 0xD22270
0329
0330 #define mmNIC1_QM1_CP_MSG_BASE1_ADDR_HI_4 0xD22274
0331
0332 #define mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_0 0xD22278
0333
0334 #define mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_1 0xD2227C
0335
0336 #define mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_2 0xD22280
0337
0338 #define mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_3 0xD22284
0339
0340 #define mmNIC1_QM1_CP_MSG_BASE2_ADDR_LO_4 0xD22288
0341
0342 #define mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_0 0xD2228C
0343
0344 #define mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_1 0xD22290
0345
0346 #define mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_2 0xD22294
0347
0348 #define mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_3 0xD22298
0349
0350 #define mmNIC1_QM1_CP_MSG_BASE2_ADDR_HI_4 0xD2229C
0351
0352 #define mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_0 0xD222A0
0353
0354 #define mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_1 0xD222A4
0355
0356 #define mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_2 0xD222A8
0357
0358 #define mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_3 0xD222AC
0359
0360 #define mmNIC1_QM1_CP_MSG_BASE3_ADDR_LO_4 0xD222B0
0361
0362 #define mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_0 0xD222B4
0363
0364 #define mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_1 0xD222B8
0365
0366 #define mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_2 0xD222BC
0367
0368 #define mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_3 0xD222C0
0369
0370 #define mmNIC1_QM1_CP_MSG_BASE3_ADDR_HI_4 0xD222C4
0371
0372 #define mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_0 0xD222C8
0373
0374 #define mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_1 0xD222CC
0375
0376 #define mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_2 0xD222D0
0377
0378 #define mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_3 0xD222D4
0379
0380 #define mmNIC1_QM1_CP_LDMA_TSIZE_OFFSET_4 0xD222D8
0381
0382 #define mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xD222E0
0383
0384 #define mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xD222E4
0385
0386 #define mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xD222E8
0387
0388 #define mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xD222EC
0389
0390 #define mmNIC1_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xD222F0
0391
0392 #define mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 0xD222F4
0393
0394 #define mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 0xD222F8
0395
0396 #define mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 0xD222FC
0397
0398 #define mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 0xD22300
0399
0400 #define mmNIC1_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 0xD22304
0401
0402 #define mmNIC1_QM1_CP_FENCE0_RDATA_0 0xD22308
0403
0404 #define mmNIC1_QM1_CP_FENCE0_RDATA_1 0xD2230C
0405
0406 #define mmNIC1_QM1_CP_FENCE0_RDATA_2 0xD22310
0407
0408 #define mmNIC1_QM1_CP_FENCE0_RDATA_3 0xD22314
0409
0410 #define mmNIC1_QM1_CP_FENCE0_RDATA_4 0xD22318
0411
0412 #define mmNIC1_QM1_CP_FENCE1_RDATA_0 0xD2231C
0413
0414 #define mmNIC1_QM1_CP_FENCE1_RDATA_1 0xD22320
0415
0416 #define mmNIC1_QM1_CP_FENCE1_RDATA_2 0xD22324
0417
0418 #define mmNIC1_QM1_CP_FENCE1_RDATA_3 0xD22328
0419
0420 #define mmNIC1_QM1_CP_FENCE1_RDATA_4 0xD2232C
0421
0422 #define mmNIC1_QM1_CP_FENCE2_RDATA_0 0xD22330
0423
0424 #define mmNIC1_QM1_CP_FENCE2_RDATA_1 0xD22334
0425
0426 #define mmNIC1_QM1_CP_FENCE2_RDATA_2 0xD22338
0427
0428 #define mmNIC1_QM1_CP_FENCE2_RDATA_3 0xD2233C
0429
0430 #define mmNIC1_QM1_CP_FENCE2_RDATA_4 0xD22340
0431
0432 #define mmNIC1_QM1_CP_FENCE3_RDATA_0 0xD22344
0433
0434 #define mmNIC1_QM1_CP_FENCE3_RDATA_1 0xD22348
0435
0436 #define mmNIC1_QM1_CP_FENCE3_RDATA_2 0xD2234C
0437
0438 #define mmNIC1_QM1_CP_FENCE3_RDATA_3 0xD22350
0439
0440 #define mmNIC1_QM1_CP_FENCE3_RDATA_4 0xD22354
0441
0442 #define mmNIC1_QM1_CP_FENCE0_CNT_0 0xD22358
0443
0444 #define mmNIC1_QM1_CP_FENCE0_CNT_1 0xD2235C
0445
0446 #define mmNIC1_QM1_CP_FENCE0_CNT_2 0xD22360
0447
0448 #define mmNIC1_QM1_CP_FENCE0_CNT_3 0xD22364
0449
0450 #define mmNIC1_QM1_CP_FENCE0_CNT_4 0xD22368
0451
0452 #define mmNIC1_QM1_CP_FENCE1_CNT_0 0xD2236C
0453
0454 #define mmNIC1_QM1_CP_FENCE1_CNT_1 0xD22370
0455
0456 #define mmNIC1_QM1_CP_FENCE1_CNT_2 0xD22374
0457
0458 #define mmNIC1_QM1_CP_FENCE1_CNT_3 0xD22378
0459
0460 #define mmNIC1_QM1_CP_FENCE1_CNT_4 0xD2237C
0461
0462 #define mmNIC1_QM1_CP_FENCE2_CNT_0 0xD22380
0463
0464 #define mmNIC1_QM1_CP_FENCE2_CNT_1 0xD22384
0465
0466 #define mmNIC1_QM1_CP_FENCE2_CNT_2 0xD22388
0467
0468 #define mmNIC1_QM1_CP_FENCE2_CNT_3 0xD2238C
0469
0470 #define mmNIC1_QM1_CP_FENCE2_CNT_4 0xD22390
0471
0472 #define mmNIC1_QM1_CP_FENCE3_CNT_0 0xD22394
0473
0474 #define mmNIC1_QM1_CP_FENCE3_CNT_1 0xD22398
0475
0476 #define mmNIC1_QM1_CP_FENCE3_CNT_2 0xD2239C
0477
0478 #define mmNIC1_QM1_CP_FENCE3_CNT_3 0xD223A0
0479
0480 #define mmNIC1_QM1_CP_FENCE3_CNT_4 0xD223A4
0481
0482 #define mmNIC1_QM1_CP_STS_0 0xD223A8
0483
0484 #define mmNIC1_QM1_CP_STS_1 0xD223AC
0485
0486 #define mmNIC1_QM1_CP_STS_2 0xD223B0
0487
0488 #define mmNIC1_QM1_CP_STS_3 0xD223B4
0489
0490 #define mmNIC1_QM1_CP_STS_4 0xD223B8
0491
0492 #define mmNIC1_QM1_CP_CURRENT_INST_LO_0 0xD223BC
0493
0494 #define mmNIC1_QM1_CP_CURRENT_INST_LO_1 0xD223C0
0495
0496 #define mmNIC1_QM1_CP_CURRENT_INST_LO_2 0xD223C4
0497
0498 #define mmNIC1_QM1_CP_CURRENT_INST_LO_3 0xD223C8
0499
0500 #define mmNIC1_QM1_CP_CURRENT_INST_LO_4 0xD223CC
0501
0502 #define mmNIC1_QM1_CP_CURRENT_INST_HI_0 0xD223D0
0503
0504 #define mmNIC1_QM1_CP_CURRENT_INST_HI_1 0xD223D4
0505
0506 #define mmNIC1_QM1_CP_CURRENT_INST_HI_2 0xD223D8
0507
0508 #define mmNIC1_QM1_CP_CURRENT_INST_HI_3 0xD223DC
0509
0510 #define mmNIC1_QM1_CP_CURRENT_INST_HI_4 0xD223E0
0511
0512 #define mmNIC1_QM1_CP_BARRIER_CFG_0 0xD223F4
0513
0514 #define mmNIC1_QM1_CP_BARRIER_CFG_1 0xD223F8
0515
0516 #define mmNIC1_QM1_CP_BARRIER_CFG_2 0xD223FC
0517
0518 #define mmNIC1_QM1_CP_BARRIER_CFG_3 0xD22400
0519
0520 #define mmNIC1_QM1_CP_BARRIER_CFG_4 0xD22404
0521
0522 #define mmNIC1_QM1_CP_DBG_0_0 0xD22408
0523
0524 #define mmNIC1_QM1_CP_DBG_0_1 0xD2240C
0525
0526 #define mmNIC1_QM1_CP_DBG_0_2 0xD22410
0527
0528 #define mmNIC1_QM1_CP_DBG_0_3 0xD22414
0529
0530 #define mmNIC1_QM1_CP_DBG_0_4 0xD22418
0531
0532 #define mmNIC1_QM1_CP_ARUSER_31_11_0 0xD2241C
0533
0534 #define mmNIC1_QM1_CP_ARUSER_31_11_1 0xD22420
0535
0536 #define mmNIC1_QM1_CP_ARUSER_31_11_2 0xD22424
0537
0538 #define mmNIC1_QM1_CP_ARUSER_31_11_3 0xD22428
0539
0540 #define mmNIC1_QM1_CP_ARUSER_31_11_4 0xD2242C
0541
0542 #define mmNIC1_QM1_CP_AWUSER_31_11_0 0xD22430
0543
0544 #define mmNIC1_QM1_CP_AWUSER_31_11_1 0xD22434
0545
0546 #define mmNIC1_QM1_CP_AWUSER_31_11_2 0xD22438
0547
0548 #define mmNIC1_QM1_CP_AWUSER_31_11_3 0xD2243C
0549
0550 #define mmNIC1_QM1_CP_AWUSER_31_11_4 0xD22440
0551
0552 #define mmNIC1_QM1_ARB_CFG_0 0xD22A00
0553
0554 #define mmNIC1_QM1_ARB_CHOISE_Q_PUSH 0xD22A04
0555
0556 #define mmNIC1_QM1_ARB_WRR_WEIGHT_0 0xD22A08
0557
0558 #define mmNIC1_QM1_ARB_WRR_WEIGHT_1 0xD22A0C
0559
0560 #define mmNIC1_QM1_ARB_WRR_WEIGHT_2 0xD22A10
0561
0562 #define mmNIC1_QM1_ARB_WRR_WEIGHT_3 0xD22A14
0563
0564 #define mmNIC1_QM1_ARB_CFG_1 0xD22A18
0565
0566 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_0 0xD22A20
0567
0568 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_1 0xD22A24
0569
0570 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_2 0xD22A28
0571
0572 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_3 0xD22A2C
0573
0574 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_4 0xD22A30
0575
0576 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_5 0xD22A34
0577
0578 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_6 0xD22A38
0579
0580 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_7 0xD22A3C
0581
0582 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_8 0xD22A40
0583
0584 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_9 0xD22A44
0585
0586 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_10 0xD22A48
0587
0588 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_11 0xD22A4C
0589
0590 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_12 0xD22A50
0591
0592 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_13 0xD22A54
0593
0594 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_14 0xD22A58
0595
0596 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_15 0xD22A5C
0597
0598 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_16 0xD22A60
0599
0600 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_17 0xD22A64
0601
0602 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_18 0xD22A68
0603
0604 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_19 0xD22A6C
0605
0606 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_20 0xD22A70
0607
0608 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_21 0xD22A74
0609
0610 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_22 0xD22A78
0611
0612 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_23 0xD22A7C
0613
0614 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_24 0xD22A80
0615
0616 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_25 0xD22A84
0617
0618 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_26 0xD22A88
0619
0620 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_27 0xD22A8C
0621
0622 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_28 0xD22A90
0623
0624 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_29 0xD22A94
0625
0626 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_30 0xD22A98
0627
0628 #define mmNIC1_QM1_ARB_MST_AVAIL_CRED_31 0xD22A9C
0629
0630 #define mmNIC1_QM1_ARB_MST_CRED_INC 0xD22AA0
0631
0632 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_0 0xD22AA4
0633
0634 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_1 0xD22AA8
0635
0636 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_2 0xD22AAC
0637
0638 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_3 0xD22AB0
0639
0640 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_4 0xD22AB4
0641
0642 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_5 0xD22AB8
0643
0644 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_6 0xD22ABC
0645
0646 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_7 0xD22AC0
0647
0648 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_8 0xD22AC4
0649
0650 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_9 0xD22AC8
0651
0652 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_10 0xD22ACC
0653
0654 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_11 0xD22AD0
0655
0656 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_12 0xD22AD4
0657
0658 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_13 0xD22AD8
0659
0660 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_14 0xD22ADC
0661
0662 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_15 0xD22AE0
0663
0664 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_16 0xD22AE4
0665
0666 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_17 0xD22AE8
0667
0668 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_18 0xD22AEC
0669
0670 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_19 0xD22AF0
0671
0672 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_20 0xD22AF4
0673
0674 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_21 0xD22AF8
0675
0676 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_22 0xD22AFC
0677
0678 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_23 0xD22B00
0679
0680 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_24 0xD22B04
0681
0682 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_25 0xD22B08
0683
0684 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_26 0xD22B0C
0685
0686 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_27 0xD22B10
0687
0688 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_28 0xD22B14
0689
0690 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_29 0xD22B18
0691
0692 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_30 0xD22B1C
0693
0694 #define mmNIC1_QM1_ARB_MST_CHOISE_PUSH_OFST_31 0xD22B20
0695
0696 #define mmNIC1_QM1_ARB_SLV_MASTER_INC_CRED_OFST 0xD22B28
0697
0698 #define mmNIC1_QM1_ARB_MST_SLAVE_EN 0xD22B2C
0699
0700 #define mmNIC1_QM1_ARB_MST_QUIET_PER 0xD22B34
0701
0702 #define mmNIC1_QM1_ARB_SLV_CHOISE_WDT 0xD22B38
0703
0704 #define mmNIC1_QM1_ARB_SLV_ID 0xD22B3C
0705
0706 #define mmNIC1_QM1_ARB_MSG_MAX_INFLIGHT 0xD22B44
0707
0708 #define mmNIC1_QM1_ARB_MSG_AWUSER_31_11 0xD22B48
0709
0710 #define mmNIC1_QM1_ARB_MSG_AWUSER_SEC_PROP 0xD22B4C
0711
0712 #define mmNIC1_QM1_ARB_MSG_AWUSER_NON_SEC_PROP 0xD22B50
0713
0714 #define mmNIC1_QM1_ARB_BASE_LO 0xD22B54
0715
0716 #define mmNIC1_QM1_ARB_BASE_HI 0xD22B58
0717
0718 #define mmNIC1_QM1_ARB_STATE_STS 0xD22B80
0719
0720 #define mmNIC1_QM1_ARB_CHOISE_FULLNESS_STS 0xD22B84
0721
0722 #define mmNIC1_QM1_ARB_MSG_STS 0xD22B88
0723
0724 #define mmNIC1_QM1_ARB_SLV_CHOISE_Q_HEAD 0xD22B8C
0725
0726 #define mmNIC1_QM1_ARB_ERR_CAUSE 0xD22B9C
0727
0728 #define mmNIC1_QM1_ARB_ERR_MSG_EN 0xD22BA0
0729
0730 #define mmNIC1_QM1_ARB_ERR_STS_DRP 0xD22BA8
0731
0732 #define mmNIC1_QM1_ARB_MST_CRED_STS_0 0xD22BB0
0733
0734 #define mmNIC1_QM1_ARB_MST_CRED_STS_1 0xD22BB4
0735
0736 #define mmNIC1_QM1_ARB_MST_CRED_STS_2 0xD22BB8
0737
0738 #define mmNIC1_QM1_ARB_MST_CRED_STS_3 0xD22BBC
0739
0740 #define mmNIC1_QM1_ARB_MST_CRED_STS_4 0xD22BC0
0741
0742 #define mmNIC1_QM1_ARB_MST_CRED_STS_5 0xD22BC4
0743
0744 #define mmNIC1_QM1_ARB_MST_CRED_STS_6 0xD22BC8
0745
0746 #define mmNIC1_QM1_ARB_MST_CRED_STS_7 0xD22BCC
0747
0748 #define mmNIC1_QM1_ARB_MST_CRED_STS_8 0xD22BD0
0749
0750 #define mmNIC1_QM1_ARB_MST_CRED_STS_9 0xD22BD4
0751
0752 #define mmNIC1_QM1_ARB_MST_CRED_STS_10 0xD22BD8
0753
0754 #define mmNIC1_QM1_ARB_MST_CRED_STS_11 0xD22BDC
0755
0756 #define mmNIC1_QM1_ARB_MST_CRED_STS_12 0xD22BE0
0757
0758 #define mmNIC1_QM1_ARB_MST_CRED_STS_13 0xD22BE4
0759
0760 #define mmNIC1_QM1_ARB_MST_CRED_STS_14 0xD22BE8
0761
0762 #define mmNIC1_QM1_ARB_MST_CRED_STS_15 0xD22BEC
0763
0764 #define mmNIC1_QM1_ARB_MST_CRED_STS_16 0xD22BF0
0765
0766 #define mmNIC1_QM1_ARB_MST_CRED_STS_17 0xD22BF4
0767
0768 #define mmNIC1_QM1_ARB_MST_CRED_STS_18 0xD22BF8
0769
0770 #define mmNIC1_QM1_ARB_MST_CRED_STS_19 0xD22BFC
0771
0772 #define mmNIC1_QM1_ARB_MST_CRED_STS_20 0xD22C00
0773
0774 #define mmNIC1_QM1_ARB_MST_CRED_STS_21 0xD22C04
0775
0776 #define mmNIC1_QM1_ARB_MST_CRED_STS_22 0xD22C08
0777
0778 #define mmNIC1_QM1_ARB_MST_CRED_STS_23 0xD22C0C
0779
0780 #define mmNIC1_QM1_ARB_MST_CRED_STS_24 0xD22C10
0781
0782 #define mmNIC1_QM1_ARB_MST_CRED_STS_25 0xD22C14
0783
0784 #define mmNIC1_QM1_ARB_MST_CRED_STS_26 0xD22C18
0785
0786 #define mmNIC1_QM1_ARB_MST_CRED_STS_27 0xD22C1C
0787
0788 #define mmNIC1_QM1_ARB_MST_CRED_STS_28 0xD22C20
0789
0790 #define mmNIC1_QM1_ARB_MST_CRED_STS_29 0xD22C24
0791
0792 #define mmNIC1_QM1_ARB_MST_CRED_STS_30 0xD22C28
0793
0794 #define mmNIC1_QM1_ARB_MST_CRED_STS_31 0xD22C2C
0795
0796 #define mmNIC1_QM1_CGM_CFG 0xD22C70
0797
0798 #define mmNIC1_QM1_CGM_STS 0xD22C74
0799
0800 #define mmNIC1_QM1_CGM_CFG1 0xD22C78
0801
0802 #define mmNIC1_QM1_LOCAL_RANGE_BASE 0xD22C80
0803
0804 #define mmNIC1_QM1_LOCAL_RANGE_SIZE 0xD22C84
0805
0806 #define mmNIC1_QM1_CSMR_STRICT_PRIO_CFG 0xD22C90
0807
0808 #define mmNIC1_QM1_HBW_RD_RATE_LIM_CFG_1 0xD22C94
0809
0810 #define mmNIC1_QM1_LBW_WR_RATE_LIM_CFG_0 0xD22C98
0811
0812 #define mmNIC1_QM1_LBW_WR_RATE_LIM_CFG_1 0xD22C9C
0813
0814 #define mmNIC1_QM1_HBW_RD_RATE_LIM_CFG_0 0xD22CA0
0815
0816 #define mmNIC1_QM1_GLBL_AXCACHE 0xD22CA4
0817
0818 #define mmNIC1_QM1_IND_GW_APB_CFG 0xD22CB0
0819
0820 #define mmNIC1_QM1_IND_GW_APB_WDATA 0xD22CB4
0821
0822 #define mmNIC1_QM1_IND_GW_APB_RDATA 0xD22CB8
0823
0824 #define mmNIC1_QM1_IND_GW_APB_STATUS 0xD22CBC
0825
0826 #define mmNIC1_QM1_GLBL_ERR_ADDR_LO 0xD22CD0
0827
0828 #define mmNIC1_QM1_GLBL_ERR_ADDR_HI 0xD22CD4
0829
0830 #define mmNIC1_QM1_GLBL_ERR_WDATA 0xD22CD8
0831
0832 #define mmNIC1_QM1_GLBL_MEM_INIT_BUSY 0xD22D00
0833
0834 #endif