gaudi/asic_reg/mmu_up_regs.h

0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * Copyright 2016-2018 HabanaLabs, Ltd.
0004  * All Rights Reserved.
0005  *
0006  */
0007
0008 /************************************
0009  ** This is an auto-generated file **
0010  **       DO NOT EDIT BELOW        **
0011  ************************************/
0012
0013 #ifndef ASIC_REG_MMU_UP_REGS_H_
0014 #define ASIC_REG_MMU_UP_REGS_H_
0015
0016 /*
0017  *****************************************
0018  *   MMU_UP (Prototype: MMU)
0019  *****************************************
0020  */
0021
0022 #define mmMMU_UP_MMU_ENABLE                                          0xC1100C
0023
0024 #define mmMMU_UP_FORCE_ORDERING                                      0xC11010
0025
0026 #define mmMMU_UP_FEATURE_ENABLE                                      0xC11014
0027
0028 #define mmMMU_UP_VA_ORDERING_MASK_31_7                               0xC11018
0029
0030 #define mmMMU_UP_VA_ORDERING_MASK_49_32                              0xC1101C
0031
0032 #define mmMMU_UP_LOG2_DDR_SIZE                                       0xC11020
0033
0034 #define mmMMU_UP_SCRAMBLER                                           0xC11024
0035
0036 #define mmMMU_UP_MEM_INIT_BUSY                                       0xC11028
0037
0038 #define mmMMU_UP_SPI_MASK                                            0xC1102C
0039
0040 #define mmMMU_UP_SPI_CAUSE                                           0xC11030
0041
0042 #define mmMMU_UP_PAGE_ERROR_CAPTURE                                  0xC11034
0043
0044 #define mmMMU_UP_PAGE_ERROR_CAPTURE_VA                               0xC11038
0045
0046 #define mmMMU_UP_ACCESS_ERROR_CAPTURE                                0xC1103C
0047
0048 #define mmMMU_UP_ACCESS_ERROR_CAPTURE_VA                             0xC11040
0049
0050 #define mmMMU_UP_SPI_INTERRUPT_CLR                                   0xC11044
0051
0052 #define mmMMU_UP_SPI_INTERRUPT_MASK                                  0xC11048
0053
0054 #define mmMMU_UP_DBG_MEM_WRAP_RM                                     0xC1104C
0055
0056 #define mmMMU_UP_SPI_CAUSE_CLR                                       0xC11050
0057
0058 #define mmMMU_UP_SLICE_CREDIT                                        0xC11054
0059
0060 #define mmMMU_UP_PIPE_CREDIT                                         0xC11058
0061
0062 #define mmMMU_UP_RAZWI_WRITE_VLD                                     0xC1105C
0063
0064 #define mmMMU_UP_RAZWI_WRITE_ID                                      0xC11060
0065
0066 #define mmMMU_UP_RAZWI_READ_VLD                                      0xC11064
0067
0068 #define mmMMU_UP_RAZWI_READ_ID                                       0xC11068
0069
0070 #define mmMMU_UP_MMU_BYPASS                                          0xC1106C
0071
0072 #endif /* ASIC_REG_MMU_UP_REGS_H_ */