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0008 #ifndef ASIC_REG_GAUDI_REGS_H_
0009 #define ASIC_REG_GAUDI_REGS_H_
0010
0011 #include "gaudi_blocks.h"
0012 #include "psoc_global_conf_regs.h"
0013 #include "psoc_timestamp_regs.h"
0014 #include "cpu_if_regs.h"
0015 #include "mmu_up_regs.h"
0016 #include "stlb_regs.h"
0017 #include "dma0_qm_regs.h"
0018 #include "dma1_qm_regs.h"
0019 #include "dma2_qm_regs.h"
0020 #include "dma3_qm_regs.h"
0021 #include "dma4_qm_regs.h"
0022 #include "dma5_qm_regs.h"
0023 #include "dma6_qm_regs.h"
0024 #include "dma7_qm_regs.h"
0025 #include "dma0_core_regs.h"
0026 #include "dma1_core_regs.h"
0027 #include "dma2_core_regs.h"
0028 #include "dma3_core_regs.h"
0029 #include "dma4_core_regs.h"
0030 #include "dma5_core_regs.h"
0031 #include "dma6_core_regs.h"
0032 #include "dma7_core_regs.h"
0033 #include "mme0_ctrl_regs.h"
0034 #include "mme1_ctrl_regs.h"
0035 #include "mme2_ctrl_regs.h"
0036 #include "mme3_ctrl_regs.h"
0037 #include "mme0_qm_regs.h"
0038 #include "mme2_qm_regs.h"
0039 #include "tpc0_cfg_regs.h"
0040 #include "tpc1_cfg_regs.h"
0041 #include "tpc2_cfg_regs.h"
0042 #include "tpc3_cfg_regs.h"
0043 #include "tpc4_cfg_regs.h"
0044 #include "tpc5_cfg_regs.h"
0045 #include "tpc6_cfg_regs.h"
0046 #include "tpc7_cfg_regs.h"
0047 #include "tpc0_qm_regs.h"
0048 #include "tpc1_qm_regs.h"
0049 #include "tpc2_qm_regs.h"
0050 #include "tpc3_qm_regs.h"
0051 #include "tpc4_qm_regs.h"
0052 #include "tpc5_qm_regs.h"
0053 #include "tpc6_qm_regs.h"
0054 #include "tpc7_qm_regs.h"
0055 #include "dma_if_e_n_down_ch0_regs.h"
0056 #include "dma_if_e_n_down_ch1_regs.h"
0057 #include "dma_if_e_s_down_ch0_regs.h"
0058 #include "dma_if_e_s_down_ch1_regs.h"
0059 #include "dma_if_w_n_down_ch0_regs.h"
0060 #include "dma_if_w_n_down_ch1_regs.h"
0061 #include "dma_if_w_s_down_ch0_regs.h"
0062 #include "dma_if_w_s_down_ch1_regs.h"
0063 #include "dma_if_e_n_regs.h"
0064 #include "dma_if_e_s_regs.h"
0065 #include "dma_if_w_n_regs.h"
0066 #include "dma_if_w_s_regs.h"
0067 #include "nif_rtr_ctrl_0_regs.h"
0068 #include "nif_rtr_ctrl_1_regs.h"
0069 #include "nif_rtr_ctrl_2_regs.h"
0070 #include "nif_rtr_ctrl_3_regs.h"
0071 #include "nif_rtr_ctrl_4_regs.h"
0072 #include "nif_rtr_ctrl_5_regs.h"
0073 #include "nif_rtr_ctrl_6_regs.h"
0074 #include "nif_rtr_ctrl_7_regs.h"
0075 #include "sif_rtr_ctrl_0_regs.h"
0076 #include "sif_rtr_ctrl_1_regs.h"
0077 #include "sif_rtr_ctrl_2_regs.h"
0078 #include "sif_rtr_ctrl_3_regs.h"
0079 #include "sif_rtr_ctrl_4_regs.h"
0080 #include "sif_rtr_ctrl_5_regs.h"
0081 #include "sif_rtr_ctrl_6_regs.h"
0082 #include "sif_rtr_ctrl_7_regs.h"
0083 #include "psoc_etr_regs.h"
0084 #include "psoc_cpu_pll_regs.h"
0085
0086 #include "dma0_qm_masks.h"
0087 #include "mme0_qm_masks.h"
0088 #include "tpc0_qm_masks.h"
0089 #include "dma0_core_masks.h"
0090 #include "tpc0_cfg_masks.h"
0091 #include "psoc_global_conf_masks.h"
0092
0093 #include "nic0_qm0_regs.h"
0094 #include "nic1_qm0_regs.h"
0095 #include "nic2_qm0_regs.h"
0096 #include "nic3_qm0_regs.h"
0097 #include "nic4_qm0_regs.h"
0098 #include "nic0_qm1_regs.h"
0099 #include "nic1_qm1_regs.h"
0100 #include "nic2_qm1_regs.h"
0101 #include "nic3_qm1_regs.h"
0102 #include "nic4_qm1_regs.h"
0103
0104 #include "nic0_qm0_masks.h"
0105
0106 #define GAUDI_ECC_MEM_SEL_OFFSET 0xF18
0107 #define GAUDI_ECC_ADDRESS_OFFSET 0xF1C
0108 #define GAUDI_ECC_SYNDROME_OFFSET 0xF20
0109 #define GAUDI_ECC_MEM_INFO_CLR_OFFSET 0xF28
0110 #define GAUDI_ECC_MEM_INFO_CLR_SERR_MASK BIT(8)
0111 #define GAUDI_ECC_MEM_INFO_CLR_DERR_MASK BIT(9)
0112 #define GAUDI_ECC_SERR0_OFFSET 0xF30
0113 #define GAUDI_ECC_DERR0_OFFSET 0xF40
0114
0115 #define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0 0x492000
0116 #define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 0x494000
0117 #define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 0x494800
0118 #define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_DATA_0 0x495000
0119 #define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0 0x495800
0120 #define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0 0x496000
0121 #define mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_SOB_OBJ_0 0x4B2000
0122 #define mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_MON_STATUS_0 0x4B6000
0123 #define mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_SOB_OBJ_0 0x4D2000
0124 #define mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_MON_STATUS_0 0x4D6000
0125 #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0 0x4F2000
0126 #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_1 0x4F2004
0127 #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047 0x4F3FFC
0128 #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 0x4F4000
0129 #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 0x4F4800
0130 #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_DATA_0 0x4F5000
0131 #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_ARM_0 0x4F5800
0132 #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0 0x4F6000
0133 #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_511 0x4F67FC
0134
0135 #define mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AW 0x300400
0136 #define mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AW 0x310400
0137 #define mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AW 0x320400
0138 #define mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AW 0x330400
0139 #define mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AW 0x340400
0140 #define mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AW 0x350400
0141 #define mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AW 0x360400
0142 #define mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AW 0x370400
0143
0144 #define mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AR 0x300490
0145 #define mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AR 0x310490
0146 #define mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AR 0x320490
0147 #define mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AR 0x330490
0148 #define mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AR 0x340490
0149 #define mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AR 0x350490
0150 #define mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AR 0x360490
0151 #define mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AR 0x370490
0152
0153 #define mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0 0x300410
0154 #define mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0 0x310410
0155 #define mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0 0x320410
0156 #define mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0 0x330410
0157 #define mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0 0x340410
0158 #define mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0 0x350410
0159 #define mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0 0x360410
0160 #define mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0 0x370410
0161
0162 #define mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0 0x300450
0163 #define mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0 0x310450
0164 #define mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0 0x320450
0165 #define mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0 0x330450
0166 #define mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0 0x340450
0167 #define mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0 0x350450
0168 #define mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0 0x360450
0169 #define mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0 0x370450
0170
0171 #define mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0 0x3004A0
0172 #define mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0 0x3104A0
0173 #define mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0 0x3204A0
0174 #define mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0 0x3304A0
0175 #define mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0 0x3404A0
0176 #define mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0 0x3504A0
0177 #define mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0 0x3604A0
0178 #define mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0 0x3704A0
0179
0180 #define mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0 0x3004E0
0181 #define mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0 0x3104E0
0182 #define mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0 0x3204E0
0183 #define mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0 0x3304E0
0184 #define mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0 0x3404E0
0185 #define mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0 0x3504E0
0186 #define mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0 0x3604E0
0187 #define mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0 0x3704E0
0188
0189 #define mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AW 0x380400
0190 #define mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AW 0x390400
0191 #define mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AW 0x3A0400
0192 #define mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AW 0x3B0400
0193 #define mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AW 0x3C0400
0194 #define mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AW 0x3D0400
0195 #define mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AW 0x3E0400
0196 #define mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AW 0x3F0400
0197
0198 #define mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AR 0x380490
0199 #define mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AR 0x390490
0200 #define mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AR 0x3A0490
0201 #define mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AR 0x3B0490
0202 #define mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AR 0x3C0490
0203 #define mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AR 0x3D0490
0204 #define mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AR 0x3E0490
0205 #define mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AR 0x3F0490
0206
0207 #define mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0 0x380410
0208 #define mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0 0x390410
0209 #define mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0 0x3A0410
0210 #define mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0 0x3B0410
0211 #define mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0 0x3C0410
0212 #define mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0 0x3D0410
0213 #define mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0 0x3E0410
0214 #define mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0 0x3F0410
0215
0216 #define mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0 0x380450
0217 #define mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0 0x390450
0218 #define mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0 0x3A0450
0219 #define mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0 0x3B0450
0220 #define mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0 0x3C0450
0221 #define mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0 0x3D0450
0222 #define mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0 0x3E0450
0223 #define mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0 0x3F0450
0224
0225 #define mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0 0x3804A0
0226 #define mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0 0x3904A0
0227 #define mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0 0x3A04A0
0228 #define mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0 0x3B04A0
0229 #define mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0 0x3C04A0
0230 #define mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0 0x3D04A0
0231 #define mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0 0x3E04A0
0232 #define mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0 0x3F04A0
0233
0234 #define mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0 0x3804E0
0235 #define mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0 0x3904E0
0236 #define mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0 0x3A04E0
0237 #define mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0 0x3B04E0
0238 #define mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0 0x3C04E0
0239 #define mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0 0x3D04E0
0240 #define mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0 0x3E04E0
0241 #define mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0 0x3F04E0
0242
0243 #define mmDMA_IF_W_S_DOWN_RSP_MID_WGHT_0 0x489030
0244 #define mmDMA_IF_W_S_DOWN_RSP_MID_WGHT_1 0x489034
0245
0246 #define mmDMA_IF_E_S_DOWN_RSP_MID_WGHT_0 0x4A9030
0247 #define mmDMA_IF_E_S_DOWN_RSP_MID_WGHT_1 0x4A9034
0248
0249 #define mmDMA_IF_W_N_DOWN_RSP_MID_WGHT_0 0x4C9030
0250 #define mmDMA_IF_W_N_DOWN_RSP_MID_WGHT_1 0x4C9034
0251
0252 #define mmDMA_IF_E_N_DOWN_RSP_MID_WGHT_0 0x4E9030
0253 #define mmDMA_IF_E_N_DOWN_RSP_MID_WGHT_1 0x4E9034
0254
0255 #define mmMME1_QM_GLBL_CFG0 0xE8000
0256 #define mmMME1_QM_GLBL_STS0 0xE8038
0257
0258 #define mmMME0_SBAB_SB_STALL 0x4002C
0259 #define mmMME0_SBAB_ARUSER0 0x40034
0260 #define mmMME0_SBAB_ARUSER1 0x40038
0261 #define mmMME0_SBAB_PROT 0x40050
0262
0263 #define mmMME1_SBAB_SB_STALL 0xC002C
0264 #define mmMME1_SBAB_ARUSER0 0xC0034
0265 #define mmMME1_SBAB_ARUSER1 0xC0038
0266 #define mmMME1_SBAB_PROT 0xC0050
0267
0268 #define mmMME2_SBAB_SB_STALL 0x14002C
0269 #define mmMME2_SBAB_ARUSER0 0x140034
0270 #define mmMME2_SBAB_ARUSER1 0x140038
0271 #define mmMME2_SBAB_PROT 0x140050
0272
0273 #define mmMME3_SBAB_SB_STALL 0x1C002C
0274 #define mmMME3_SBAB_ARUSER0 0x1C0034
0275 #define mmMME3_SBAB_ARUSER1 0x1C0038
0276 #define mmMME3_SBAB_PROT 0x1C0050
0277
0278 #define mmMME0_ACC_ACC_STALL 0x20028
0279 #define mmMME0_ACC_WBC 0x20038
0280 #define mmMME0_ACC_PROT 0x20050
0281
0282 #define mmMME1_ACC_ACC_STALL 0xA0028
0283 #define mmMME1_ACC_WBC 0xA0038
0284 #define mmMME1_ACC_PROT 0xA0050
0285
0286 #define mmMME2_ACC_ACC_STALL 0x120028
0287 #define mmMME2_ACC_WBC 0x120038
0288 #define mmMME2_ACC_PROT 0x120050
0289
0290 #define mmMME3_ACC_ACC_STALL 0x1A0028
0291 #define mmMME3_ACC_WBC 0x1A0038
0292 #define mmMME3_ACC_PROT 0x1A0050
0293
0294 #define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR 0x800040
0295
0296 #define mmPSOC_EFUSE_READ 0xC4A000
0297 #define mmPSOC_EFUSE_DATA_0 0xC4A080
0298
0299 #define mmPCIE_WRAP_MAX_OUTSTAND 0xC01B20
0300 #define mmPCIE_WRAP_LBW_PROT_OVR 0xC01B48
0301 #define mmPCIE_WRAP_HBW_DRAIN_CFG 0xC01D54
0302 #define mmPCIE_WRAP_LBW_DRAIN_CFG 0xC01D5C
0303
0304 #define mmPCIE_MSI_INTR_0 0xC13000
0305
0306 #define mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG 0xC02000
0307
0308 #define mmPCIE_AUX_FLR_CTRL 0xC07394
0309 #define mmPCIE_AUX_DBI 0xC07490
0310
0311 #define mmPCIE_CORE_MSI_REQ 0xC04100
0312
0313 #define mmPSOC_PCI_PLL_NR 0xC72100
0314 #define mmSRAM_W_PLL_NR 0x4C8100
0315 #define mmPSOC_HBM_PLL_NR 0xC74100
0316 #define mmNIC0_PLL_NR 0xCF9100
0317 #define mmDMA_W_PLL_NR 0x487100
0318 #define mmMESH_W_PLL_NR 0x4C7100
0319 #define mmPSOC_MME_PLL_NR 0xC71100
0320 #define mmPSOC_TPC_PLL_NR 0xC73100
0321 #define mmIF_W_PLL_NR 0x488100
0322
0323 #endif
