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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 
0003 /*
0004  * Copyright 2016-2019 HabanaLabs, Ltd.
0005  * All Rights Reserved.
0006  */
0007 
0008 #include "goyaP.h"
0009 #include "../include/goya/asic_reg/goya_regs.h"
0010 
0011 /*
0012  * goya_set_block_as_protected - set the given block as protected
0013  *
0014  * @hdev: pointer to hl_device structure
0015  * @block: block base address
0016  *
0017  */
0018 static void goya_pb_set_block(struct hl_device *hdev, u64 base)
0019 {
0020     u32 pb_addr = base - CFG_BASE + PROT_BITS_OFFS;
0021 
0022     while (pb_addr & 0xFFF) {
0023         WREG32(pb_addr, 0);
0024         pb_addr += 4;
0025     }
0026 }
0027 
0028 static void goya_init_mme_protection_bits(struct hl_device *hdev)
0029 {
0030     u32 pb_addr, mask;
0031     u8 word_offset;
0032 
0033     /* TODO: change to real reg name when Soc Online is updated */
0034     u64 mmMME_SBB_POWER_ECO1 = 0xDFF60,
0035         mmMME_SBB_POWER_ECO2 = 0xDFF64;
0036 
0037     goya_pb_set_block(hdev, mmACC_MS_ECC_MEM_0_BASE);
0038     goya_pb_set_block(hdev, mmACC_MS_ECC_MEM_1_BASE);
0039     goya_pb_set_block(hdev, mmACC_MS_ECC_MEM_2_BASE);
0040     goya_pb_set_block(hdev, mmACC_MS_ECC_MEM_3_BASE);
0041 
0042     goya_pb_set_block(hdev, mmSBA_ECC_MEM_BASE);
0043     goya_pb_set_block(hdev, mmSBB_ECC_MEM_BASE);
0044 
0045     goya_pb_set_block(hdev, mmMME1_RTR_BASE);
0046     goya_pb_set_block(hdev, mmMME1_RD_REGULATOR_BASE);
0047     goya_pb_set_block(hdev, mmMME1_WR_REGULATOR_BASE);
0048     goya_pb_set_block(hdev, mmMME2_RTR_BASE);
0049     goya_pb_set_block(hdev, mmMME2_RD_REGULATOR_BASE);
0050     goya_pb_set_block(hdev, mmMME2_WR_REGULATOR_BASE);
0051     goya_pb_set_block(hdev, mmMME3_RTR_BASE);
0052     goya_pb_set_block(hdev, mmMME3_RD_REGULATOR_BASE);
0053     goya_pb_set_block(hdev, mmMME3_WR_REGULATOR_BASE);
0054 
0055     goya_pb_set_block(hdev, mmMME4_RTR_BASE);
0056     goya_pb_set_block(hdev, mmMME4_RD_REGULATOR_BASE);
0057     goya_pb_set_block(hdev, mmMME4_WR_REGULATOR_BASE);
0058 
0059     goya_pb_set_block(hdev, mmMME5_RTR_BASE);
0060     goya_pb_set_block(hdev, mmMME5_RD_REGULATOR_BASE);
0061     goya_pb_set_block(hdev, mmMME5_WR_REGULATOR_BASE);
0062 
0063     goya_pb_set_block(hdev, mmMME6_RTR_BASE);
0064     goya_pb_set_block(hdev, mmMME6_RD_REGULATOR_BASE);
0065     goya_pb_set_block(hdev, mmMME6_WR_REGULATOR_BASE);
0066 
0067     pb_addr = (mmMME_DUMMY & ~0xFFF) + PROT_BITS_OFFS;
0068     word_offset = ((mmMME_DUMMY & PROT_BITS_OFFS) >> 7) << 2;
0069     mask = 1 << ((mmMME_DUMMY & 0x7F) >> 2);
0070     mask |= 1 << ((mmMME_RESET & 0x7F) >> 2);
0071     mask |= 1 << ((mmMME_STALL & 0x7F) >> 2);
0072     mask |= 1 << ((mmMME_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
0073     mask |= 1 << ((mmMME_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
0074     mask |= 1 << ((mmMME_DBGMEM_ADD & 0x7F) >> 2);
0075     mask |= 1 << ((mmMME_DBGMEM_DATA_WR & 0x7F) >> 2);
0076     mask |= 1 << ((mmMME_DBGMEM_DATA_RD & 0x7F) >> 2);
0077     mask |= 1 << ((mmMME_DBGMEM_CTRL & 0x7F) >> 2);
0078     mask |= 1 << ((mmMME_DBGMEM_RC & 0x7F) >> 2);
0079     mask |= 1 << ((mmMME_LOG_SHADOW & 0x7F) >> 2);
0080 
0081     WREG32(pb_addr + word_offset, ~mask);
0082 
0083     pb_addr = (mmMME_STORE_MAX_CREDIT & ~0xFFF) + PROT_BITS_OFFS;
0084     word_offset = ((mmMME_STORE_MAX_CREDIT & PROT_BITS_OFFS) >> 7) << 2;
0085     mask = 1 << ((mmMME_STORE_MAX_CREDIT & 0x7F) >> 2);
0086     mask |= 1 << ((mmMME_AGU & 0x7F) >> 2);
0087     mask |= 1 << ((mmMME_SBA & 0x7F) >> 2);
0088     mask |= 1 << ((mmMME_SBB & 0x7F) >> 2);
0089     mask |= 1 << ((mmMME_SBC & 0x7F) >> 2);
0090     mask |= 1 << ((mmMME_WBC & 0x7F) >> 2);
0091     mask |= 1 << ((mmMME_SBA_CONTROL_DATA & 0x7F) >> 2);
0092     mask |= 1 << ((mmMME_SBB_CONTROL_DATA & 0x7F) >> 2);
0093     mask |= 1 << ((mmMME_SBC_CONTROL_DATA & 0x7F) >> 2);
0094     mask |= 1 << ((mmMME_WBC_CONTROL_DATA & 0x7F) >> 2);
0095     mask |= 1 << ((mmMME_TE & 0x7F) >> 2);
0096     mask |= 1 << ((mmMME_TE2DEC & 0x7F) >> 2);
0097     mask |= 1 << ((mmMME_REI_STATUS & 0x7F) >> 2);
0098     mask |= 1 << ((mmMME_REI_MASK & 0x7F) >> 2);
0099     mask |= 1 << ((mmMME_SEI_STATUS & 0x7F) >> 2);
0100     mask |= 1 << ((mmMME_SEI_MASK & 0x7F) >> 2);
0101     mask |= 1 << ((mmMME_SPI_STATUS & 0x7F) >> 2);
0102     mask |= 1 << ((mmMME_SPI_MASK & 0x7F) >> 2);
0103 
0104     WREG32(pb_addr + word_offset, ~mask);
0105 
0106     pb_addr = (mmMME_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
0107     word_offset = ((mmMME_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
0108     mask = 1 << ((mmMME_QM_GLBL_CFG0 & 0x7F) >> 2);
0109     mask |= 1 << ((mmMME_QM_GLBL_CFG1 & 0x7F) >> 2);
0110     mask |= 1 << ((mmMME_QM_GLBL_PROT & 0x7F) >> 2);
0111     mask |= 1 << ((mmMME_QM_GLBL_ERR_CFG & 0x7F) >> 2);
0112     mask |= 1 << ((mmMME_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
0113     mask |= 1 << ((mmMME_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
0114     mask |= 1 << ((mmMME_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
0115     mask |= 1 << ((mmMME_QM_GLBL_SECURE_PROPS & 0x7F) >> 2);
0116     mask |= 1 << ((mmMME_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
0117     mask |= 1 << ((mmMME_QM_GLBL_STS0 & 0x7F) >> 2);
0118     mask |= 1 << ((mmMME_QM_GLBL_STS1 & 0x7F) >> 2);
0119     mask |= 1 << ((mmMME_QM_PQ_BASE_LO & 0x7F) >> 2);
0120     mask |= 1 << ((mmMME_QM_PQ_BASE_HI & 0x7F) >> 2);
0121     mask |= 1 << ((mmMME_QM_PQ_SIZE & 0x7F) >> 2);
0122     mask |= 1 << ((mmMME_QM_PQ_PI & 0x7F) >> 2);
0123     mask |= 1 << ((mmMME_QM_PQ_CI & 0x7F) >> 2);
0124     mask |= 1 << ((mmMME_QM_PQ_CFG0 & 0x7F) >> 2);
0125     mask |= 1 << ((mmMME_QM_PQ_CFG1 & 0x7F) >> 2);
0126     mask |= 1 << ((mmMME_QM_PQ_ARUSER & 0x7F) >> 2);
0127 
0128     WREG32(pb_addr + word_offset, ~mask);
0129 
0130     pb_addr = (mmMME_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS;
0131     word_offset = ((mmMME_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2;
0132     mask = 1 << ((mmMME_QM_PQ_PUSH0 & 0x7F) >> 2);
0133     mask |= 1 << ((mmMME_QM_PQ_PUSH1 & 0x7F) >> 2);
0134     mask |= 1 << ((mmMME_QM_PQ_PUSH2 & 0x7F) >> 2);
0135     mask |= 1 << ((mmMME_QM_PQ_PUSH3 & 0x7F) >> 2);
0136     mask |= 1 << ((mmMME_QM_PQ_STS0 & 0x7F) >> 2);
0137     mask |= 1 << ((mmMME_QM_PQ_STS1 & 0x7F) >> 2);
0138     mask |= 1 << ((mmMME_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
0139     mask |= 1 << ((mmMME_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
0140     mask |= 1 << ((mmMME_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
0141     mask |= 1 << ((mmMME_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
0142     mask |= 1 << ((mmMME_QM_CQ_CFG0 & 0x7F) >> 2);
0143     mask |= 1 << ((mmMME_QM_CQ_CFG1 & 0x7F) >> 2);
0144     mask |= 1 << ((mmMME_QM_CQ_ARUSER & 0x7F) >> 2);
0145     mask |= 1 << ((mmMME_QM_CQ_PTR_LO & 0x7F) >> 2);
0146     mask |= 1 << ((mmMME_QM_CQ_PTR_HI & 0x7F) >> 2);
0147     mask |= 1 << ((mmMME_QM_CQ_TSIZE & 0x7F) >> 2);
0148     mask |= 1 << ((mmMME_QM_CQ_CTL & 0x7F) >> 2);
0149     mask |= 1 << ((mmMME_QM_CQ_PTR_LO_STS & 0x7F) >> 2);
0150     mask |= 1 << ((mmMME_QM_CQ_PTR_HI_STS & 0x7F) >> 2);
0151     mask |= 1 << ((mmMME_QM_CQ_TSIZE_STS & 0x7F) >> 2);
0152     mask |= 1 << ((mmMME_QM_CQ_CTL_STS & 0x7F) >> 2);
0153     mask |= 1 << ((mmMME_QM_CQ_STS0 & 0x7F) >> 2);
0154     mask |= 1 << ((mmMME_QM_CQ_STS1 & 0x7F) >> 2);
0155     mask |= 1 << ((mmMME_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
0156     mask |= 1 << ((mmMME_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
0157     mask |= 1 << ((mmMME_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
0158     mask |= 1 << ((mmMME_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
0159 
0160     WREG32(pb_addr + word_offset, ~mask);
0161 
0162     pb_addr = (mmMME_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
0163     word_offset = ((mmMME_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
0164     mask = 1 << ((mmMME_QM_CQ_IFIFO_CNT & 0x7F) >> 2);
0165     mask |= 1 << ((mmMME_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
0166     mask |= 1 << ((mmMME_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
0167     mask |= 1 << ((mmMME_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
0168     mask |= 1 << ((mmMME_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
0169     mask |= 1 << ((mmMME_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
0170     mask |= 1 << ((mmMME_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
0171     mask |= 1 << ((mmMME_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
0172     mask |= 1 << ((mmMME_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
0173     mask |= 1 << ((mmMME_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
0174     mask |= 1 << ((mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
0175     mask |= 1 << ((mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
0176     mask |= 1 << ((mmMME_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
0177     mask |= 1 << ((mmMME_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
0178     mask |= 1 << ((mmMME_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
0179 
0180     WREG32(pb_addr + word_offset, ~mask);
0181 
0182     pb_addr = (mmMME_QM_CP_STS & ~0xFFF) + PROT_BITS_OFFS;
0183     word_offset = ((mmMME_QM_CP_STS & PROT_BITS_OFFS) >> 7) << 2;
0184     mask = 1 << ((mmMME_QM_CP_STS & 0x7F) >> 2);
0185     mask |= 1 << ((mmMME_QM_CP_CURRENT_INST_LO & 0x7F) >> 2);
0186     mask |= 1 << ((mmMME_QM_CP_CURRENT_INST_HI & 0x7F) >> 2);
0187     mask |= 1 << ((mmMME_QM_CP_BARRIER_CFG & 0x7F) >> 2);
0188     mask |= 1 << ((mmMME_QM_CP_DBG_0 & 0x7F) >> 2);
0189     mask |= 1 << ((mmMME_QM_PQ_BUF_ADDR & 0x7F) >> 2);
0190     mask |= 1 << ((mmMME_QM_PQ_BUF_RDATA & 0x7F) >> 2);
0191     mask |= 1 << ((mmMME_QM_CQ_BUF_ADDR & 0x7F) >> 2);
0192     mask |= 1 << ((mmMME_QM_CQ_BUF_RDATA & 0x7F) >> 2);
0193 
0194     WREG32(pb_addr + word_offset, ~mask);
0195 
0196     pb_addr = (mmMME_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
0197     word_offset = ((mmMME_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
0198     mask = 1 << ((mmMME_CMDQ_GLBL_CFG0 & 0x7F) >> 2);
0199     mask |= 1 << ((mmMME_CMDQ_GLBL_CFG1 & 0x7F) >> 2);
0200     mask |= 1 << ((mmMME_CMDQ_GLBL_PROT & 0x7F) >> 2);
0201     mask |= 1 << ((mmMME_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2);
0202     mask |= 1 << ((mmMME_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
0203     mask |= 1 << ((mmMME_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
0204     mask |= 1 << ((mmMME_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2);
0205     mask |= 1 << ((mmMME_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2);
0206     mask |= 1 << ((mmMME_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
0207     mask |= 1 << ((mmMME_CMDQ_GLBL_STS0 & 0x7F) >> 2);
0208     mask |= 1 << ((mmMME_CMDQ_GLBL_STS1 & 0x7F) >> 2);
0209 
0210     WREG32(pb_addr + word_offset, ~mask);
0211 
0212     pb_addr = (mmMME_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
0213     word_offset = ((mmMME_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
0214     mask = 1 << ((mmMME_CMDQ_CQ_CFG0 & 0x7F) >> 2);
0215     mask |= 1 << ((mmMME_CMDQ_CQ_CFG1 & 0x7F) >> 2);
0216     mask |= 1 << ((mmMME_CMDQ_CQ_ARUSER & 0x7F) >> 2);
0217     mask |= 1 << ((mmMME_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2);
0218     mask |= 1 << ((mmMME_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2);
0219     mask |= 1 << ((mmMME_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2);
0220     mask |= 1 << ((mmMME_CMDQ_CQ_CTL_STS & 0x7F) >> 2);
0221     mask |= 1 << ((mmMME_CMDQ_CQ_STS0 & 0x7F) >> 2);
0222     mask |= 1 << ((mmMME_CMDQ_CQ_STS1 & 0x7F) >> 2);
0223     mask |= 1 << ((mmMME_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
0224     mask |= 1 << ((mmMME_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
0225     mask |= 1 << ((mmMME_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
0226     mask |= 1 << ((mmMME_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
0227 
0228     WREG32(pb_addr + word_offset, ~mask);
0229 
0230     pb_addr = (mmMME_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
0231     word_offset = ((mmMME_CMDQ_CQ_IFIFO_CNT &
0232             PROT_BITS_OFFS) >> 7) << 2;
0233     mask = 1 << ((mmMME_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2);
0234     mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
0235     mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
0236     mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
0237     mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
0238     mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
0239     mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
0240     mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
0241     mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
0242     mask |= 1 << ((mmMME_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
0243     mask |= 1 << ((mmMME_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
0244     mask |= 1 << ((mmMME_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
0245     mask |= 1 << ((mmMME_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
0246     mask |= 1 << ((mmMME_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
0247     mask |= 1 << ((mmMME_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
0248     mask |= 1 << ((mmMME_CMDQ_CP_STS & 0x7F) >> 2);
0249     mask |= 1 << ((mmMME_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2);
0250 
0251     WREG32(pb_addr + word_offset, ~mask);
0252 
0253     pb_addr = (mmMME_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS;
0254     word_offset = ((mmMME_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7)
0255             << 2;
0256     mask = 1 << ((mmMME_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2);
0257     mask |= 1 << ((mmMME_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2);
0258     mask |= 1 << ((mmMME_CMDQ_CP_DBG_0 & 0x7F) >> 2);
0259     mask |= 1 << ((mmMME_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2);
0260     mask |= 1 << ((mmMME_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2);
0261 
0262     WREG32(pb_addr + word_offset, ~mask);
0263 
0264     pb_addr = (mmMME_SBB_POWER_ECO1 & ~0xFFF) + PROT_BITS_OFFS;
0265     word_offset = ((mmMME_SBB_POWER_ECO1 & PROT_BITS_OFFS) >> 7) << 2;
0266     mask = 1 << ((mmMME_SBB_POWER_ECO1 & 0x7F) >> 2);
0267     mask |= 1 << ((mmMME_SBB_POWER_ECO2 & 0x7F) >> 2);
0268 
0269     WREG32(pb_addr + word_offset, ~mask);
0270 }
0271 
0272 static void goya_init_dma_protection_bits(struct hl_device *hdev)
0273 {
0274     u32 pb_addr, mask;
0275     u8 word_offset;
0276 
0277     goya_pb_set_block(hdev, mmDMA_NRTR_BASE);
0278     goya_pb_set_block(hdev, mmDMA_RD_REGULATOR_BASE);
0279     goya_pb_set_block(hdev, mmDMA_WR_REGULATOR_BASE);
0280 
0281     pb_addr = (mmDMA_QM_0_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
0282     word_offset = ((mmDMA_QM_0_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
0283     mask = 1 << ((mmDMA_QM_0_GLBL_CFG0 & 0x7F) >> 2);
0284     mask |= 1 << ((mmDMA_QM_0_GLBL_CFG1 & 0x7F) >> 2);
0285     mask |= 1 << ((mmDMA_QM_0_GLBL_PROT & 0x7F) >> 2);
0286     mask |= 1 << ((mmDMA_QM_0_GLBL_ERR_CFG & 0x7F) >> 2);
0287     mask |= 1 << ((mmDMA_QM_0_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
0288     mask |= 1 << ((mmDMA_QM_0_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
0289     mask |= 1 << ((mmDMA_QM_0_GLBL_ERR_WDATA & 0x7F) >> 2);
0290     mask |= 1 << ((mmDMA_QM_0_GLBL_SECURE_PROPS & 0x7F) >> 2);
0291     mask |= 1 << ((mmDMA_QM_0_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
0292     mask |= 1 << ((mmDMA_QM_0_GLBL_STS0 & 0x7F) >> 2);
0293     mask |= 1 << ((mmDMA_QM_0_GLBL_STS1 & 0x7F) >> 2);
0294     mask |= 1 << ((mmDMA_QM_0_PQ_BASE_LO & 0x7F) >> 2);
0295     mask |= 1 << ((mmDMA_QM_0_PQ_BASE_HI & 0x7F) >> 2);
0296     mask |= 1 << ((mmDMA_QM_0_PQ_SIZE & 0x7F) >> 2);
0297     mask |= 1 << ((mmDMA_QM_0_PQ_PI & 0x7F) >> 2);
0298     mask |= 1 << ((mmDMA_QM_0_PQ_CI & 0x7F) >> 2);
0299     mask |= 1 << ((mmDMA_QM_0_PQ_CFG0 & 0x7F) >> 2);
0300     mask |= 1 << ((mmDMA_QM_0_PQ_CFG1 & 0x7F) >> 2);
0301     mask |= 1 << ((mmDMA_QM_0_PQ_ARUSER & 0x7F) >> 2);
0302 
0303     WREG32(pb_addr + word_offset, ~mask);
0304 
0305     pb_addr = (mmDMA_QM_0_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS;
0306     word_offset = ((mmDMA_QM_0_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2;
0307     mask = 1 << ((mmDMA_QM_0_PQ_PUSH0 & 0x7F) >> 2);
0308     mask |= 1 << ((mmDMA_QM_0_PQ_PUSH1 & 0x7F) >> 2);
0309     mask |= 1 << ((mmDMA_QM_0_PQ_PUSH2 & 0x7F) >> 2);
0310     mask |= 1 << ((mmDMA_QM_0_PQ_PUSH3 & 0x7F) >> 2);
0311     mask |= 1 << ((mmDMA_QM_0_PQ_STS0 & 0x7F) >> 2);
0312     mask |= 1 << ((mmDMA_QM_0_PQ_STS1 & 0x7F) >> 2);
0313     mask |= 1 << ((mmDMA_QM_0_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
0314     mask |= 1 << ((mmDMA_QM_0_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
0315     mask |= 1 << ((mmDMA_QM_0_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
0316     mask |= 1 << ((mmDMA_QM_0_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
0317     mask |= 1 << ((mmDMA_QM_0_CQ_CFG0 & 0x7F) >> 2);
0318     mask |= 1 << ((mmDMA_QM_0_CQ_CFG1 & 0x7F) >> 2);
0319     mask |= 1 << ((mmDMA_QM_0_CQ_ARUSER & 0x7F) >> 2);
0320     mask |= 1 << ((mmDMA_QM_0_CQ_PTR_LO & 0x7F) >> 2);
0321     mask |= 1 << ((mmDMA_QM_0_CQ_PTR_HI & 0x7F) >> 2);
0322     mask |= 1 << ((mmDMA_QM_0_CQ_TSIZE & 0x7F) >> 2);
0323     mask |= 1 << ((mmDMA_QM_0_CQ_CTL & 0x7F) >> 2);
0324     mask |= 1 << ((mmDMA_QM_0_CQ_PTR_LO_STS & 0x7F) >> 2);
0325     mask |= 1 << ((mmDMA_QM_0_CQ_PTR_HI_STS & 0x7F) >> 2);
0326     mask |= 1 << ((mmDMA_QM_0_CQ_TSIZE_STS & 0x7F) >> 2);
0327     mask |= 1 << ((mmDMA_QM_0_CQ_CTL_STS & 0x7F) >> 2);
0328     mask |= 1 << ((mmDMA_QM_0_CQ_STS0 & 0x7F) >> 2);
0329     mask |= 1 << ((mmDMA_QM_0_CQ_STS1 & 0x7F) >> 2);
0330     mask |= 1 << ((mmDMA_QM_0_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
0331     mask |= 1 << ((mmDMA_QM_0_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
0332     mask |= 1 << ((mmDMA_QM_0_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
0333     mask |= 1 << ((mmDMA_QM_0_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
0334 
0335     WREG32(pb_addr + word_offset, ~mask);
0336 
0337     pb_addr = (mmDMA_QM_0_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
0338     word_offset = ((mmDMA_QM_0_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
0339     mask = 1 << ((mmDMA_QM_0_CQ_IFIFO_CNT & 0x7F) >> 2);
0340     mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
0341     mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
0342     mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
0343     mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
0344     mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
0345     mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
0346     mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
0347     mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
0348     mask |= 1 << ((mmDMA_QM_0_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
0349     mask |= 1 << ((mmDMA_QM_0_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
0350     mask |= 1 << ((mmDMA_QM_0_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
0351     mask |= 1 << ((mmDMA_QM_0_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
0352     mask |= 1 << ((mmDMA_QM_0_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
0353     mask |= 1 << ((mmDMA_QM_0_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
0354 
0355     WREG32(pb_addr + word_offset, ~mask);
0356 
0357     goya_pb_set_block(hdev, mmDMA_CH_0_BASE);
0358 
0359     pb_addr = (mmDMA_QM_1_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
0360     word_offset = ((mmDMA_QM_1_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
0361     mask = 1 << ((mmDMA_QM_1_GLBL_CFG0 & 0x7F) >> 2);
0362     mask |= 1 << ((mmDMA_QM_1_GLBL_CFG1 & 0x7F) >> 2);
0363     mask |= 1 << ((mmDMA_QM_1_GLBL_PROT & 0x7F) >> 2);
0364     mask |= 1 << ((mmDMA_QM_1_GLBL_ERR_CFG & 0x7F) >> 2);
0365     mask |= 1 << ((mmDMA_QM_1_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
0366     mask |= 1 << ((mmDMA_QM_1_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
0367     mask |= 1 << ((mmDMA_QM_1_GLBL_ERR_WDATA & 0x7F) >> 2);
0368     mask |= 1 << ((mmDMA_QM_1_GLBL_SECURE_PROPS & 0x7F) >> 2);
0369     mask |= 1 << ((mmDMA_QM_1_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
0370     mask |= 1 << ((mmDMA_QM_1_GLBL_STS0 & 0x7F) >> 2);
0371     mask |= 1 << ((mmDMA_QM_1_GLBL_STS1 & 0x7F) >> 2);
0372     mask |= 1 << ((mmDMA_QM_1_PQ_BASE_LO & 0x7F) >> 2);
0373     mask |= 1 << ((mmDMA_QM_1_PQ_BASE_HI & 0x7F) >> 2);
0374     mask |= 1 << ((mmDMA_QM_1_PQ_SIZE & 0x7F) >> 2);
0375     mask |= 1 << ((mmDMA_QM_1_PQ_PI & 0x7F) >> 2);
0376     mask |= 1 << ((mmDMA_QM_1_PQ_CI & 0x7F) >> 2);
0377     mask |= 1 << ((mmDMA_QM_1_PQ_CFG0 & 0x7F) >> 2);
0378     mask |= 1 << ((mmDMA_QM_1_PQ_CFG1 & 0x7F) >> 2);
0379     mask |= 1 << ((mmDMA_QM_1_PQ_ARUSER & 0x7F) >> 2);
0380 
0381     WREG32(pb_addr + word_offset, ~mask);
0382 
0383     pb_addr = (mmDMA_QM_1_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS;
0384     word_offset = ((mmDMA_QM_1_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2;
0385     mask = 1 << ((mmDMA_QM_1_PQ_PUSH0 & 0x7F) >> 2);
0386     mask |= 1 << ((mmDMA_QM_1_PQ_PUSH1 & 0x7F) >> 2);
0387     mask |= 1 << ((mmDMA_QM_1_PQ_PUSH2 & 0x7F) >> 2);
0388     mask |= 1 << ((mmDMA_QM_1_PQ_PUSH3 & 0x7F) >> 2);
0389     mask |= 1 << ((mmDMA_QM_1_PQ_STS0 & 0x7F) >> 2);
0390     mask |= 1 << ((mmDMA_QM_1_PQ_STS1 & 0x7F) >> 2);
0391     mask |= 1 << ((mmDMA_QM_1_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
0392     mask |= 1 << ((mmDMA_QM_1_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
0393     mask |= 1 << ((mmDMA_QM_1_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
0394     mask |= 1 << ((mmDMA_QM_1_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
0395     mask |= 1 << ((mmDMA_QM_1_CQ_CFG0 & 0x7F) >> 2);
0396     mask |= 1 << ((mmDMA_QM_1_CQ_CFG1 & 0x7F) >> 2);
0397     mask |= 1 << ((mmDMA_QM_1_CQ_ARUSER & 0x7F) >> 2);
0398     mask |= 1 << ((mmDMA_QM_1_CQ_PTR_LO & 0x7F) >> 2);
0399     mask |= 1 << ((mmDMA_QM_1_CQ_PTR_HI & 0x7F) >> 2);
0400     mask |= 1 << ((mmDMA_QM_1_CQ_TSIZE & 0x7F) >> 2);
0401     mask |= 1 << ((mmDMA_QM_1_CQ_CTL & 0x7F) >> 2);
0402     mask |= 1 << ((mmDMA_QM_1_CQ_PTR_LO_STS & 0x7F) >> 2);
0403     mask |= 1 << ((mmDMA_QM_1_CQ_PTR_HI_STS & 0x7F) >> 2);
0404     mask |= 1 << ((mmDMA_QM_1_CQ_TSIZE_STS & 0x7F) >> 2);
0405     mask |= 1 << ((mmDMA_QM_1_CQ_CTL_STS & 0x7F) >> 2);
0406     mask |= 1 << ((mmDMA_QM_1_CQ_STS0 & 0x7F) >> 2);
0407     mask |= 1 << ((mmDMA_QM_1_CQ_STS1 & 0x7F) >> 2);
0408     mask |= 1 << ((mmDMA_QM_1_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
0409     mask |= 1 << ((mmDMA_QM_1_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
0410     mask |= 1 << ((mmDMA_QM_1_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
0411     mask |= 1 << ((mmDMA_QM_1_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
0412 
0413     WREG32(pb_addr + word_offset, ~mask);
0414 
0415     pb_addr = (mmDMA_QM_1_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
0416     word_offset = ((mmDMA_QM_1_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
0417     mask = 1 << ((mmDMA_QM_1_CQ_IFIFO_CNT & 0x7F) >> 2);
0418     mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
0419     mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
0420     mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
0421     mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
0422     mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
0423     mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
0424     mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
0425     mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
0426     mask |= 1 << ((mmDMA_QM_1_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
0427     mask |= 1 << ((mmDMA_QM_1_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
0428     mask |= 1 << ((mmDMA_QM_1_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
0429     mask |= 1 << ((mmDMA_QM_1_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
0430     mask |= 1 << ((mmDMA_QM_1_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
0431     mask |= 1 << ((mmDMA_QM_1_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
0432 
0433     WREG32(pb_addr + word_offset, ~mask);
0434 
0435     goya_pb_set_block(hdev, mmDMA_CH_1_BASE);
0436 
0437     pb_addr = (mmDMA_QM_2_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
0438     word_offset = ((mmDMA_QM_2_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
0439     mask = 1 << ((mmDMA_QM_2_GLBL_CFG0 & 0x7F) >> 2);
0440     mask |= 1 << ((mmDMA_QM_2_GLBL_CFG1 & 0x7F) >> 2);
0441     mask |= 1 << ((mmDMA_QM_2_GLBL_PROT & 0x7F) >> 2);
0442     mask |= 1 << ((mmDMA_QM_2_GLBL_ERR_CFG & 0x7F) >> 2);
0443     mask |= 1 << ((mmDMA_QM_2_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
0444     mask |= 1 << ((mmDMA_QM_2_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
0445     mask |= 1 << ((mmDMA_QM_2_GLBL_ERR_WDATA & 0x7F) >> 2);
0446     mask |= 1 << ((mmDMA_QM_2_GLBL_SECURE_PROPS & 0x7F) >> 2);
0447     mask |= 1 << ((mmDMA_QM_2_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
0448     mask |= 1 << ((mmDMA_QM_2_GLBL_STS0 & 0x7F) >> 2);
0449     mask |= 1 << ((mmDMA_QM_2_GLBL_STS1 & 0x7F) >> 2);
0450     mask |= 1 << ((mmDMA_QM_2_PQ_BASE_LO & 0x7F) >> 2);
0451     mask |= 1 << ((mmDMA_QM_2_PQ_BASE_HI & 0x7F) >> 2);
0452     mask |= 1 << ((mmDMA_QM_2_PQ_SIZE & 0x7F) >> 2);
0453     mask |= 1 << ((mmDMA_QM_2_PQ_PI & 0x7F) >> 2);
0454     mask |= 1 << ((mmDMA_QM_2_PQ_CI & 0x7F) >> 2);
0455     mask |= 1 << ((mmDMA_QM_2_PQ_CFG0 & 0x7F) >> 2);
0456     mask |= 1 << ((mmDMA_QM_2_PQ_CFG1 & 0x7F) >> 2);
0457     mask |= 1 << ((mmDMA_QM_2_PQ_ARUSER & 0x7F) >> 2);
0458 
0459     WREG32(pb_addr + word_offset, ~mask);
0460 
0461     pb_addr = (mmDMA_QM_2_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS;
0462     word_offset = ((mmDMA_QM_2_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2;
0463     mask = 1 << ((mmDMA_QM_2_PQ_PUSH0 & 0x7F) >> 2);
0464     mask |= 1 << ((mmDMA_QM_2_PQ_PUSH1 & 0x7F) >> 2);
0465     mask |= 1 << ((mmDMA_QM_2_PQ_PUSH2 & 0x7F) >> 2);
0466     mask |= 1 << ((mmDMA_QM_2_PQ_PUSH3 & 0x7F) >> 2);
0467     mask |= 1 << ((mmDMA_QM_2_PQ_STS0 & 0x7F) >> 2);
0468     mask |= 1 << ((mmDMA_QM_2_PQ_STS1 & 0x7F) >> 2);
0469     mask |= 1 << ((mmDMA_QM_2_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
0470     mask |= 1 << ((mmDMA_QM_2_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
0471     mask |= 1 << ((mmDMA_QM_2_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
0472     mask |= 1 << ((mmDMA_QM_2_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
0473     mask |= 1 << ((mmDMA_QM_2_CQ_CFG0 & 0x7F) >> 2);
0474     mask |= 1 << ((mmDMA_QM_2_CQ_CFG1 & 0x7F) >> 2);
0475     mask |= 1 << ((mmDMA_QM_2_CQ_ARUSER & 0x7F) >> 2);
0476     mask |= 1 << ((mmDMA_QM_2_CQ_PTR_LO & 0x7F) >> 2);
0477     mask |= 1 << ((mmDMA_QM_2_CQ_PTR_HI & 0x7F) >> 2);
0478     mask |= 1 << ((mmDMA_QM_2_CQ_TSIZE & 0x7F) >> 2);
0479     mask |= 1 << ((mmDMA_QM_2_CQ_CTL & 0x7F) >> 2);
0480     mask |= 1 << ((mmDMA_QM_2_CQ_PTR_LO_STS & 0x7F) >> 2);
0481     mask |= 1 << ((mmDMA_QM_2_CQ_PTR_HI_STS & 0x7F) >> 2);
0482     mask |= 1 << ((mmDMA_QM_2_CQ_TSIZE_STS & 0x7F) >> 2);
0483     mask |= 1 << ((mmDMA_QM_2_CQ_CTL_STS & 0x7F) >> 2);
0484     mask |= 1 << ((mmDMA_QM_2_CQ_STS0 & 0x7F) >> 2);
0485     mask |= 1 << ((mmDMA_QM_2_CQ_STS1 & 0x7F) >> 2);
0486     mask |= 1 << ((mmDMA_QM_2_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
0487     mask |= 1 << ((mmDMA_QM_2_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
0488     mask |= 1 << ((mmDMA_QM_2_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
0489     mask |= 1 << ((mmDMA_QM_2_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
0490 
0491     WREG32(pb_addr + word_offset, ~mask);
0492 
0493     pb_addr = (mmDMA_QM_2_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
0494     word_offset = ((mmDMA_QM_2_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
0495     mask = 1 << ((mmDMA_QM_2_CQ_IFIFO_CNT & 0x7F) >> 2);
0496     mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
0497     mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
0498     mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
0499     mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
0500     mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
0501     mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
0502     mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
0503     mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
0504     mask |= 1 << ((mmDMA_QM_2_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
0505     mask |= 1 << ((mmDMA_QM_2_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
0506     mask |= 1 << ((mmDMA_QM_2_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
0507     mask |= 1 << ((mmDMA_QM_2_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
0508     mask |= 1 << ((mmDMA_QM_2_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
0509     mask |= 1 << ((mmDMA_QM_2_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
0510 
0511     WREG32(pb_addr + word_offset, ~mask);
0512 
0513     goya_pb_set_block(hdev, mmDMA_CH_2_BASE);
0514 
0515     pb_addr = (mmDMA_QM_3_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
0516     word_offset = ((mmDMA_QM_3_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
0517     mask = 1 << ((mmDMA_QM_3_GLBL_CFG0 & 0x7F) >> 2);
0518     mask |= 1 << ((mmDMA_QM_3_GLBL_CFG1 & 0x7F) >> 2);
0519     mask |= 1 << ((mmDMA_QM_3_GLBL_PROT & 0x7F) >> 2);
0520     mask |= 1 << ((mmDMA_QM_3_GLBL_ERR_CFG & 0x7F) >> 2);
0521     mask |= 1 << ((mmDMA_QM_3_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
0522     mask |= 1 << ((mmDMA_QM_3_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
0523     mask |= 1 << ((mmDMA_QM_3_GLBL_ERR_WDATA & 0x7F) >> 2);
0524     mask |= 1 << ((mmDMA_QM_3_GLBL_SECURE_PROPS & 0x7F) >> 2);
0525     mask |= 1 << ((mmDMA_QM_3_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
0526     mask |= 1 << ((mmDMA_QM_3_GLBL_STS0 & 0x7F) >> 2);
0527     mask |= 1 << ((mmDMA_QM_3_GLBL_STS1 & 0x7F) >> 2);
0528     mask |= 1 << ((mmDMA_QM_3_PQ_BASE_LO & 0x7F) >> 2);
0529     mask |= 1 << ((mmDMA_QM_3_PQ_BASE_HI & 0x7F) >> 2);
0530     mask |= 1 << ((mmDMA_QM_3_PQ_SIZE & 0x7F) >> 2);
0531     mask |= 1 << ((mmDMA_QM_3_PQ_PI & 0x7F) >> 2);
0532     mask |= 1 << ((mmDMA_QM_3_PQ_CI & 0x7F) >> 2);
0533     mask |= 1 << ((mmDMA_QM_3_PQ_CFG0 & 0x7F) >> 2);
0534     mask |= 1 << ((mmDMA_QM_3_PQ_CFG1 & 0x7F) >> 2);
0535     mask |= 1 << ((mmDMA_QM_3_PQ_ARUSER & 0x7F) >> 2);
0536 
0537     WREG32(pb_addr + word_offset, ~mask);
0538 
0539     pb_addr = (mmDMA_QM_3_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS;
0540     word_offset = ((mmDMA_QM_3_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2;
0541     mask = 1 << ((mmDMA_QM_3_PQ_PUSH0 & 0x7F) >> 2);
0542     mask |= 1 << ((mmDMA_QM_3_PQ_PUSH1 & 0x7F) >> 2);
0543     mask |= 1 << ((mmDMA_QM_3_PQ_PUSH2 & 0x7F) >> 2);
0544     mask |= 1 << ((mmDMA_QM_3_PQ_PUSH3 & 0x7F) >> 2);
0545     mask |= 1 << ((mmDMA_QM_3_PQ_STS0 & 0x7F) >> 2);
0546     mask |= 1 << ((mmDMA_QM_3_PQ_STS1 & 0x7F) >> 2);
0547     mask |= 1 << ((mmDMA_QM_3_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
0548     mask |= 1 << ((mmDMA_QM_3_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
0549     mask |= 1 << ((mmDMA_QM_3_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
0550     mask |= 1 << ((mmDMA_QM_3_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
0551     mask |= 1 << ((mmDMA_QM_3_CQ_CFG0 & 0x7F) >> 2);
0552     mask |= 1 << ((mmDMA_QM_3_CQ_CFG1 & 0x7F) >> 2);
0553     mask |= 1 << ((mmDMA_QM_3_CQ_ARUSER & 0x7F) >> 2);
0554     mask |= 1 << ((mmDMA_QM_3_CQ_PTR_LO & 0x7F) >> 2);
0555     mask |= 1 << ((mmDMA_QM_3_CQ_PTR_HI & 0x7F) >> 2);
0556     mask |= 1 << ((mmDMA_QM_3_CQ_TSIZE & 0x7F) >> 2);
0557     mask |= 1 << ((mmDMA_QM_3_CQ_CTL & 0x7F) >> 2);
0558     mask |= 1 << ((mmDMA_QM_3_CQ_PTR_LO_STS & 0x7F) >> 2);
0559     mask |= 1 << ((mmDMA_QM_3_CQ_PTR_HI_STS & 0x7F) >> 2);
0560     mask |= 1 << ((mmDMA_QM_3_CQ_TSIZE_STS & 0x7F) >> 2);
0561     mask |= 1 << ((mmDMA_QM_3_CQ_CTL_STS & 0x7F) >> 2);
0562     mask |= 1 << ((mmDMA_QM_3_CQ_STS0 & 0x7F) >> 2);
0563     mask |= 1 << ((mmDMA_QM_3_CQ_STS1 & 0x7F) >> 2);
0564     mask |= 1 << ((mmDMA_QM_3_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
0565     mask |= 1 << ((mmDMA_QM_3_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
0566     mask |= 1 << ((mmDMA_QM_3_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
0567     mask |= 1 << ((mmDMA_QM_3_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
0568 
0569     WREG32(pb_addr + word_offset, ~mask);
0570 
0571     pb_addr = (mmDMA_QM_3_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
0572     word_offset = ((mmDMA_QM_3_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
0573     mask = 1 << ((mmDMA_QM_3_CQ_IFIFO_CNT & 0x7F) >> 2);
0574     mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
0575     mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
0576     mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
0577     mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
0578     mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
0579     mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
0580     mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
0581     mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
0582     mask |= 1 << ((mmDMA_QM_3_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
0583     mask |= 1 << ((mmDMA_QM_3_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
0584     mask |= 1 << ((mmDMA_QM_3_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
0585     mask |= 1 << ((mmDMA_QM_3_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
0586     mask |= 1 << ((mmDMA_QM_3_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
0587     mask |= 1 << ((mmDMA_QM_3_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
0588 
0589     WREG32(pb_addr + word_offset, ~mask);
0590 
0591     goya_pb_set_block(hdev, mmDMA_CH_3_BASE);
0592 
0593     pb_addr = (mmDMA_QM_4_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
0594     word_offset = ((mmDMA_QM_4_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
0595     mask = 1 << ((mmDMA_QM_4_GLBL_CFG0 & 0x7F) >> 2);
0596     mask |= 1 << ((mmDMA_QM_4_GLBL_CFG1 & 0x7F) >> 2);
0597     mask |= 1 << ((mmDMA_QM_4_GLBL_PROT & 0x7F) >> 2);
0598     mask |= 1 << ((mmDMA_QM_4_GLBL_ERR_CFG & 0x7F) >> 2);
0599     mask |= 1 << ((mmDMA_QM_4_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
0600     mask |= 1 << ((mmDMA_QM_4_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
0601     mask |= 1 << ((mmDMA_QM_4_GLBL_ERR_WDATA & 0x7F) >> 2);
0602     mask |= 1 << ((mmDMA_QM_4_GLBL_SECURE_PROPS & 0x7F) >> 2);
0603     mask |= 1 << ((mmDMA_QM_4_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
0604     mask |= 1 << ((mmDMA_QM_4_GLBL_STS0 & 0x7F) >> 2);
0605     mask |= 1 << ((mmDMA_QM_4_GLBL_STS1 & 0x7F) >> 2);
0606     mask |= 1 << ((mmDMA_QM_4_PQ_BASE_LO & 0x7F) >> 2);
0607     mask |= 1 << ((mmDMA_QM_4_PQ_BASE_HI & 0x7F) >> 2);
0608     mask |= 1 << ((mmDMA_QM_4_PQ_SIZE & 0x7F) >> 2);
0609     mask |= 1 << ((mmDMA_QM_4_PQ_PI & 0x7F) >> 2);
0610     mask |= 1 << ((mmDMA_QM_4_PQ_CI & 0x7F) >> 2);
0611     mask |= 1 << ((mmDMA_QM_4_PQ_CFG0 & 0x7F) >> 2);
0612     mask |= 1 << ((mmDMA_QM_4_PQ_CFG1 & 0x7F) >> 2);
0613     mask |= 1 << ((mmDMA_QM_4_PQ_ARUSER & 0x7F) >> 2);
0614 
0615     WREG32(pb_addr + word_offset, ~mask);
0616 
0617     pb_addr = (mmDMA_QM_4_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS;
0618     word_offset = ((mmDMA_QM_4_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2;
0619     mask = 1 << ((mmDMA_QM_4_PQ_PUSH0 & 0x7F) >> 2);
0620     mask |= 1 << ((mmDMA_QM_4_PQ_PUSH1 & 0x7F) >> 2);
0621     mask |= 1 << ((mmDMA_QM_4_PQ_PUSH2 & 0x7F) >> 2);
0622     mask |= 1 << ((mmDMA_QM_4_PQ_PUSH3 & 0x7F) >> 2);
0623     mask |= 1 << ((mmDMA_QM_4_PQ_STS0 & 0x7F) >> 2);
0624     mask |= 1 << ((mmDMA_QM_4_PQ_STS1 & 0x7F) >> 2);
0625     mask |= 1 << ((mmDMA_QM_4_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
0626     mask |= 1 << ((mmDMA_QM_4_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
0627     mask |= 1 << ((mmDMA_QM_4_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
0628     mask |= 1 << ((mmDMA_QM_4_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
0629     mask |= 1 << ((mmDMA_QM_4_CQ_CFG0 & 0x7F) >> 2);
0630     mask |= 1 << ((mmDMA_QM_4_CQ_CFG1 & 0x7F) >> 2);
0631     mask |= 1 << ((mmDMA_QM_4_CQ_ARUSER & 0x7F) >> 2);
0632     mask |= 1 << ((mmDMA_QM_4_CQ_PTR_LO & 0x7F) >> 2);
0633     mask |= 1 << ((mmDMA_QM_4_CQ_PTR_HI & 0x7F) >> 2);
0634     mask |= 1 << ((mmDMA_QM_4_CQ_TSIZE & 0x7F) >> 2);
0635     mask |= 1 << ((mmDMA_QM_4_CQ_CTL & 0x7F) >> 2);
0636     mask |= 1 << ((mmDMA_QM_4_CQ_PTR_LO_STS & 0x7F) >> 2);
0637     mask |= 1 << ((mmDMA_QM_4_CQ_PTR_HI_STS & 0x7F) >> 2);
0638     mask |= 1 << ((mmDMA_QM_4_CQ_TSIZE_STS & 0x7F) >> 2);
0639     mask |= 1 << ((mmDMA_QM_4_CQ_CTL_STS & 0x7F) >> 2);
0640     mask |= 1 << ((mmDMA_QM_4_CQ_STS0 & 0x7F) >> 2);
0641     mask |= 1 << ((mmDMA_QM_4_CQ_STS1 & 0x7F) >> 2);
0642     mask |= 1 << ((mmDMA_QM_4_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
0643     mask |= 1 << ((mmDMA_QM_4_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
0644     mask |= 1 << ((mmDMA_QM_4_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
0645     mask |= 1 << ((mmDMA_QM_4_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
0646 
0647     WREG32(pb_addr + word_offset, ~mask);
0648 
0649     pb_addr = (mmDMA_QM_4_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
0650     word_offset = ((mmDMA_QM_4_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
0651     mask = 1 << ((mmDMA_QM_4_CQ_IFIFO_CNT & 0x7F) >> 2);
0652     mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
0653     mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
0654     mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
0655     mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
0656     mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
0657     mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
0658     mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
0659     mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
0660     mask |= 1 << ((mmDMA_QM_4_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
0661     mask |= 1 << ((mmDMA_QM_4_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
0662     mask |= 1 << ((mmDMA_QM_4_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
0663     mask |= 1 << ((mmDMA_QM_4_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
0664     mask |= 1 << ((mmDMA_QM_4_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
0665     mask |= 1 << ((mmDMA_QM_4_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
0666 
0667     WREG32(pb_addr + word_offset, ~mask);
0668 
0669     goya_pb_set_block(hdev, mmDMA_CH_4_BASE);
0670 }
0671 
0672 static void goya_init_tpc_protection_bits(struct hl_device *hdev)
0673 {
0674     u32 pb_addr, mask;
0675     u8 word_offset;
0676 
0677     goya_pb_set_block(hdev, mmTPC0_RD_REGULATOR_BASE);
0678     goya_pb_set_block(hdev, mmTPC0_WR_REGULATOR_BASE);
0679 
0680     pb_addr = (mmTPC0_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS;
0681     word_offset = ((mmTPC0_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2;
0682 
0683     mask = 1 << ((mmTPC0_CFG_SEMAPHORE & 0x7F) >> 2);
0684     mask |= 1 << ((mmTPC0_CFG_VFLAGS & 0x7F) >> 2);
0685     mask |= 1 << ((mmTPC0_CFG_SFLAGS & 0x7F) >> 2);
0686     mask |= 1 << ((mmTPC0_CFG_STATUS & 0x7F) >> 2);
0687 
0688     WREG32(pb_addr + word_offset, ~mask);
0689 
0690     pb_addr = (mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS;
0691     word_offset = ((mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH &
0692             PROT_BITS_OFFS) >> 7) << 2;
0693     mask = 1 << ((mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2);
0694     mask |= 1 << ((mmTPC0_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
0695     mask |= 1 << ((mmTPC0_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
0696     mask |= 1 << ((mmTPC0_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
0697     mask |= 1 << ((mmTPC0_CFG_TPC_STALL & 0x7F) >> 2);
0698     mask |= 1 << ((mmTPC0_CFG_MSS_CONFIG & 0x7F) >> 2);
0699     mask |= 1 << ((mmTPC0_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
0700     mask |= 1 << ((mmTPC0_CFG_TPC_INTR_MASK & 0x7F) >> 2);
0701 
0702     WREG32(pb_addr + word_offset, ~mask);
0703 
0704     pb_addr = (mmTPC0_CFG_ARUSER & ~0xFFF) + PROT_BITS_OFFS;
0705     word_offset = ((mmTPC0_CFG_ARUSER & PROT_BITS_OFFS) >> 7) << 2;
0706     mask = 1 << ((mmTPC0_CFG_ARUSER & 0x7F) >> 2);
0707     mask |= 1 << ((mmTPC0_CFG_AWUSER & 0x7F) >> 2);
0708 
0709     WREG32(pb_addr + word_offset, ~mask);
0710 
0711     pb_addr = (mmTPC0_CFG_FUNC_MBIST_CNTRL & ~0xFFF) + PROT_BITS_OFFS;
0712     word_offset = ((mmTPC0_CFG_FUNC_MBIST_CNTRL &
0713             PROT_BITS_OFFS) >> 7) << 2;
0714     mask = 1 << ((mmTPC0_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2);
0715     mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_PAT & 0x7F) >> 2);
0716     mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2);
0717     mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2);
0718     mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2);
0719     mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2);
0720     mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2);
0721     mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2);
0722     mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2);
0723     mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2);
0724     mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2);
0725     mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2);
0726 
0727     WREG32(pb_addr + word_offset, ~mask);
0728 
0729     pb_addr = (mmTPC0_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
0730     word_offset = ((mmTPC0_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
0731     mask = 1 << ((mmTPC0_QM_GLBL_CFG0 & 0x7F) >> 2);
0732     mask |= 1 << ((mmTPC0_QM_GLBL_CFG1 & 0x7F) >> 2);
0733     mask |= 1 << ((mmTPC0_QM_GLBL_PROT & 0x7F) >> 2);
0734     mask |= 1 << ((mmTPC0_QM_GLBL_ERR_CFG & 0x7F) >> 2);
0735     mask |= 1 << ((mmTPC0_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
0736     mask |= 1 << ((mmTPC0_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
0737     mask |= 1 << ((mmTPC0_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
0738     mask |= 1 << ((mmTPC0_QM_GLBL_SECURE_PROPS & 0x7F) >> 2);
0739     mask |= 1 << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
0740     mask |= 1 << ((mmTPC0_QM_GLBL_STS0 & 0x7F) >> 2);
0741     mask |= 1 << ((mmTPC0_QM_GLBL_STS1 & 0x7F) >> 2);
0742     mask |= 1 << ((mmTPC0_QM_PQ_BASE_LO & 0x7F) >> 2);
0743     mask |= 1 << ((mmTPC0_QM_PQ_BASE_HI & 0x7F) >> 2);
0744     mask |= 1 << ((mmTPC0_QM_PQ_SIZE & 0x7F) >> 2);
0745     mask |= 1 << ((mmTPC0_QM_PQ_PI & 0x7F) >> 2);
0746     mask |= 1 << ((mmTPC0_QM_PQ_CI & 0x7F) >> 2);
0747     mask |= 1 << ((mmTPC0_QM_PQ_CFG0 & 0x7F) >> 2);
0748     mask |= 1 << ((mmTPC0_QM_PQ_CFG1 & 0x7F) >> 2);
0749     mask |= 1 << ((mmTPC0_QM_PQ_ARUSER & 0x7F) >> 2);
0750 
0751     WREG32(pb_addr + word_offset, ~mask);
0752 
0753     pb_addr = (mmTPC0_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS;
0754     word_offset = ((mmTPC0_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2;
0755     mask = 1 << ((mmTPC0_QM_PQ_PUSH0 & 0x7F) >> 2);
0756     mask |= 1 << ((mmTPC0_QM_PQ_PUSH1 & 0x7F) >> 2);
0757     mask |= 1 << ((mmTPC0_QM_PQ_PUSH2 & 0x7F) >> 2);
0758     mask |= 1 << ((mmTPC0_QM_PQ_PUSH3 & 0x7F) >> 2);
0759     mask |= 1 << ((mmTPC0_QM_PQ_STS0 & 0x7F) >> 2);
0760     mask |= 1 << ((mmTPC0_QM_PQ_STS1 & 0x7F) >> 2);
0761     mask |= 1 << ((mmTPC0_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
0762     mask |= 1 << ((mmTPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
0763     mask |= 1 << ((mmTPC0_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
0764     mask |= 1 << ((mmTPC0_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
0765     mask |= 1 << ((mmTPC0_QM_CQ_CFG0 & 0x7F) >> 2);
0766     mask |= 1 << ((mmTPC0_QM_CQ_CFG1 & 0x7F) >> 2);
0767     mask |= 1 << ((mmTPC0_QM_CQ_ARUSER & 0x7F) >> 2);
0768     mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO & 0x7F) >> 2);
0769     mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI & 0x7F) >> 2);
0770     mask |= 1 << ((mmTPC0_QM_CQ_TSIZE & 0x7F) >> 2);
0771     mask |= 1 << ((mmTPC0_QM_CQ_CTL & 0x7F) >> 2);
0772     mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_STS & 0x7F) >> 2);
0773     mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_STS & 0x7F) >> 2);
0774     mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_STS & 0x7F) >> 2);
0775     mask |= 1 << ((mmTPC0_QM_CQ_CTL_STS & 0x7F) >> 2);
0776     mask |= 1 << ((mmTPC0_QM_CQ_STS0 & 0x7F) >> 2);
0777     mask |= 1 << ((mmTPC0_QM_CQ_STS1 & 0x7F) >> 2);
0778     mask |= 1 << ((mmTPC0_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
0779     mask |= 1 << ((mmTPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
0780     mask |= 1 << ((mmTPC0_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
0781     mask |= 1 << ((mmTPC0_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
0782 
0783     WREG32(pb_addr + word_offset, ~mask);
0784 
0785     pb_addr = (mmTPC0_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
0786     word_offset = ((mmTPC0_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
0787     mask = 1 << ((mmTPC0_QM_CQ_IFIFO_CNT & 0x7F) >> 2);
0788     mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
0789     mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
0790     mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
0791     mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
0792     mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
0793     mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
0794     mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
0795     mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
0796     mask |= 1 << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
0797     mask |= 1 << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
0798     mask |= 1 << ((mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
0799     mask |= 1 << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
0800     mask |= 1 << ((mmTPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
0801     mask |= 1 << ((mmTPC0_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
0802 
0803     WREG32(pb_addr + word_offset, ~mask);
0804 
0805     pb_addr = (mmTPC0_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
0806     word_offset = ((mmTPC0_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
0807     mask = 1 << ((mmTPC0_CMDQ_GLBL_CFG0 & 0x7F) >> 2);
0808     mask |= 1 << ((mmTPC0_CMDQ_GLBL_CFG1 & 0x7F) >> 2);
0809     mask |= 1 << ((mmTPC0_CMDQ_GLBL_PROT & 0x7F) >> 2);
0810     mask |= 1 << ((mmTPC0_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2);
0811     mask |= 1 << ((mmTPC0_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
0812     mask |= 1 << ((mmTPC0_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
0813     mask |= 1 << ((mmTPC0_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2);
0814     mask |= 1 << ((mmTPC0_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2);
0815     mask |= 1 << ((mmTPC0_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
0816     mask |= 1 << ((mmTPC0_CMDQ_GLBL_STS0 & 0x7F) >> 2);
0817     mask |= 1 << ((mmTPC0_CMDQ_GLBL_STS1 & 0x7F) >> 2);
0818 
0819     WREG32(pb_addr + word_offset, ~mask);
0820 
0821     pb_addr = (mmTPC0_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
0822     word_offset = ((mmTPC0_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
0823     mask = 1 << ((mmTPC0_CMDQ_CQ_CFG0 & 0x7F) >> 2);
0824     mask |= 1 << ((mmTPC0_CMDQ_CQ_CFG1 & 0x7F) >> 2);
0825     mask |= 1 << ((mmTPC0_CMDQ_CQ_ARUSER & 0x7F) >> 2);
0826     mask |= 1 << ((mmTPC0_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2);
0827     mask |= 1 << ((mmTPC0_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2);
0828     mask |= 1 << ((mmTPC0_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2);
0829     mask |= 1 << ((mmTPC0_CMDQ_CQ_CTL_STS & 0x7F) >> 2);
0830     mask |= 1 << ((mmTPC0_CMDQ_CQ_STS0 & 0x7F) >> 2);
0831     mask |= 1 << ((mmTPC0_CMDQ_CQ_STS1 & 0x7F) >> 2);
0832     mask |= 1 << ((mmTPC0_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
0833     mask |= 1 << ((mmTPC0_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
0834     mask |= 1 << ((mmTPC0_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
0835     mask |= 1 << ((mmTPC0_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
0836 
0837     WREG32(pb_addr + word_offset, ~mask);
0838 
0839     pb_addr = (mmTPC0_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
0840     word_offset = ((mmTPC0_CMDQ_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
0841     mask = 1 << ((mmTPC0_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2);
0842     mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
0843     mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
0844     mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
0845     mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
0846     mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
0847     mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
0848     mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
0849     mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
0850     mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
0851     mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
0852     mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
0853     mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
0854     mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
0855     mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
0856     mask |= 1 << ((mmTPC0_CMDQ_CP_STS & 0x7F) >> 2);
0857     mask |= 1 << ((mmTPC0_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2);
0858 
0859     WREG32(pb_addr + word_offset, ~mask);
0860 
0861     pb_addr = (mmTPC0_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS;
0862     word_offset = ((mmTPC0_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7)
0863             << 2;
0864     mask = 1 << ((mmTPC0_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2);
0865     mask |= 1 << ((mmTPC0_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2);
0866     mask |= 1 << ((mmTPC0_CMDQ_CP_DBG_0 & 0x7F) >> 2);
0867     mask |= 1 << ((mmTPC0_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2);
0868     mask |= 1 << ((mmTPC0_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2);
0869 
0870     WREG32(pb_addr + word_offset, ~mask);
0871 
0872     goya_pb_set_block(hdev, mmTPC1_RTR_BASE);
0873     goya_pb_set_block(hdev, mmTPC1_RD_REGULATOR_BASE);
0874     goya_pb_set_block(hdev, mmTPC1_WR_REGULATOR_BASE);
0875 
0876     pb_addr = (mmTPC1_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS;
0877     word_offset = ((mmTPC1_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2;
0878 
0879     mask = 1 << ((mmTPC1_CFG_SEMAPHORE & 0x7F) >> 2);
0880     mask |= 1 << ((mmTPC1_CFG_VFLAGS & 0x7F) >> 2);
0881     mask |= 1 << ((mmTPC1_CFG_SFLAGS & 0x7F) >> 2);
0882     mask |= 1 << ((mmTPC1_CFG_STATUS & 0x7F) >> 2);
0883 
0884     WREG32(pb_addr + word_offset, ~mask);
0885 
0886     pb_addr = (mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS;
0887     word_offset = ((mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH &
0888             PROT_BITS_OFFS) >> 7) << 2;
0889     mask = 1 << ((mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2);
0890     mask |= 1 << ((mmTPC1_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
0891     mask |= 1 << ((mmTPC1_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
0892     mask |= 1 << ((mmTPC1_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
0893     mask |= 1 << ((mmTPC1_CFG_TPC_STALL & 0x7F) >> 2);
0894     mask |= 1 << ((mmTPC1_CFG_MSS_CONFIG & 0x7F) >> 2);
0895     mask |= 1 << ((mmTPC1_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
0896     mask |= 1 << ((mmTPC1_CFG_TPC_INTR_MASK & 0x7F) >> 2);
0897 
0898     WREG32(pb_addr + word_offset, ~mask);
0899 
0900     pb_addr = (mmTPC1_CFG_ARUSER & ~0xFFF) + PROT_BITS_OFFS;
0901     word_offset = ((mmTPC1_CFG_ARUSER & PROT_BITS_OFFS) >> 7) << 2;
0902     mask = 1 << ((mmTPC1_CFG_ARUSER & 0x7F) >> 2);
0903     mask |= 1 << ((mmTPC1_CFG_AWUSER & 0x7F) >> 2);
0904 
0905     WREG32(pb_addr + word_offset, ~mask);
0906 
0907     pb_addr = (mmTPC1_CFG_FUNC_MBIST_CNTRL & ~0xFFF) + PROT_BITS_OFFS;
0908     word_offset = ((mmTPC1_CFG_FUNC_MBIST_CNTRL & PROT_BITS_OFFS) >> 7)
0909             << 2;
0910     mask = 1 << ((mmTPC1_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2);
0911     mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_PAT & 0x7F) >> 2);
0912     mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2);
0913     mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2);
0914     mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2);
0915     mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2);
0916     mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2);
0917     mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2);
0918     mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2);
0919     mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2);
0920     mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2);
0921     mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2);
0922 
0923     WREG32(pb_addr + word_offset, ~mask);
0924 
0925     pb_addr = (mmTPC1_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
0926     word_offset = ((mmTPC1_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
0927     mask = 1 << ((mmTPC1_QM_GLBL_CFG0 & 0x7F) >> 2);
0928     mask |= 1 << ((mmTPC1_QM_GLBL_CFG1 & 0x7F) >> 2);
0929     mask |= 1 << ((mmTPC1_QM_GLBL_PROT & 0x7F) >> 2);
0930     mask |= 1 << ((mmTPC1_QM_GLBL_ERR_CFG & 0x7F) >> 2);
0931     mask |= 1 << ((mmTPC1_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
0932     mask |= 1 << ((mmTPC1_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
0933     mask |= 1 << ((mmTPC1_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
0934     mask |= 1 << ((mmTPC1_QM_GLBL_SECURE_PROPS & 0x7F) >> 2);
0935     mask |= 1 << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
0936     mask |= 1 << ((mmTPC1_QM_GLBL_STS0 & 0x7F) >> 2);
0937     mask |= 1 << ((mmTPC1_QM_GLBL_STS1 & 0x7F) >> 2);
0938     mask |= 1 << ((mmTPC1_QM_PQ_BASE_LO & 0x7F) >> 2);
0939     mask |= 1 << ((mmTPC1_QM_PQ_BASE_HI & 0x7F) >> 2);
0940     mask |= 1 << ((mmTPC1_QM_PQ_SIZE & 0x7F) >> 2);
0941     mask |= 1 << ((mmTPC1_QM_PQ_PI & 0x7F) >> 2);
0942     mask |= 1 << ((mmTPC1_QM_PQ_CI & 0x7F) >> 2);
0943     mask |= 1 << ((mmTPC1_QM_PQ_CFG0 & 0x7F) >> 2);
0944     mask |= 1 << ((mmTPC1_QM_PQ_CFG1 & 0x7F) >> 2);
0945     mask |= 1 << ((mmTPC1_QM_PQ_ARUSER & 0x7F) >> 2);
0946 
0947     WREG32(pb_addr + word_offset, ~mask);
0948 
0949     pb_addr = (mmTPC1_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS;
0950     word_offset = ((mmTPC1_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2;
0951     mask = 1 << ((mmTPC1_QM_PQ_PUSH0 & 0x7F) >> 2);
0952     mask |= 1 << ((mmTPC1_QM_PQ_PUSH1 & 0x7F) >> 2);
0953     mask |= 1 << ((mmTPC1_QM_PQ_PUSH2 & 0x7F) >> 2);
0954     mask |= 1 << ((mmTPC1_QM_PQ_PUSH3 & 0x7F) >> 2);
0955     mask |= 1 << ((mmTPC1_QM_PQ_STS0 & 0x7F) >> 2);
0956     mask |= 1 << ((mmTPC1_QM_PQ_STS1 & 0x7F) >> 2);
0957     mask |= 1 << ((mmTPC1_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
0958     mask |= 1 << ((mmTPC1_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
0959     mask |= 1 << ((mmTPC1_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
0960     mask |= 1 << ((mmTPC1_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
0961     mask |= 1 << ((mmTPC1_QM_CQ_CFG0 & 0x7F) >> 2);
0962     mask |= 1 << ((mmTPC1_QM_CQ_CFG1 & 0x7F) >> 2);
0963     mask |= 1 << ((mmTPC1_QM_CQ_ARUSER & 0x7F) >> 2);
0964     mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO & 0x7F) >> 2);
0965     mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI & 0x7F) >> 2);
0966     mask |= 1 << ((mmTPC1_QM_CQ_TSIZE & 0x7F) >> 2);
0967     mask |= 1 << ((mmTPC1_QM_CQ_CTL & 0x7F) >> 2);
0968     mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_STS & 0x7F) >> 2);
0969     mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_STS & 0x7F) >> 2);
0970     mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_STS & 0x7F) >> 2);
0971     mask |= 1 << ((mmTPC1_QM_CQ_CTL_STS & 0x7F) >> 2);
0972     mask |= 1 << ((mmTPC1_QM_CQ_STS0 & 0x7F) >> 2);
0973     mask |= 1 << ((mmTPC1_QM_CQ_STS1 & 0x7F) >> 2);
0974     mask |= 1 << ((mmTPC1_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
0975     mask |= 1 << ((mmTPC1_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
0976     mask |= 1 << ((mmTPC1_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
0977     mask |= 1 << ((mmTPC1_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
0978 
0979     WREG32(pb_addr + word_offset, ~mask);
0980 
0981     pb_addr = (mmTPC1_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
0982     word_offset = ((mmTPC1_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
0983     mask = 1 << ((mmTPC1_QM_CQ_IFIFO_CNT & 0x7F) >> 2);
0984     mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
0985     mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
0986     mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
0987     mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
0988     mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
0989     mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
0990     mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
0991     mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
0992     mask |= 1 << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
0993     mask |= 1 << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
0994     mask |= 1 << ((mmTPC1_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
0995     mask |= 1 << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
0996     mask |= 1 << ((mmTPC1_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
0997     mask |= 1 << ((mmTPC1_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
0998 
0999     WREG32(pb_addr + word_offset, ~mask);
1000 
1001     pb_addr = (mmTPC1_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
1002     word_offset = ((mmTPC1_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
1003     mask = 1 << ((mmTPC1_CMDQ_GLBL_CFG0 & 0x7F) >> 2);
1004     mask |= 1 << ((mmTPC1_CMDQ_GLBL_CFG1 & 0x7F) >> 2);
1005     mask |= 1 << ((mmTPC1_CMDQ_GLBL_PROT & 0x7F) >> 2);
1006     mask |= 1 << ((mmTPC1_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2);
1007     mask |= 1 << ((mmTPC1_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
1008     mask |= 1 << ((mmTPC1_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
1009     mask |= 1 << ((mmTPC1_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2);
1010     mask |= 1 << ((mmTPC1_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2);
1011     mask |= 1 << ((mmTPC1_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
1012     mask |= 1 << ((mmTPC1_CMDQ_GLBL_STS0 & 0x7F) >> 2);
1013     mask |= 1 << ((mmTPC1_CMDQ_GLBL_STS1 & 0x7F) >> 2);
1014 
1015     WREG32(pb_addr + word_offset, ~mask);
1016 
1017     pb_addr = (mmTPC1_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
1018     word_offset = ((mmTPC1_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
1019     mask = 1 << ((mmTPC1_CMDQ_CQ_CFG0 & 0x7F) >> 2);
1020     mask |= 1 << ((mmTPC1_CMDQ_CQ_CFG1 & 0x7F) >> 2);
1021     mask |= 1 << ((mmTPC1_CMDQ_CQ_ARUSER & 0x7F) >> 2);
1022     mask |= 1 << ((mmTPC1_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2);
1023     mask |= 1 << ((mmTPC1_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2);
1024     mask |= 1 << ((mmTPC1_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2);
1025     mask |= 1 << ((mmTPC1_CMDQ_CQ_CTL_STS & 0x7F) >> 2);
1026     mask |= 1 << ((mmTPC1_CMDQ_CQ_STS0 & 0x7F) >> 2);
1027     mask |= 1 << ((mmTPC1_CMDQ_CQ_STS1 & 0x7F) >> 2);
1028     mask |= 1 << ((mmTPC1_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1029     mask |= 1 << ((mmTPC1_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1030     mask |= 1 << ((mmTPC1_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1031     mask |= 1 << ((mmTPC1_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1032 
1033     WREG32(pb_addr + word_offset, ~mask);
1034 
1035     pb_addr = (mmTPC1_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
1036     word_offset = ((mmTPC1_CMDQ_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
1037     mask = 1 << ((mmTPC1_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2);
1038     mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
1039     mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
1040     mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
1041     mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
1042     mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
1043     mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
1044     mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
1045     mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
1046     mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
1047     mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
1048     mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
1049     mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
1050     mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
1051     mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
1052     mask |= 1 << ((mmTPC1_CMDQ_CP_STS & 0x7F) >> 2);
1053     mask |= 1 << ((mmTPC1_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2);
1054 
1055     WREG32(pb_addr + word_offset, ~mask);
1056 
1057     pb_addr = (mmTPC1_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS;
1058     word_offset = ((mmTPC1_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7)
1059             << 2;
1060     mask = 1 << ((mmTPC1_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2);
1061     mask |= 1 << ((mmTPC1_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2);
1062     mask |= 1 << ((mmTPC1_CMDQ_CP_DBG_0 & 0x7F) >> 2);
1063     mask |= 1 << ((mmTPC1_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2);
1064     mask |= 1 << ((mmTPC1_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2);
1065 
1066     WREG32(pb_addr + word_offset, ~mask);
1067 
1068     goya_pb_set_block(hdev, mmTPC2_RTR_BASE);
1069     goya_pb_set_block(hdev, mmTPC2_RD_REGULATOR_BASE);
1070     goya_pb_set_block(hdev, mmTPC2_WR_REGULATOR_BASE);
1071 
1072     pb_addr = (mmTPC2_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS;
1073     word_offset = ((mmTPC2_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2;
1074 
1075     mask = 1 << ((mmTPC2_CFG_SEMAPHORE & 0x7F) >> 2);
1076     mask |= 1 << ((mmTPC2_CFG_VFLAGS & 0x7F) >> 2);
1077     mask |= 1 << ((mmTPC2_CFG_SFLAGS & 0x7F) >> 2);
1078     mask |= 1 << ((mmTPC2_CFG_STATUS & 0x7F) >> 2);
1079 
1080     WREG32(pb_addr + word_offset, ~mask);
1081 
1082     pb_addr = (mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS;
1083     word_offset = ((mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH &
1084             PROT_BITS_OFFS) >> 7) << 2;
1085     mask = 1 << ((mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2);
1086     mask |= 1 << ((mmTPC2_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
1087     mask |= 1 << ((mmTPC2_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
1088     mask |= 1 << ((mmTPC2_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
1089     mask |= 1 << ((mmTPC2_CFG_TPC_STALL & 0x7F) >> 2);
1090     mask |= 1 << ((mmTPC2_CFG_MSS_CONFIG & 0x7F) >> 2);
1091     mask |= 1 << ((mmTPC2_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
1092     mask |= 1 << ((mmTPC2_CFG_TPC_INTR_MASK & 0x7F) >> 2);
1093 
1094     WREG32(pb_addr + word_offset, ~mask);
1095 
1096     pb_addr = (mmTPC2_CFG_ARUSER & ~0xFFF) + PROT_BITS_OFFS;
1097     word_offset = ((mmTPC2_CFG_ARUSER & PROT_BITS_OFFS) >> 7) << 2;
1098     mask = 1 << ((mmTPC2_CFG_ARUSER & 0x7F) >> 2);
1099     mask |= 1 << ((mmTPC2_CFG_AWUSER & 0x7F) >> 2);
1100 
1101     WREG32(pb_addr + word_offset, ~mask);
1102 
1103     pb_addr = (mmTPC2_CFG_FUNC_MBIST_CNTRL & ~0xFFF) + PROT_BITS_OFFS;
1104     word_offset = ((mmTPC2_CFG_FUNC_MBIST_CNTRL & PROT_BITS_OFFS) >> 7)
1105             << 2;
1106     mask = 1 << ((mmTPC2_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2);
1107     mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_PAT & 0x7F) >> 2);
1108     mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2);
1109     mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2);
1110     mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2);
1111     mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2);
1112     mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2);
1113     mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2);
1114     mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2);
1115     mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2);
1116     mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2);
1117     mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2);
1118 
1119     WREG32(pb_addr + word_offset, ~mask);
1120 
1121     pb_addr = (mmTPC2_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
1122     word_offset = ((mmTPC2_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
1123     mask = 1 << ((mmTPC2_QM_GLBL_CFG0 & 0x7F) >> 2);
1124     mask |= 1 << ((mmTPC2_QM_GLBL_CFG1 & 0x7F) >> 2);
1125     mask |= 1 << ((mmTPC2_QM_GLBL_PROT & 0x7F) >> 2);
1126     mask |= 1 << ((mmTPC2_QM_GLBL_ERR_CFG & 0x7F) >> 2);
1127     mask |= 1 << ((mmTPC2_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
1128     mask |= 1 << ((mmTPC2_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
1129     mask |= 1 << ((mmTPC2_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
1130     mask |= 1 << ((mmTPC2_QM_GLBL_SECURE_PROPS & 0x7F) >> 2);
1131     mask |= 1 << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
1132     mask |= 1 << ((mmTPC2_QM_GLBL_STS0 & 0x7F) >> 2);
1133     mask |= 1 << ((mmTPC2_QM_GLBL_STS1 & 0x7F) >> 2);
1134     mask |= 1 << ((mmTPC2_QM_PQ_BASE_LO & 0x7F) >> 2);
1135     mask |= 1 << ((mmTPC2_QM_PQ_BASE_HI & 0x7F) >> 2);
1136     mask |= 1 << ((mmTPC2_QM_PQ_SIZE & 0x7F) >> 2);
1137     mask |= 1 << ((mmTPC2_QM_PQ_PI & 0x7F) >> 2);
1138     mask |= 1 << ((mmTPC2_QM_PQ_CI & 0x7F) >> 2);
1139     mask |= 1 << ((mmTPC2_QM_PQ_CFG0 & 0x7F) >> 2);
1140     mask |= 1 << ((mmTPC2_QM_PQ_CFG1 & 0x7F) >> 2);
1141     mask |= 1 << ((mmTPC2_QM_PQ_ARUSER & 0x7F) >> 2);
1142 
1143     WREG32(pb_addr + word_offset, ~mask);
1144 
1145     pb_addr = (mmTPC2_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS;
1146     word_offset = ((mmTPC2_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2;
1147     mask = 1 << ((mmTPC2_QM_PQ_PUSH0 & 0x7F) >> 2);
1148     mask |= 1 << ((mmTPC2_QM_PQ_PUSH1 & 0x7F) >> 2);
1149     mask |= 1 << ((mmTPC2_QM_PQ_PUSH2 & 0x7F) >> 2);
1150     mask |= 1 << ((mmTPC2_QM_PQ_PUSH3 & 0x7F) >> 2);
1151     mask |= 1 << ((mmTPC2_QM_PQ_STS0 & 0x7F) >> 2);
1152     mask |= 1 << ((mmTPC2_QM_PQ_STS1 & 0x7F) >> 2);
1153     mask |= 1 << ((mmTPC2_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1154     mask |= 1 << ((mmTPC2_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1155     mask |= 1 << ((mmTPC2_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1156     mask |= 1 << ((mmTPC2_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1157     mask |= 1 << ((mmTPC2_QM_CQ_CFG0 & 0x7F) >> 2);
1158     mask |= 1 << ((mmTPC2_QM_CQ_CFG1 & 0x7F) >> 2);
1159     mask |= 1 << ((mmTPC2_QM_CQ_ARUSER & 0x7F) >> 2);
1160     mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO & 0x7F) >> 2);
1161     mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI & 0x7F) >> 2);
1162     mask |= 1 << ((mmTPC2_QM_CQ_TSIZE & 0x7F) >> 2);
1163     mask |= 1 << ((mmTPC2_QM_CQ_CTL & 0x7F) >> 2);
1164     mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_STS & 0x7F) >> 2);
1165     mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_STS & 0x7F) >> 2);
1166     mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_STS & 0x7F) >> 2);
1167     mask |= 1 << ((mmTPC2_QM_CQ_CTL_STS & 0x7F) >> 2);
1168     mask |= 1 << ((mmTPC2_QM_CQ_STS0 & 0x7F) >> 2);
1169     mask |= 1 << ((mmTPC2_QM_CQ_STS1 & 0x7F) >> 2);
1170     mask |= 1 << ((mmTPC2_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1171     mask |= 1 << ((mmTPC2_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1172     mask |= 1 << ((mmTPC2_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1173     mask |= 1 << ((mmTPC2_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1174 
1175     WREG32(pb_addr + word_offset, ~mask);
1176 
1177     pb_addr = (mmTPC2_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
1178     word_offset = ((mmTPC2_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
1179     mask = 1 << ((mmTPC2_QM_CQ_IFIFO_CNT & 0x7F) >> 2);
1180     mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
1181     mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
1182     mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
1183     mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
1184     mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
1185     mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
1186     mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
1187     mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
1188     mask |= 1 << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
1189     mask |= 1 << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
1190     mask |= 1 << ((mmTPC2_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
1191     mask |= 1 << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
1192     mask |= 1 << ((mmTPC2_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
1193     mask |= 1 << ((mmTPC2_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
1194 
1195     WREG32(pb_addr + word_offset, ~mask);
1196 
1197     pb_addr = (mmTPC2_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
1198     word_offset = ((mmTPC2_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
1199     mask = 1 << ((mmTPC2_CMDQ_GLBL_CFG0 & 0x7F) >> 2);
1200     mask |= 1 << ((mmTPC2_CMDQ_GLBL_CFG1 & 0x7F) >> 2);
1201     mask |= 1 << ((mmTPC2_CMDQ_GLBL_PROT & 0x7F) >> 2);
1202     mask |= 1 << ((mmTPC2_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2);
1203     mask |= 1 << ((mmTPC2_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
1204     mask |= 1 << ((mmTPC2_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
1205     mask |= 1 << ((mmTPC2_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2);
1206     mask |= 1 << ((mmTPC2_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2);
1207     mask |= 1 << ((mmTPC2_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
1208     mask |= 1 << ((mmTPC2_CMDQ_GLBL_STS0 & 0x7F) >> 2);
1209     mask |= 1 << ((mmTPC2_CMDQ_GLBL_STS1 & 0x7F) >> 2);
1210 
1211     WREG32(pb_addr + word_offset, ~mask);
1212 
1213     pb_addr = (mmTPC2_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
1214     word_offset = ((mmTPC2_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
1215     mask = 1 << ((mmTPC2_CMDQ_CQ_CFG0 & 0x7F) >> 2);
1216     mask |= 1 << ((mmTPC2_CMDQ_CQ_CFG1 & 0x7F) >> 2);
1217     mask |= 1 << ((mmTPC2_CMDQ_CQ_ARUSER & 0x7F) >> 2);
1218     mask |= 1 << ((mmTPC2_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2);
1219     mask |= 1 << ((mmTPC2_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2);
1220     mask |= 1 << ((mmTPC2_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2);
1221     mask |= 1 << ((mmTPC2_CMDQ_CQ_CTL_STS & 0x7F) >> 2);
1222     mask |= 1 << ((mmTPC2_CMDQ_CQ_STS0 & 0x7F) >> 2);
1223     mask |= 1 << ((mmTPC2_CMDQ_CQ_STS1 & 0x7F) >> 2);
1224     mask |= 1 << ((mmTPC2_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1225     mask |= 1 << ((mmTPC2_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1226     mask |= 1 << ((mmTPC2_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1227     mask |= 1 << ((mmTPC2_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1228 
1229     WREG32(pb_addr + word_offset, ~mask);
1230 
1231     pb_addr = (mmTPC2_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
1232     word_offset = ((mmTPC2_CMDQ_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
1233     mask = 1 << ((mmTPC2_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2);
1234     mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
1235     mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
1236     mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
1237     mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
1238     mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
1239     mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
1240     mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
1241     mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
1242     mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
1243     mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
1244     mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
1245     mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
1246     mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
1247     mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
1248     mask |= 1 << ((mmTPC2_CMDQ_CP_STS & 0x7F) >> 2);
1249     mask |= 1 << ((mmTPC2_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2);
1250 
1251     WREG32(pb_addr + word_offset, ~mask);
1252 
1253     pb_addr = (mmTPC2_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS;
1254     word_offset = ((mmTPC2_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7)
1255             << 2;
1256     mask = 1 << ((mmTPC2_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2);
1257     mask |= 1 << ((mmTPC2_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2);
1258     mask |= 1 << ((mmTPC2_CMDQ_CP_DBG_0 & 0x7F) >> 2);
1259     mask |= 1 << ((mmTPC2_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2);
1260     mask |= 1 << ((mmTPC2_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2);
1261 
1262     WREG32(pb_addr + word_offset, ~mask);
1263 
1264     goya_pb_set_block(hdev, mmTPC3_RTR_BASE);
1265     goya_pb_set_block(hdev, mmTPC3_RD_REGULATOR_BASE);
1266     goya_pb_set_block(hdev, mmTPC3_WR_REGULATOR_BASE);
1267 
1268     pb_addr = (mmTPC3_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS;
1269     word_offset = ((mmTPC3_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2;
1270 
1271     mask = 1 << ((mmTPC3_CFG_SEMAPHORE & 0x7F) >> 2);
1272     mask |= 1 << ((mmTPC3_CFG_VFLAGS & 0x7F) >> 2);
1273     mask |= 1 << ((mmTPC3_CFG_SFLAGS & 0x7F) >> 2);
1274     mask |= 1 << ((mmTPC3_CFG_STATUS & 0x7F) >> 2);
1275 
1276     WREG32(pb_addr + word_offset, ~mask);
1277 
1278     pb_addr = (mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS;
1279     word_offset = ((mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH
1280             & PROT_BITS_OFFS) >> 7) << 2;
1281     mask = 1 << ((mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2);
1282     mask |= 1 << ((mmTPC3_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
1283     mask |= 1 << ((mmTPC3_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
1284     mask |= 1 << ((mmTPC3_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
1285     mask |= 1 << ((mmTPC3_CFG_TPC_STALL & 0x7F) >> 2);
1286     mask |= 1 << ((mmTPC3_CFG_MSS_CONFIG & 0x7F) >> 2);
1287     mask |= 1 << ((mmTPC3_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
1288     mask |= 1 << ((mmTPC3_CFG_TPC_INTR_MASK & 0x7F) >> 2);
1289 
1290     WREG32(pb_addr + word_offset, ~mask);
1291 
1292     pb_addr = (mmTPC3_CFG_ARUSER & ~0xFFF) + PROT_BITS_OFFS;
1293     word_offset = ((mmTPC3_CFG_ARUSER & PROT_BITS_OFFS) >> 7) << 2;
1294     mask = 1 << ((mmTPC3_CFG_ARUSER & 0x7F) >> 2);
1295     mask |= 1 << ((mmTPC3_CFG_AWUSER & 0x7F) >> 2);
1296 
1297     WREG32(pb_addr + word_offset, ~mask);
1298 
1299     pb_addr = (mmTPC3_CFG_FUNC_MBIST_CNTRL & ~0xFFF) + PROT_BITS_OFFS;
1300     word_offset = ((mmTPC3_CFG_FUNC_MBIST_CNTRL
1301             & PROT_BITS_OFFS) >> 7) << 2;
1302     mask = 1 << ((mmTPC3_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2);
1303     mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_PAT & 0x7F) >> 2);
1304     mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2);
1305     mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2);
1306     mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2);
1307     mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2);
1308     mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2);
1309     mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2);
1310     mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2);
1311     mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2);
1312     mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2);
1313     mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2);
1314 
1315     WREG32(pb_addr + word_offset, ~mask);
1316 
1317     pb_addr = (mmTPC3_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
1318     word_offset = ((mmTPC3_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
1319     mask = 1 << ((mmTPC3_QM_GLBL_CFG0 & 0x7F) >> 2);
1320     mask |= 1 << ((mmTPC3_QM_GLBL_CFG1 & 0x7F) >> 2);
1321     mask |= 1 << ((mmTPC3_QM_GLBL_PROT & 0x7F) >> 2);
1322     mask |= 1 << ((mmTPC3_QM_GLBL_ERR_CFG & 0x7F) >> 2);
1323     mask |= 1 << ((mmTPC3_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
1324     mask |= 1 << ((mmTPC3_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
1325     mask |= 1 << ((mmTPC3_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
1326     mask |= 1 << ((mmTPC3_QM_GLBL_SECURE_PROPS & 0x7F) >> 2);
1327     mask |= 1 << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
1328     mask |= 1 << ((mmTPC3_QM_GLBL_STS0 & 0x7F) >> 2);
1329     mask |= 1 << ((mmTPC3_QM_GLBL_STS1 & 0x7F) >> 2);
1330     mask |= 1 << ((mmTPC3_QM_PQ_BASE_LO & 0x7F) >> 2);
1331     mask |= 1 << ((mmTPC3_QM_PQ_BASE_HI & 0x7F) >> 2);
1332     mask |= 1 << ((mmTPC3_QM_PQ_SIZE & 0x7F) >> 2);
1333     mask |= 1 << ((mmTPC3_QM_PQ_PI & 0x7F) >> 2);
1334     mask |= 1 << ((mmTPC3_QM_PQ_CI & 0x7F) >> 2);
1335     mask |= 1 << ((mmTPC3_QM_PQ_CFG0 & 0x7F) >> 2);
1336     mask |= 1 << ((mmTPC3_QM_PQ_CFG1 & 0x7F) >> 2);
1337     mask |= 1 << ((mmTPC3_QM_PQ_ARUSER & 0x7F) >> 2);
1338 
1339     WREG32(pb_addr + word_offset, ~mask);
1340 
1341     pb_addr = (mmTPC3_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS;
1342     word_offset = ((mmTPC3_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2;
1343     mask = 1 << ((mmTPC3_QM_PQ_PUSH0 & 0x7F) >> 2);
1344     mask |= 1 << ((mmTPC3_QM_PQ_PUSH1 & 0x7F) >> 2);
1345     mask |= 1 << ((mmTPC3_QM_PQ_PUSH2 & 0x7F) >> 2);
1346     mask |= 1 << ((mmTPC3_QM_PQ_PUSH3 & 0x7F) >> 2);
1347     mask |= 1 << ((mmTPC3_QM_PQ_STS0 & 0x7F) >> 2);
1348     mask |= 1 << ((mmTPC3_QM_PQ_STS1 & 0x7F) >> 2);
1349     mask |= 1 << ((mmTPC3_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1350     mask |= 1 << ((mmTPC3_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1351     mask |= 1 << ((mmTPC3_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1352     mask |= 1 << ((mmTPC3_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1353     mask |= 1 << ((mmTPC3_QM_CQ_CFG0 & 0x7F) >> 2);
1354     mask |= 1 << ((mmTPC3_QM_CQ_CFG1 & 0x7F) >> 2);
1355     mask |= 1 << ((mmTPC3_QM_CQ_ARUSER & 0x7F) >> 2);
1356     mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO & 0x7F) >> 2);
1357     mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI & 0x7F) >> 2);
1358     mask |= 1 << ((mmTPC3_QM_CQ_TSIZE & 0x7F) >> 2);
1359     mask |= 1 << ((mmTPC3_QM_CQ_CTL & 0x7F) >> 2);
1360     mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_STS & 0x7F) >> 2);
1361     mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_STS & 0x7F) >> 2);
1362     mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_STS & 0x7F) >> 2);
1363     mask |= 1 << ((mmTPC3_QM_CQ_CTL_STS & 0x7F) >> 2);
1364     mask |= 1 << ((mmTPC3_QM_CQ_STS0 & 0x7F) >> 2);
1365     mask |= 1 << ((mmTPC3_QM_CQ_STS1 & 0x7F) >> 2);
1366     mask |= 1 << ((mmTPC3_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1367     mask |= 1 << ((mmTPC3_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1368     mask |= 1 << ((mmTPC3_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1369     mask |= 1 << ((mmTPC3_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1370 
1371     WREG32(pb_addr + word_offset, ~mask);
1372 
1373     pb_addr = (mmTPC3_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
1374     word_offset = ((mmTPC3_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
1375     mask = 1 << ((mmTPC3_QM_CQ_IFIFO_CNT & 0x7F) >> 2);
1376     mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
1377     mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
1378     mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
1379     mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
1380     mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
1381     mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
1382     mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
1383     mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
1384     mask |= 1 << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
1385     mask |= 1 << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
1386     mask |= 1 << ((mmTPC3_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
1387     mask |= 1 << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
1388     mask |= 1 << ((mmTPC3_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
1389     mask |= 1 << ((mmTPC3_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
1390 
1391     WREG32(pb_addr + word_offset, ~mask);
1392 
1393     pb_addr = (mmTPC3_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
1394     word_offset = ((mmTPC3_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
1395     mask = 1 << ((mmTPC3_CMDQ_GLBL_CFG0 & 0x7F) >> 2);
1396     mask |= 1 << ((mmTPC3_CMDQ_GLBL_CFG1 & 0x7F) >> 2);
1397     mask |= 1 << ((mmTPC3_CMDQ_GLBL_PROT & 0x7F) >> 2);
1398     mask |= 1 << ((mmTPC3_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2);
1399     mask |= 1 << ((mmTPC3_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
1400     mask |= 1 << ((mmTPC3_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
1401     mask |= 1 << ((mmTPC3_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2);
1402     mask |= 1 << ((mmTPC3_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2);
1403     mask |= 1 << ((mmTPC3_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
1404     mask |= 1 << ((mmTPC3_CMDQ_GLBL_STS0 & 0x7F) >> 2);
1405     mask |= 1 << ((mmTPC3_CMDQ_GLBL_STS1 & 0x7F) >> 2);
1406 
1407     WREG32(pb_addr + word_offset, ~mask);
1408 
1409     pb_addr = (mmTPC3_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
1410     word_offset = ((mmTPC3_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
1411     mask = 1 << ((mmTPC3_CMDQ_CQ_CFG0 & 0x7F) >> 2);
1412     mask |= 1 << ((mmTPC3_CMDQ_CQ_CFG1 & 0x7F) >> 2);
1413     mask |= 1 << ((mmTPC3_CMDQ_CQ_ARUSER & 0x7F) >> 2);
1414     mask |= 1 << ((mmTPC3_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2);
1415     mask |= 1 << ((mmTPC3_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2);
1416     mask |= 1 << ((mmTPC3_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2);
1417     mask |= 1 << ((mmTPC3_CMDQ_CQ_CTL_STS & 0x7F) >> 2);
1418     mask |= 1 << ((mmTPC3_CMDQ_CQ_STS0 & 0x7F) >> 2);
1419     mask |= 1 << ((mmTPC3_CMDQ_CQ_STS1 & 0x7F) >> 2);
1420     mask |= 1 << ((mmTPC3_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1421     mask |= 1 << ((mmTPC3_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1422     mask |= 1 << ((mmTPC3_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1423     mask |= 1 << ((mmTPC3_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1424 
1425     WREG32(pb_addr + word_offset, ~mask);
1426 
1427     pb_addr = (mmTPC3_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
1428     word_offset = ((mmTPC3_CMDQ_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
1429     mask = 1 << ((mmTPC3_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2);
1430     mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
1431     mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
1432     mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
1433     mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
1434     mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
1435     mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
1436     mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
1437     mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
1438     mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
1439     mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
1440     mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
1441     mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
1442     mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
1443     mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
1444     mask |= 1 << ((mmTPC3_CMDQ_CP_STS & 0x7F) >> 2);
1445     mask |= 1 << ((mmTPC3_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2);
1446 
1447     WREG32(pb_addr + word_offset, ~mask);
1448 
1449     pb_addr = (mmTPC3_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS;
1450     word_offset = ((mmTPC3_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7)
1451             << 2;
1452     mask = 1 << ((mmTPC3_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2);
1453     mask |= 1 << ((mmTPC3_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2);
1454     mask |= 1 << ((mmTPC3_CMDQ_CP_DBG_0 & 0x7F) >> 2);
1455     mask |= 1 << ((mmTPC3_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2);
1456     mask |= 1 << ((mmTPC3_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2);
1457 
1458     WREG32(pb_addr + word_offset, ~mask);
1459 
1460     goya_pb_set_block(hdev, mmTPC4_RTR_BASE);
1461     goya_pb_set_block(hdev, mmTPC4_RD_REGULATOR_BASE);
1462     goya_pb_set_block(hdev, mmTPC4_WR_REGULATOR_BASE);
1463 
1464     pb_addr = (mmTPC4_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS;
1465     word_offset = ((mmTPC4_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2;
1466 
1467     mask = 1 << ((mmTPC4_CFG_SEMAPHORE & 0x7F) >> 2);
1468     mask |= 1 << ((mmTPC4_CFG_VFLAGS & 0x7F) >> 2);
1469     mask |= 1 << ((mmTPC4_CFG_SFLAGS & 0x7F) >> 2);
1470     mask |= 1 << ((mmTPC4_CFG_STATUS & 0x7F) >> 2);
1471 
1472     WREG32(pb_addr + word_offset, ~mask);
1473 
1474     pb_addr = (mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS;
1475     word_offset = ((mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH &
1476             PROT_BITS_OFFS) >> 7) << 2;
1477     mask = 1 << ((mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2);
1478     mask |= 1 << ((mmTPC4_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
1479     mask |= 1 << ((mmTPC4_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
1480     mask |= 1 << ((mmTPC4_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
1481     mask |= 1 << ((mmTPC4_CFG_TPC_STALL & 0x7F) >> 2);
1482     mask |= 1 << ((mmTPC4_CFG_MSS_CONFIG & 0x7F) >> 2);
1483     mask |= 1 << ((mmTPC4_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
1484     mask |= 1 << ((mmTPC4_CFG_TPC_INTR_MASK & 0x7F) >> 2);
1485 
1486     WREG32(pb_addr + word_offset, ~mask);
1487 
1488     pb_addr = (mmTPC4_CFG_ARUSER & ~0xFFF) + PROT_BITS_OFFS;
1489     word_offset = ((mmTPC4_CFG_ARUSER & PROT_BITS_OFFS) >> 7) << 2;
1490     mask = 1 << ((mmTPC4_CFG_ARUSER & 0x7F) >> 2);
1491     mask |= 1 << ((mmTPC4_CFG_AWUSER & 0x7F) >> 2);
1492 
1493     WREG32(pb_addr + word_offset, ~mask);
1494 
1495     pb_addr = (mmTPC4_CFG_FUNC_MBIST_CNTRL & ~0xFFF) + PROT_BITS_OFFS;
1496     word_offset = ((mmTPC4_CFG_FUNC_MBIST_CNTRL &
1497             PROT_BITS_OFFS) >> 7) << 2;
1498     mask = 1 << ((mmTPC4_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2);
1499     mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_PAT & 0x7F) >> 2);
1500     mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2);
1501     mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2);
1502     mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2);
1503     mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2);
1504     mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2);
1505     mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2);
1506     mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2);
1507     mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2);
1508     mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2);
1509     mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2);
1510 
1511     WREG32(pb_addr + word_offset, ~mask);
1512 
1513     pb_addr = (mmTPC4_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
1514     word_offset = ((mmTPC4_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
1515     mask = 1 << ((mmTPC4_QM_GLBL_CFG0 & 0x7F) >> 2);
1516     mask |= 1 << ((mmTPC4_QM_GLBL_CFG1 & 0x7F) >> 2);
1517     mask |= 1 << ((mmTPC4_QM_GLBL_PROT & 0x7F) >> 2);
1518     mask |= 1 << ((mmTPC4_QM_GLBL_ERR_CFG & 0x7F) >> 2);
1519     mask |= 1 << ((mmTPC4_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
1520     mask |= 1 << ((mmTPC4_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
1521     mask |= 1 << ((mmTPC4_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
1522     mask |= 1 << ((mmTPC4_QM_GLBL_SECURE_PROPS & 0x7F) >> 2);
1523     mask |= 1 << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
1524     mask |= 1 << ((mmTPC4_QM_GLBL_STS0 & 0x7F) >> 2);
1525     mask |= 1 << ((mmTPC4_QM_GLBL_STS1 & 0x7F) >> 2);
1526     mask |= 1 << ((mmTPC4_QM_PQ_BASE_LO & 0x7F) >> 2);
1527     mask |= 1 << ((mmTPC4_QM_PQ_BASE_HI & 0x7F) >> 2);
1528     mask |= 1 << ((mmTPC4_QM_PQ_SIZE & 0x7F) >> 2);
1529     mask |= 1 << ((mmTPC4_QM_PQ_PI & 0x7F) >> 2);
1530     mask |= 1 << ((mmTPC4_QM_PQ_CI & 0x7F) >> 2);
1531     mask |= 1 << ((mmTPC4_QM_PQ_CFG0 & 0x7F) >> 2);
1532     mask |= 1 << ((mmTPC4_QM_PQ_CFG1 & 0x7F) >> 2);
1533     mask |= 1 << ((mmTPC4_QM_PQ_ARUSER & 0x7F) >> 2);
1534 
1535     WREG32(pb_addr + word_offset, ~mask);
1536 
1537     pb_addr = (mmTPC4_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS;
1538     word_offset = ((mmTPC4_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2;
1539     mask = 1 << ((mmTPC4_QM_PQ_PUSH0 & 0x7F) >> 2);
1540     mask |= 1 << ((mmTPC4_QM_PQ_PUSH1 & 0x7F) >> 2);
1541     mask |= 1 << ((mmTPC4_QM_PQ_PUSH2 & 0x7F) >> 2);
1542     mask |= 1 << ((mmTPC4_QM_PQ_PUSH3 & 0x7F) >> 2);
1543     mask |= 1 << ((mmTPC4_QM_PQ_STS0 & 0x7F) >> 2);
1544     mask |= 1 << ((mmTPC4_QM_PQ_STS1 & 0x7F) >> 2);
1545     mask |= 1 << ((mmTPC4_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1546     mask |= 1 << ((mmTPC4_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1547     mask |= 1 << ((mmTPC4_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1548     mask |= 1 << ((mmTPC4_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1549     mask |= 1 << ((mmTPC4_QM_CQ_CFG0 & 0x7F) >> 2);
1550     mask |= 1 << ((mmTPC4_QM_CQ_CFG1 & 0x7F) >> 2);
1551     mask |= 1 << ((mmTPC4_QM_CQ_ARUSER & 0x7F) >> 2);
1552     mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO & 0x7F) >> 2);
1553     mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI & 0x7F) >> 2);
1554     mask |= 1 << ((mmTPC4_QM_CQ_TSIZE & 0x7F) >> 2);
1555     mask |= 1 << ((mmTPC4_QM_CQ_CTL & 0x7F) >> 2);
1556     mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_STS & 0x7F) >> 2);
1557     mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_STS & 0x7F) >> 2);
1558     mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_STS & 0x7F) >> 2);
1559     mask |= 1 << ((mmTPC4_QM_CQ_CTL_STS & 0x7F) >> 2);
1560     mask |= 1 << ((mmTPC4_QM_CQ_STS0 & 0x7F) >> 2);
1561     mask |= 1 << ((mmTPC4_QM_CQ_STS1 & 0x7F) >> 2);
1562     mask |= 1 << ((mmTPC4_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1563     mask |= 1 << ((mmTPC4_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1564     mask |= 1 << ((mmTPC4_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1565     mask |= 1 << ((mmTPC4_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1566 
1567     WREG32(pb_addr + word_offset, ~mask);
1568 
1569     pb_addr = (mmTPC4_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
1570     word_offset = ((mmTPC4_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
1571     mask = 1 << ((mmTPC4_QM_CQ_IFIFO_CNT & 0x7F) >> 2);
1572     mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
1573     mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
1574     mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
1575     mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
1576     mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
1577     mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
1578     mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
1579     mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
1580     mask |= 1 << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
1581     mask |= 1 << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
1582     mask |= 1 << ((mmTPC4_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
1583     mask |= 1 << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
1584     mask |= 1 << ((mmTPC4_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
1585     mask |= 1 << ((mmTPC4_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
1586 
1587     WREG32(pb_addr + word_offset, ~mask);
1588 
1589     pb_addr = (mmTPC4_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
1590     word_offset = ((mmTPC4_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
1591     mask = 1 << ((mmTPC4_CMDQ_GLBL_CFG0 & 0x7F) >> 2);
1592     mask |= 1 << ((mmTPC4_CMDQ_GLBL_CFG1 & 0x7F) >> 2);
1593     mask |= 1 << ((mmTPC4_CMDQ_GLBL_PROT & 0x7F) >> 2);
1594     mask |= 1 << ((mmTPC4_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2);
1595     mask |= 1 << ((mmTPC4_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
1596     mask |= 1 << ((mmTPC4_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
1597     mask |= 1 << ((mmTPC4_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2);
1598     mask |= 1 << ((mmTPC4_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2);
1599     mask |= 1 << ((mmTPC4_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
1600     mask |= 1 << ((mmTPC4_CMDQ_GLBL_STS0 & 0x7F) >> 2);
1601     mask |= 1 << ((mmTPC4_CMDQ_GLBL_STS1 & 0x7F) >> 2);
1602 
1603     WREG32(pb_addr + word_offset, ~mask);
1604 
1605     pb_addr = (mmTPC4_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
1606     word_offset = ((mmTPC4_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
1607     mask = 1 << ((mmTPC4_CMDQ_CQ_CFG0 & 0x7F) >> 2);
1608     mask |= 1 << ((mmTPC4_CMDQ_CQ_CFG1 & 0x7F) >> 2);
1609     mask |= 1 << ((mmTPC4_CMDQ_CQ_ARUSER & 0x7F) >> 2);
1610     mask |= 1 << ((mmTPC4_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2);
1611     mask |= 1 << ((mmTPC4_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2);
1612     mask |= 1 << ((mmTPC4_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2);
1613     mask |= 1 << ((mmTPC4_CMDQ_CQ_CTL_STS & 0x7F) >> 2);
1614     mask |= 1 << ((mmTPC4_CMDQ_CQ_STS0 & 0x7F) >> 2);
1615     mask |= 1 << ((mmTPC4_CMDQ_CQ_STS1 & 0x7F) >> 2);
1616     mask |= 1 << ((mmTPC4_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1617     mask |= 1 << ((mmTPC4_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1618     mask |= 1 << ((mmTPC4_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1619     mask |= 1 << ((mmTPC4_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1620 
1621     WREG32(pb_addr + word_offset, ~mask);
1622 
1623     pb_addr = (mmTPC4_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
1624     word_offset = ((mmTPC4_CMDQ_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
1625     mask = 1 << ((mmTPC4_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2);
1626     mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
1627     mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
1628     mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
1629     mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
1630     mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
1631     mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
1632     mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
1633     mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
1634     mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
1635     mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
1636     mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
1637     mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
1638     mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
1639     mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
1640     mask |= 1 << ((mmTPC4_CMDQ_CP_STS & 0x7F) >> 2);
1641     mask |= 1 << ((mmTPC4_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2);
1642 
1643     WREG32(pb_addr + word_offset, ~mask);
1644 
1645     pb_addr = (mmTPC4_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS;
1646     word_offset = ((mmTPC4_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7)
1647             << 2;
1648     mask = 1 << ((mmTPC4_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2);
1649     mask |= 1 << ((mmTPC4_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2);
1650     mask |= 1 << ((mmTPC4_CMDQ_CP_DBG_0 & 0x7F) >> 2);
1651     mask |= 1 << ((mmTPC4_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2);
1652     mask |= 1 << ((mmTPC4_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2);
1653 
1654     WREG32(pb_addr + word_offset, ~mask);
1655 
1656     goya_pb_set_block(hdev, mmTPC5_RTR_BASE);
1657     goya_pb_set_block(hdev, mmTPC5_RD_REGULATOR_BASE);
1658     goya_pb_set_block(hdev, mmTPC5_WR_REGULATOR_BASE);
1659 
1660     pb_addr = (mmTPC5_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS;
1661     word_offset = ((mmTPC5_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2;
1662 
1663     mask = 1 << ((mmTPC5_CFG_SEMAPHORE & 0x7F) >> 2);
1664     mask |= 1 << ((mmTPC5_CFG_VFLAGS & 0x7F) >> 2);
1665     mask |= 1 << ((mmTPC5_CFG_SFLAGS & 0x7F) >> 2);
1666     mask |= 1 << ((mmTPC5_CFG_STATUS & 0x7F) >> 2);
1667 
1668     WREG32(pb_addr + word_offset, ~mask);
1669 
1670     pb_addr = (mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS;
1671     word_offset = ((mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH &
1672             PROT_BITS_OFFS) >> 7) << 2;
1673     mask = 1 << ((mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2);
1674     mask |= 1 << ((mmTPC5_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
1675     mask |= 1 << ((mmTPC5_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
1676     mask |= 1 << ((mmTPC5_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
1677     mask |= 1 << ((mmTPC5_CFG_TPC_STALL & 0x7F) >> 2);
1678     mask |= 1 << ((mmTPC5_CFG_MSS_CONFIG & 0x7F) >> 2);
1679     mask |= 1 << ((mmTPC5_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
1680     mask |= 1 << ((mmTPC5_CFG_TPC_INTR_MASK & 0x7F) >> 2);
1681 
1682     WREG32(pb_addr + word_offset, ~mask);
1683 
1684     pb_addr = (mmTPC5_CFG_ARUSER & ~0xFFF) + PROT_BITS_OFFS;
1685     word_offset = ((mmTPC5_CFG_ARUSER & PROT_BITS_OFFS) >> 7) << 2;
1686     mask = 1 << ((mmTPC5_CFG_ARUSER & 0x7F) >> 2);
1687     mask |= 1 << ((mmTPC5_CFG_AWUSER & 0x7F) >> 2);
1688 
1689     WREG32(pb_addr + word_offset, ~mask);
1690 
1691     pb_addr = (mmTPC5_CFG_FUNC_MBIST_CNTRL & ~0xFFF) + PROT_BITS_OFFS;
1692     word_offset = ((mmTPC5_CFG_FUNC_MBIST_CNTRL &
1693             PROT_BITS_OFFS) >> 7) << 2;
1694     mask = 1 << ((mmTPC5_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2);
1695     mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_PAT & 0x7F) >> 2);
1696     mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2);
1697     mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2);
1698     mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2);
1699     mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2);
1700     mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2);
1701     mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2);
1702     mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2);
1703     mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2);
1704     mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2);
1705     mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2);
1706 
1707     WREG32(pb_addr + word_offset, ~mask);
1708 
1709     pb_addr = (mmTPC5_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
1710     word_offset = ((mmTPC5_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
1711     mask = 1 << ((mmTPC5_QM_GLBL_CFG0 & 0x7F) >> 2);
1712     mask |= 1 << ((mmTPC5_QM_GLBL_CFG1 & 0x7F) >> 2);
1713     mask |= 1 << ((mmTPC5_QM_GLBL_PROT & 0x7F) >> 2);
1714     mask |= 1 << ((mmTPC5_QM_GLBL_ERR_CFG & 0x7F) >> 2);
1715     mask |= 1 << ((mmTPC5_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
1716     mask |= 1 << ((mmTPC5_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
1717     mask |= 1 << ((mmTPC5_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
1718     mask |= 1 << ((mmTPC5_QM_GLBL_SECURE_PROPS & 0x7F) >> 2);
1719     mask |= 1 << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
1720     mask |= 1 << ((mmTPC5_QM_GLBL_STS0 & 0x7F) >> 2);
1721     mask |= 1 << ((mmTPC5_QM_GLBL_STS1 & 0x7F) >> 2);
1722     mask |= 1 << ((mmTPC5_QM_PQ_BASE_LO & 0x7F) >> 2);
1723     mask |= 1 << ((mmTPC5_QM_PQ_BASE_HI & 0x7F) >> 2);
1724     mask |= 1 << ((mmTPC5_QM_PQ_SIZE & 0x7F) >> 2);
1725     mask |= 1 << ((mmTPC5_QM_PQ_PI & 0x7F) >> 2);
1726     mask |= 1 << ((mmTPC5_QM_PQ_CI & 0x7F) >> 2);
1727     mask |= 1 << ((mmTPC5_QM_PQ_CFG0 & 0x7F) >> 2);
1728     mask |= 1 << ((mmTPC5_QM_PQ_CFG1 & 0x7F) >> 2);
1729     mask |= 1 << ((mmTPC5_QM_PQ_ARUSER & 0x7F) >> 2);
1730 
1731     WREG32(pb_addr + word_offset, ~mask);
1732 
1733     pb_addr = (mmTPC5_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS;
1734     word_offset = ((mmTPC5_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2;
1735     mask = 1 << ((mmTPC5_QM_PQ_PUSH0 & 0x7F) >> 2);
1736     mask |= 1 << ((mmTPC5_QM_PQ_PUSH1 & 0x7F) >> 2);
1737     mask |= 1 << ((mmTPC5_QM_PQ_PUSH2 & 0x7F) >> 2);
1738     mask |= 1 << ((mmTPC5_QM_PQ_PUSH3 & 0x7F) >> 2);
1739     mask |= 1 << ((mmTPC5_QM_PQ_STS0 & 0x7F) >> 2);
1740     mask |= 1 << ((mmTPC5_QM_PQ_STS1 & 0x7F) >> 2);
1741     mask |= 1 << ((mmTPC5_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1742     mask |= 1 << ((mmTPC5_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1743     mask |= 1 << ((mmTPC5_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1744     mask |= 1 << ((mmTPC5_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1745     mask |= 1 << ((mmTPC5_QM_CQ_CFG0 & 0x7F) >> 2);
1746     mask |= 1 << ((mmTPC5_QM_CQ_CFG1 & 0x7F) >> 2);
1747     mask |= 1 << ((mmTPC5_QM_CQ_ARUSER & 0x7F) >> 2);
1748     mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO & 0x7F) >> 2);
1749     mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI & 0x7F) >> 2);
1750     mask |= 1 << ((mmTPC5_QM_CQ_TSIZE & 0x7F) >> 2);
1751     mask |= 1 << ((mmTPC5_QM_CQ_CTL & 0x7F) >> 2);
1752     mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_STS & 0x7F) >> 2);
1753     mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_STS & 0x7F) >> 2);
1754     mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_STS & 0x7F) >> 2);
1755     mask |= 1 << ((mmTPC5_QM_CQ_CTL_STS & 0x7F) >> 2);
1756     mask |= 1 << ((mmTPC5_QM_CQ_STS0 & 0x7F) >> 2);
1757     mask |= 1 << ((mmTPC5_QM_CQ_STS1 & 0x7F) >> 2);
1758     mask |= 1 << ((mmTPC5_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1759     mask |= 1 << ((mmTPC5_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1760     mask |= 1 << ((mmTPC5_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1761     mask |= 1 << ((mmTPC5_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1762 
1763     WREG32(pb_addr + word_offset, ~mask);
1764 
1765     pb_addr = (mmTPC5_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
1766     word_offset = ((mmTPC5_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
1767     mask = 1 << ((mmTPC5_QM_CQ_IFIFO_CNT & 0x7F) >> 2);
1768     mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
1769     mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
1770     mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
1771     mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
1772     mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
1773     mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
1774     mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
1775     mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
1776     mask |= 1 << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
1777     mask |= 1 << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
1778     mask |= 1 << ((mmTPC5_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
1779     mask |= 1 << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
1780     mask |= 1 << ((mmTPC5_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
1781     mask |= 1 << ((mmTPC5_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
1782 
1783     WREG32(pb_addr + word_offset, ~mask);
1784 
1785     pb_addr = (mmTPC5_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
1786     word_offset = ((mmTPC5_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
1787     mask = 1 << ((mmTPC5_CMDQ_GLBL_CFG0 & 0x7F) >> 2);
1788     mask |= 1 << ((mmTPC5_CMDQ_GLBL_CFG1 & 0x7F) >> 2);
1789     mask |= 1 << ((mmTPC5_CMDQ_GLBL_PROT & 0x7F) >> 2);
1790     mask |= 1 << ((mmTPC5_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2);
1791     mask |= 1 << ((mmTPC5_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
1792     mask |= 1 << ((mmTPC5_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
1793     mask |= 1 << ((mmTPC5_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2);
1794     mask |= 1 << ((mmTPC5_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2);
1795     mask |= 1 << ((mmTPC5_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
1796     mask |= 1 << ((mmTPC5_CMDQ_GLBL_STS0 & 0x7F) >> 2);
1797     mask |= 1 << ((mmTPC5_CMDQ_GLBL_STS1 & 0x7F) >> 2);
1798 
1799     WREG32(pb_addr + word_offset, ~mask);
1800 
1801     pb_addr = (mmTPC5_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
1802     word_offset = ((mmTPC5_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
1803     mask = 1 << ((mmTPC5_CMDQ_CQ_CFG0 & 0x7F) >> 2);
1804     mask |= 1 << ((mmTPC5_CMDQ_CQ_CFG1 & 0x7F) >> 2);
1805     mask |= 1 << ((mmTPC5_CMDQ_CQ_ARUSER & 0x7F) >> 2);
1806     mask |= 1 << ((mmTPC5_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2);
1807     mask |= 1 << ((mmTPC5_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2);
1808     mask |= 1 << ((mmTPC5_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2);
1809     mask |= 1 << ((mmTPC5_CMDQ_CQ_CTL_STS & 0x7F) >> 2);
1810     mask |= 1 << ((mmTPC5_CMDQ_CQ_STS0 & 0x7F) >> 2);
1811     mask |= 1 << ((mmTPC5_CMDQ_CQ_STS1 & 0x7F) >> 2);
1812     mask |= 1 << ((mmTPC5_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1813     mask |= 1 << ((mmTPC5_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1814     mask |= 1 << ((mmTPC5_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1815     mask |= 1 << ((mmTPC5_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1816 
1817     WREG32(pb_addr + word_offset, ~mask);
1818 
1819     pb_addr = (mmTPC5_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
1820     word_offset = ((mmTPC5_CMDQ_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
1821     mask = 1 << ((mmTPC5_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2);
1822     mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
1823     mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
1824     mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
1825     mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
1826     mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
1827     mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
1828     mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
1829     mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
1830     mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
1831     mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
1832     mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
1833     mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
1834     mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
1835     mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
1836     mask |= 1 << ((mmTPC5_CMDQ_CP_STS & 0x7F) >> 2);
1837     mask |= 1 << ((mmTPC5_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2);
1838 
1839     WREG32(pb_addr + word_offset, ~mask);
1840 
1841     pb_addr = (mmTPC5_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS;
1842     word_offset = ((mmTPC5_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7)
1843             << 2;
1844     mask = 1 << ((mmTPC5_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2);
1845     mask |= 1 << ((mmTPC5_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2);
1846     mask |= 1 << ((mmTPC5_CMDQ_CP_DBG_0 & 0x7F) >> 2);
1847     mask |= 1 << ((mmTPC5_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2);
1848     mask |= 1 << ((mmTPC5_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2);
1849 
1850     WREG32(pb_addr + word_offset, ~mask);
1851 
1852     goya_pb_set_block(hdev, mmTPC6_RTR_BASE);
1853     goya_pb_set_block(hdev, mmTPC6_RD_REGULATOR_BASE);
1854     goya_pb_set_block(hdev, mmTPC6_WR_REGULATOR_BASE);
1855 
1856     pb_addr = (mmTPC6_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS;
1857     word_offset = ((mmTPC6_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2;
1858 
1859     mask = 1 << ((mmTPC6_CFG_SEMAPHORE & 0x7F) >> 2);
1860     mask |= 1 << ((mmTPC6_CFG_VFLAGS & 0x7F) >> 2);
1861     mask |= 1 << ((mmTPC6_CFG_SFLAGS & 0x7F) >> 2);
1862     mask |= 1 << ((mmTPC6_CFG_STATUS & 0x7F) >> 2);
1863 
1864     WREG32(pb_addr + word_offset, ~mask);
1865 
1866     pb_addr = (mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS;
1867     word_offset = ((mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH &
1868             PROT_BITS_OFFS) >> 7) << 2;
1869     mask = 1 << ((mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2);
1870     mask |= 1 << ((mmTPC6_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
1871     mask |= 1 << ((mmTPC6_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
1872     mask |= 1 << ((mmTPC6_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
1873     mask |= 1 << ((mmTPC6_CFG_TPC_STALL & 0x7F) >> 2);
1874     mask |= 1 << ((mmTPC6_CFG_MSS_CONFIG & 0x7F) >> 2);
1875     mask |= 1 << ((mmTPC6_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
1876     mask |= 1 << ((mmTPC6_CFG_TPC_INTR_MASK & 0x7F) >> 2);
1877 
1878     WREG32(pb_addr + word_offset, ~mask);
1879 
1880     pb_addr = (mmTPC6_CFG_ARUSER & ~0xFFF) + PROT_BITS_OFFS;
1881     word_offset = ((mmTPC6_CFG_ARUSER & PROT_BITS_OFFS) >> 7) << 2;
1882     mask = 1 << ((mmTPC6_CFG_ARUSER & 0x7F) >> 2);
1883     mask |= 1 << ((mmTPC6_CFG_AWUSER & 0x7F) >> 2);
1884 
1885     WREG32(pb_addr + word_offset, ~mask);
1886 
1887     pb_addr = (mmTPC6_CFG_FUNC_MBIST_CNTRL & ~0xFFF) + PROT_BITS_OFFS;
1888     word_offset = ((mmTPC6_CFG_FUNC_MBIST_CNTRL &
1889             PROT_BITS_OFFS) >> 7) << 2;
1890     mask = 1 << ((mmTPC6_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2);
1891     mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_PAT & 0x7F) >> 2);
1892     mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2);
1893     mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2);
1894     mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2);
1895     mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2);
1896     mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2);
1897     mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2);
1898     mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2);
1899     mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2);
1900     mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2);
1901     mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2);
1902 
1903     WREG32(pb_addr + word_offset, ~mask);
1904 
1905     pb_addr = (mmTPC6_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
1906     word_offset = ((mmTPC6_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
1907     mask = 1 << ((mmTPC6_QM_GLBL_CFG0 & 0x7F) >> 2);
1908     mask |= 1 << ((mmTPC6_QM_GLBL_CFG1 & 0x7F) >> 2);
1909     mask |= 1 << ((mmTPC6_QM_GLBL_PROT & 0x7F) >> 2);
1910     mask |= 1 << ((mmTPC6_QM_GLBL_ERR_CFG & 0x7F) >> 2);
1911     mask |= 1 << ((mmTPC6_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
1912     mask |= 1 << ((mmTPC6_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
1913     mask |= 1 << ((mmTPC6_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
1914     mask |= 1 << ((mmTPC6_QM_GLBL_SECURE_PROPS & 0x7F) >> 2);
1915     mask |= 1 << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
1916     mask |= 1 << ((mmTPC6_QM_GLBL_STS0 & 0x7F) >> 2);
1917     mask |= 1 << ((mmTPC6_QM_GLBL_STS1 & 0x7F) >> 2);
1918     mask |= 1 << ((mmTPC6_QM_PQ_BASE_LO & 0x7F) >> 2);
1919     mask |= 1 << ((mmTPC6_QM_PQ_BASE_HI & 0x7F) >> 2);
1920     mask |= 1 << ((mmTPC6_QM_PQ_SIZE & 0x7F) >> 2);
1921     mask |= 1 << ((mmTPC6_QM_PQ_PI & 0x7F) >> 2);
1922     mask |= 1 << ((mmTPC6_QM_PQ_CI & 0x7F) >> 2);
1923     mask |= 1 << ((mmTPC6_QM_PQ_CFG0 & 0x7F) >> 2);
1924     mask |= 1 << ((mmTPC6_QM_PQ_CFG1 & 0x7F) >> 2);
1925     mask |= 1 << ((mmTPC6_QM_PQ_ARUSER & 0x7F) >> 2);
1926 
1927     WREG32(pb_addr + word_offset, ~mask);
1928 
1929     pb_addr = (mmTPC6_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS;
1930     word_offset = ((mmTPC6_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2;
1931     mask = 1 << ((mmTPC6_QM_PQ_PUSH0 & 0x7F) >> 2);
1932     mask |= 1 << ((mmTPC6_QM_PQ_PUSH1 & 0x7F) >> 2);
1933     mask |= 1 << ((mmTPC6_QM_PQ_PUSH2 & 0x7F) >> 2);
1934     mask |= 1 << ((mmTPC6_QM_PQ_PUSH3 & 0x7F) >> 2);
1935     mask |= 1 << ((mmTPC6_QM_PQ_STS0 & 0x7F) >> 2);
1936     mask |= 1 << ((mmTPC6_QM_PQ_STS1 & 0x7F) >> 2);
1937     mask |= 1 << ((mmTPC6_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1938     mask |= 1 << ((mmTPC6_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1939     mask |= 1 << ((mmTPC6_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1940     mask |= 1 << ((mmTPC6_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1941     mask |= 1 << ((mmTPC6_QM_CQ_CFG0 & 0x7F) >> 2);
1942     mask |= 1 << ((mmTPC6_QM_CQ_CFG1 & 0x7F) >> 2);
1943     mask |= 1 << ((mmTPC6_QM_CQ_ARUSER & 0x7F) >> 2);
1944     mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO & 0x7F) >> 2);
1945     mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI & 0x7F) >> 2);
1946     mask |= 1 << ((mmTPC6_QM_CQ_TSIZE & 0x7F) >> 2);
1947     mask |= 1 << ((mmTPC6_QM_CQ_CTL & 0x7F) >> 2);
1948     mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_STS & 0x7F) >> 2);
1949     mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_STS & 0x7F) >> 2);
1950     mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_STS & 0x7F) >> 2);
1951     mask |= 1 << ((mmTPC6_QM_CQ_CTL_STS & 0x7F) >> 2);
1952     mask |= 1 << ((mmTPC6_QM_CQ_STS0 & 0x7F) >> 2);
1953     mask |= 1 << ((mmTPC6_QM_CQ_STS1 & 0x7F) >> 2);
1954     mask |= 1 << ((mmTPC6_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
1955     mask |= 1 << ((mmTPC6_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
1956     mask |= 1 << ((mmTPC6_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
1957     mask |= 1 << ((mmTPC6_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
1958 
1959     WREG32(pb_addr + word_offset, ~mask);
1960 
1961     pb_addr = (mmTPC6_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
1962     word_offset = ((mmTPC6_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
1963     mask = 1 << ((mmTPC6_QM_CQ_IFIFO_CNT & 0x7F) >> 2);
1964     mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
1965     mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
1966     mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
1967     mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
1968     mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
1969     mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
1970     mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
1971     mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
1972     mask |= 1 << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
1973     mask |= 1 << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
1974     mask |= 1 << ((mmTPC6_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
1975     mask |= 1 << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
1976     mask |= 1 << ((mmTPC6_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
1977     mask |= 1 << ((mmTPC6_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
1978 
1979     WREG32(pb_addr + word_offset, ~mask);
1980 
1981     pb_addr = (mmTPC6_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
1982     word_offset = ((mmTPC6_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
1983     mask = 1 << ((mmTPC6_CMDQ_GLBL_CFG0 & 0x7F) >> 2);
1984     mask |= 1 << ((mmTPC6_CMDQ_GLBL_CFG1 & 0x7F) >> 2);
1985     mask |= 1 << ((mmTPC6_CMDQ_GLBL_PROT & 0x7F) >> 2);
1986     mask |= 1 << ((mmTPC6_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2);
1987     mask |= 1 << ((mmTPC6_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
1988     mask |= 1 << ((mmTPC6_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
1989     mask |= 1 << ((mmTPC6_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2);
1990     mask |= 1 << ((mmTPC6_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2);
1991     mask |= 1 << ((mmTPC6_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
1992     mask |= 1 << ((mmTPC6_CMDQ_GLBL_STS0 & 0x7F) >> 2);
1993     mask |= 1 << ((mmTPC6_CMDQ_GLBL_STS1 & 0x7F) >> 2);
1994 
1995     WREG32(pb_addr + word_offset, ~mask);
1996 
1997     pb_addr = (mmTPC6_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
1998     word_offset = ((mmTPC6_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
1999     mask = 1 << ((mmTPC6_CMDQ_CQ_CFG0 & 0x7F) >> 2);
2000     mask |= 1 << ((mmTPC6_CMDQ_CQ_CFG1 & 0x7F) >> 2);
2001     mask |= 1 << ((mmTPC6_CMDQ_CQ_ARUSER & 0x7F) >> 2);
2002     mask |= 1 << ((mmTPC6_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2);
2003     mask |= 1 << ((mmTPC6_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2);
2004     mask |= 1 << ((mmTPC6_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2);
2005     mask |= 1 << ((mmTPC6_CMDQ_CQ_CTL_STS & 0x7F) >> 2);
2006     mask |= 1 << ((mmTPC6_CMDQ_CQ_STS0 & 0x7F) >> 2);
2007     mask |= 1 << ((mmTPC6_CMDQ_CQ_STS1 & 0x7F) >> 2);
2008     mask |= 1 << ((mmTPC6_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
2009     mask |= 1 << ((mmTPC6_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
2010     mask |= 1 << ((mmTPC6_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
2011     mask |= 1 << ((mmTPC6_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
2012 
2013     WREG32(pb_addr + word_offset, ~mask);
2014 
2015     pb_addr = (mmTPC6_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
2016     word_offset = ((mmTPC6_CMDQ_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
2017     mask = 1 << ((mmTPC6_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2);
2018     mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
2019     mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
2020     mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
2021     mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
2022     mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
2023     mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
2024     mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
2025     mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
2026     mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
2027     mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
2028     mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
2029     mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
2030     mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
2031     mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
2032     mask |= 1 << ((mmTPC6_CMDQ_CP_STS & 0x7F) >> 2);
2033     mask |= 1 << ((mmTPC6_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2);
2034 
2035     WREG32(pb_addr + word_offset, ~mask);
2036 
2037     pb_addr = (mmTPC6_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS;
2038     word_offset = ((mmTPC6_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7)
2039             << 2;
2040     mask = 1 << ((mmTPC6_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2);
2041     mask |= 1 << ((mmTPC6_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2);
2042     mask |= 1 << ((mmTPC6_CMDQ_CP_DBG_0 & 0x7F) >> 2);
2043     mask |= 1 << ((mmTPC6_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2);
2044     mask |= 1 << ((mmTPC6_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2);
2045 
2046     WREG32(pb_addr + word_offset, ~mask);
2047 
2048     goya_pb_set_block(hdev, mmTPC7_NRTR_BASE);
2049     goya_pb_set_block(hdev, mmTPC7_RD_REGULATOR_BASE);
2050     goya_pb_set_block(hdev, mmTPC7_WR_REGULATOR_BASE);
2051 
2052     pb_addr = (mmTPC7_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS;
2053     word_offset = ((mmTPC7_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2;
2054 
2055     mask = 1 << ((mmTPC7_CFG_SEMAPHORE & 0x7F) >> 2);
2056     mask |= 1 << ((mmTPC7_CFG_VFLAGS & 0x7F) >> 2);
2057     mask |= 1 << ((mmTPC7_CFG_SFLAGS & 0x7F) >> 2);
2058     mask |= 1 << ((mmTPC7_CFG_STATUS & 0x7F) >> 2);
2059 
2060     WREG32(pb_addr + word_offset, ~mask);
2061 
2062     pb_addr = (mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS;
2063     word_offset = ((mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH &
2064             PROT_BITS_OFFS) >> 7) << 2;
2065     mask = 1 << ((mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2);
2066     mask |= 1 << ((mmTPC7_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2);
2067     mask |= 1 << ((mmTPC7_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
2068     mask |= 1 << ((mmTPC7_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
2069     mask |= 1 << ((mmTPC7_CFG_TPC_STALL & 0x7F) >> 2);
2070     mask |= 1 << ((mmTPC7_CFG_MSS_CONFIG & 0x7F) >> 2);
2071     mask |= 1 << ((mmTPC7_CFG_TPC_INTR_CAUSE & 0x7F) >> 2);
2072     mask |= 1 << ((mmTPC7_CFG_TPC_INTR_MASK & 0x7F) >> 2);
2073 
2074     WREG32(pb_addr + word_offset, ~mask);
2075 
2076     pb_addr = (mmTPC7_CFG_ARUSER & ~0xFFF) + PROT_BITS_OFFS;
2077     word_offset = ((mmTPC7_CFG_ARUSER & PROT_BITS_OFFS) >> 7) << 2;
2078     mask = 1 << ((mmTPC7_CFG_ARUSER & 0x7F) >> 2);
2079     mask |= 1 << ((mmTPC7_CFG_AWUSER & 0x7F) >> 2);
2080 
2081     WREG32(pb_addr + word_offset, ~mask);
2082 
2083     pb_addr = (mmTPC7_CFG_FUNC_MBIST_CNTRL & ~0xFFF) + PROT_BITS_OFFS;
2084     word_offset = ((mmTPC7_CFG_FUNC_MBIST_CNTRL &
2085             PROT_BITS_OFFS) >> 7) << 2;
2086     mask = 1 << ((mmTPC7_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2);
2087     mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_PAT & 0x7F) >> 2);
2088     mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2);
2089     mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2);
2090     mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2);
2091     mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2);
2092     mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2);
2093     mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2);
2094     mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2);
2095     mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2);
2096     mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2);
2097     mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2);
2098 
2099     WREG32(pb_addr + word_offset, ~mask);
2100 
2101     pb_addr = (mmTPC7_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
2102     word_offset = ((mmTPC7_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
2103     mask = 1 << ((mmTPC7_QM_GLBL_CFG0 & 0x7F) >> 2);
2104     mask |= 1 << ((mmTPC7_QM_GLBL_CFG1 & 0x7F) >> 2);
2105     mask |= 1 << ((mmTPC7_QM_GLBL_PROT & 0x7F) >> 2);
2106     mask |= 1 << ((mmTPC7_QM_GLBL_ERR_CFG & 0x7F) >> 2);
2107     mask |= 1 << ((mmTPC7_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
2108     mask |= 1 << ((mmTPC7_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
2109     mask |= 1 << ((mmTPC7_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
2110     mask |= 1 << ((mmTPC7_QM_GLBL_SECURE_PROPS & 0x7F) >> 2);
2111     mask |= 1 << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
2112     mask |= 1 << ((mmTPC7_QM_GLBL_STS0 & 0x7F) >> 2);
2113     mask |= 1 << ((mmTPC7_QM_GLBL_STS1 & 0x7F) >> 2);
2114     mask |= 1 << ((mmTPC7_QM_PQ_BASE_LO & 0x7F) >> 2);
2115     mask |= 1 << ((mmTPC7_QM_PQ_BASE_HI & 0x7F) >> 2);
2116     mask |= 1 << ((mmTPC7_QM_PQ_SIZE & 0x7F) >> 2);
2117     mask |= 1 << ((mmTPC7_QM_PQ_PI & 0x7F) >> 2);
2118     mask |= 1 << ((mmTPC7_QM_PQ_CI & 0x7F) >> 2);
2119     mask |= 1 << ((mmTPC7_QM_PQ_CFG0 & 0x7F) >> 2);
2120     mask |= 1 << ((mmTPC7_QM_PQ_CFG1 & 0x7F) >> 2);
2121     mask |= 1 << ((mmTPC7_QM_PQ_ARUSER & 0x7F) >> 2);
2122 
2123     WREG32(pb_addr + word_offset, ~mask);
2124 
2125     pb_addr = (mmTPC7_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS;
2126     word_offset = ((mmTPC7_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2;
2127     mask = 1 << ((mmTPC7_QM_PQ_PUSH0 & 0x7F) >> 2);
2128     mask |= 1 << ((mmTPC7_QM_PQ_PUSH1 & 0x7F) >> 2);
2129     mask |= 1 << ((mmTPC7_QM_PQ_PUSH2 & 0x7F) >> 2);
2130     mask |= 1 << ((mmTPC7_QM_PQ_PUSH3 & 0x7F) >> 2);
2131     mask |= 1 << ((mmTPC7_QM_PQ_STS0 & 0x7F) >> 2);
2132     mask |= 1 << ((mmTPC7_QM_PQ_STS1 & 0x7F) >> 2);
2133     mask |= 1 << ((mmTPC7_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
2134     mask |= 1 << ((mmTPC7_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
2135     mask |= 1 << ((mmTPC7_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
2136     mask |= 1 << ((mmTPC7_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
2137     mask |= 1 << ((mmTPC7_QM_CQ_CFG0 & 0x7F) >> 2);
2138     mask |= 1 << ((mmTPC7_QM_CQ_CFG1 & 0x7F) >> 2);
2139     mask |= 1 << ((mmTPC7_QM_CQ_ARUSER & 0x7F) >> 2);
2140     mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO & 0x7F) >> 2);
2141     mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI & 0x7F) >> 2);
2142     mask |= 1 << ((mmTPC7_QM_CQ_TSIZE & 0x7F) >> 2);
2143     mask |= 1 << ((mmTPC7_QM_CQ_CTL & 0x7F) >> 2);
2144     mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_STS & 0x7F) >> 2);
2145     mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_STS & 0x7F) >> 2);
2146     mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_STS & 0x7F) >> 2);
2147     mask |= 1 << ((mmTPC7_QM_CQ_CTL_STS & 0x7F) >> 2);
2148     mask |= 1 << ((mmTPC7_QM_CQ_STS0 & 0x7F) >> 2);
2149     mask |= 1 << ((mmTPC7_QM_CQ_STS1 & 0x7F) >> 2);
2150     mask |= 1 << ((mmTPC7_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
2151     mask |= 1 << ((mmTPC7_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
2152     mask |= 1 << ((mmTPC7_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
2153     mask |= 1 << ((mmTPC7_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
2154 
2155     WREG32(pb_addr + word_offset, ~mask);
2156 
2157     pb_addr = (mmTPC7_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
2158     word_offset = ((mmTPC7_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
2159     mask = 1 << ((mmTPC7_QM_CQ_IFIFO_CNT & 0x7F) >> 2);
2160     mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
2161     mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
2162     mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
2163     mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
2164     mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
2165     mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
2166     mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
2167     mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
2168     mask |= 1 << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
2169     mask |= 1 << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
2170     mask |= 1 << ((mmTPC7_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
2171     mask |= 1 << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
2172     mask |= 1 << ((mmTPC7_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
2173     mask |= 1 << ((mmTPC7_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
2174 
2175     WREG32(pb_addr + word_offset, ~mask);
2176 
2177     pb_addr = (mmTPC7_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
2178     word_offset = ((mmTPC7_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
2179     mask = 1 << ((mmTPC7_CMDQ_GLBL_CFG0 & 0x7F) >> 2);
2180     mask |= 1 << ((mmTPC7_CMDQ_GLBL_CFG1 & 0x7F) >> 2);
2181     mask |= 1 << ((mmTPC7_CMDQ_GLBL_PROT & 0x7F) >> 2);
2182     mask |= 1 << ((mmTPC7_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2);
2183     mask |= 1 << ((mmTPC7_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
2184     mask |= 1 << ((mmTPC7_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
2185     mask |= 1 << ((mmTPC7_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2);
2186     mask |= 1 << ((mmTPC7_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2);
2187     mask |= 1 << ((mmTPC7_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
2188     mask |= 1 << ((mmTPC7_CMDQ_GLBL_STS0 & 0x7F) >> 2);
2189     mask |= 1 << ((mmTPC7_CMDQ_GLBL_STS1 & 0x7F) >> 2);
2190 
2191     WREG32(pb_addr + word_offset, ~mask);
2192 
2193     pb_addr = (mmTPC7_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
2194     word_offset = ((mmTPC7_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
2195     mask = 1 << ((mmTPC7_CMDQ_CQ_CFG0 & 0x7F) >> 2);
2196     mask |= 1 << ((mmTPC7_CMDQ_CQ_CFG1 & 0x7F) >> 2);
2197     mask |= 1 << ((mmTPC7_CMDQ_CQ_ARUSER & 0x7F) >> 2);
2198     mask |= 1 << ((mmTPC7_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2);
2199     mask |= 1 << ((mmTPC7_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2);
2200     mask |= 1 << ((mmTPC7_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2);
2201     mask |= 1 << ((mmTPC7_CMDQ_CQ_CTL_STS & 0x7F) >> 2);
2202     mask |= 1 << ((mmTPC7_CMDQ_CQ_STS0 & 0x7F) >> 2);
2203     mask |= 1 << ((mmTPC7_CMDQ_CQ_STS1 & 0x7F) >> 2);
2204     mask |= 1 << ((mmTPC7_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
2205     mask |= 1 << ((mmTPC7_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
2206     mask |= 1 << ((mmTPC7_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
2207     mask |= 1 << ((mmTPC7_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
2208 
2209     WREG32(pb_addr + word_offset, ~mask);
2210 
2211     pb_addr = (mmTPC7_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
2212     word_offset = ((mmTPC7_CMDQ_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
2213     mask = 1 << ((mmTPC7_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2);
2214     mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
2215     mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
2216     mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
2217     mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
2218     mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
2219     mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
2220     mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
2221     mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
2222     mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
2223     mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
2224     mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
2225     mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
2226     mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
2227     mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
2228     mask |= 1 << ((mmTPC7_CMDQ_CP_STS & 0x7F) >> 2);
2229     mask |= 1 << ((mmTPC7_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2);
2230 
2231     WREG32(pb_addr + word_offset, ~mask);
2232 
2233     pb_addr = (mmTPC7_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS;
2234     word_offset = ((mmTPC7_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7)
2235             << 2;
2236     mask = 1 << ((mmTPC7_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2);
2237     mask |= 1 << ((mmTPC7_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2);
2238     mask |= 1 << ((mmTPC7_CMDQ_CP_DBG_0 & 0x7F) >> 2);
2239     mask |= 1 << ((mmTPC7_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2);
2240     mask |= 1 << ((mmTPC7_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2);
2241 
2242     WREG32(pb_addr + word_offset, ~mask);
2243 }
2244 
2245 /*
2246  * goya_init_protection_bits - Initialize protection bits for specific registers
2247  *
2248  * @hdev: pointer to hl_device structure
2249  *
2250  * All protection bits are 1 by default, means not protected. Need to set to 0
2251  * each bit that belongs to a protected register.
2252  *
2253  */
2254 static void goya_init_protection_bits(struct hl_device *hdev)
2255 {
2256     /*
2257      * In each 4K block of registers, the last 128 bytes are protection
2258      * bits - total of 1024 bits, one for each register. Each bit is related
2259      * to a specific register, by the order of the registers.
2260      * So in order to calculate the bit that is related to a given register,
2261      * we need to calculate its word offset and then the exact bit inside
2262      * the word (which is 4 bytes).
2263      *
2264      * Register address:
2265      *
2266      * 31                 12 11           7   6             2  1      0
2267      * -----------------------------------------------------------------
2268      * |      Don't         |    word       |  bit location  |    0    |
2269      * |      care          |   offset      |  inside word   |         |
2270      * -----------------------------------------------------------------
2271      *
2272      * Bits 7-11 represents the word offset inside the 128 bytes.
2273      * Bits 2-6 represents the bit location inside the word.
2274      */
2275     u32 pb_addr, mask;
2276     u8 word_offset;
2277 
2278     goya_pb_set_block(hdev, mmPCI_NRTR_BASE);
2279     goya_pb_set_block(hdev, mmPCI_RD_REGULATOR_BASE);
2280     goya_pb_set_block(hdev, mmPCI_WR_REGULATOR_BASE);
2281 
2282     goya_pb_set_block(hdev, mmSRAM_Y0_X0_BANK_BASE);
2283     goya_pb_set_block(hdev, mmSRAM_Y0_X0_RTR_BASE);
2284     goya_pb_set_block(hdev, mmSRAM_Y0_X1_BANK_BASE);
2285     goya_pb_set_block(hdev, mmSRAM_Y0_X1_RTR_BASE);
2286     goya_pb_set_block(hdev, mmSRAM_Y0_X2_BANK_BASE);
2287     goya_pb_set_block(hdev, mmSRAM_Y0_X2_RTR_BASE);
2288     goya_pb_set_block(hdev, mmSRAM_Y0_X3_BANK_BASE);
2289     goya_pb_set_block(hdev, mmSRAM_Y0_X3_RTR_BASE);
2290     goya_pb_set_block(hdev, mmSRAM_Y0_X4_BANK_BASE);
2291     goya_pb_set_block(hdev, mmSRAM_Y0_X4_RTR_BASE);
2292 
2293     goya_pb_set_block(hdev, mmSRAM_Y1_X0_BANK_BASE);
2294     goya_pb_set_block(hdev, mmSRAM_Y1_X0_RTR_BASE);
2295     goya_pb_set_block(hdev, mmSRAM_Y1_X1_BANK_BASE);
2296     goya_pb_set_block(hdev, mmSRAM_Y1_X1_RTR_BASE);
2297     goya_pb_set_block(hdev, mmSRAM_Y1_X2_BANK_BASE);
2298     goya_pb_set_block(hdev, mmSRAM_Y1_X2_RTR_BASE);
2299     goya_pb_set_block(hdev, mmSRAM_Y1_X3_BANK_BASE);
2300     goya_pb_set_block(hdev, mmSRAM_Y1_X3_RTR_BASE);
2301     goya_pb_set_block(hdev, mmSRAM_Y1_X4_BANK_BASE);
2302     goya_pb_set_block(hdev, mmSRAM_Y1_X4_RTR_BASE);
2303 
2304     goya_pb_set_block(hdev, mmSRAM_Y2_X0_BANK_BASE);
2305     goya_pb_set_block(hdev, mmSRAM_Y2_X0_RTR_BASE);
2306     goya_pb_set_block(hdev, mmSRAM_Y2_X1_BANK_BASE);
2307     goya_pb_set_block(hdev, mmSRAM_Y2_X1_RTR_BASE);
2308     goya_pb_set_block(hdev, mmSRAM_Y2_X2_BANK_BASE);
2309     goya_pb_set_block(hdev, mmSRAM_Y2_X2_RTR_BASE);
2310     goya_pb_set_block(hdev, mmSRAM_Y2_X3_BANK_BASE);
2311     goya_pb_set_block(hdev, mmSRAM_Y2_X3_RTR_BASE);
2312     goya_pb_set_block(hdev, mmSRAM_Y2_X4_BANK_BASE);
2313     goya_pb_set_block(hdev, mmSRAM_Y2_X4_RTR_BASE);
2314 
2315     goya_pb_set_block(hdev, mmSRAM_Y3_X0_BANK_BASE);
2316     goya_pb_set_block(hdev, mmSRAM_Y3_X0_RTR_BASE);
2317     goya_pb_set_block(hdev, mmSRAM_Y3_X1_BANK_BASE);
2318     goya_pb_set_block(hdev, mmSRAM_Y3_X1_RTR_BASE);
2319     goya_pb_set_block(hdev, mmSRAM_Y3_X2_BANK_BASE);
2320     goya_pb_set_block(hdev, mmSRAM_Y3_X2_RTR_BASE);
2321     goya_pb_set_block(hdev, mmSRAM_Y3_X3_BANK_BASE);
2322     goya_pb_set_block(hdev, mmSRAM_Y3_X3_RTR_BASE);
2323     goya_pb_set_block(hdev, mmSRAM_Y3_X4_BANK_BASE);
2324     goya_pb_set_block(hdev, mmSRAM_Y3_X4_RTR_BASE);
2325 
2326     goya_pb_set_block(hdev, mmSRAM_Y4_X0_BANK_BASE);
2327     goya_pb_set_block(hdev, mmSRAM_Y4_X0_RTR_BASE);
2328     goya_pb_set_block(hdev, mmSRAM_Y4_X1_BANK_BASE);
2329     goya_pb_set_block(hdev, mmSRAM_Y4_X1_RTR_BASE);
2330     goya_pb_set_block(hdev, mmSRAM_Y4_X2_BANK_BASE);
2331     goya_pb_set_block(hdev, mmSRAM_Y4_X2_RTR_BASE);
2332     goya_pb_set_block(hdev, mmSRAM_Y4_X3_BANK_BASE);
2333     goya_pb_set_block(hdev, mmSRAM_Y4_X3_RTR_BASE);
2334     goya_pb_set_block(hdev, mmSRAM_Y4_X4_BANK_BASE);
2335     goya_pb_set_block(hdev, mmSRAM_Y4_X4_RTR_BASE);
2336 
2337     goya_pb_set_block(hdev, mmSRAM_Y5_X0_BANK_BASE);
2338     goya_pb_set_block(hdev, mmSRAM_Y5_X0_RTR_BASE);
2339     goya_pb_set_block(hdev, mmSRAM_Y5_X1_BANK_BASE);
2340     goya_pb_set_block(hdev, mmSRAM_Y5_X1_RTR_BASE);
2341     goya_pb_set_block(hdev, mmSRAM_Y5_X2_BANK_BASE);
2342     goya_pb_set_block(hdev, mmSRAM_Y5_X2_RTR_BASE);
2343     goya_pb_set_block(hdev, mmSRAM_Y5_X3_BANK_BASE);
2344     goya_pb_set_block(hdev, mmSRAM_Y5_X3_RTR_BASE);
2345     goya_pb_set_block(hdev, mmSRAM_Y5_X4_BANK_BASE);
2346     goya_pb_set_block(hdev, mmSRAM_Y5_X4_RTR_BASE);
2347 
2348     goya_pb_set_block(hdev, mmPCIE_WRAP_BASE);
2349     goya_pb_set_block(hdev, mmPCIE_CORE_BASE);
2350     goya_pb_set_block(hdev, mmPCIE_DB_CFG_BASE);
2351     goya_pb_set_block(hdev, mmPCIE_DB_CMD_BASE);
2352     goya_pb_set_block(hdev, mmPCIE_AUX_BASE);
2353     goya_pb_set_block(hdev, mmPCIE_DB_RSV_BASE);
2354     goya_pb_set_block(hdev, mmPCIE_PHY_BASE);
2355     goya_pb_set_block(hdev, mmTPC0_NRTR_BASE);
2356     goya_pb_set_block(hdev, mmTPC_PLL_BASE);
2357 
2358     pb_addr = (mmTPC_PLL_CLK_RLX_0 & ~0xFFF) + PROT_BITS_OFFS;
2359     word_offset = ((mmTPC_PLL_CLK_RLX_0 & PROT_BITS_OFFS) >> 7) << 2;
2360     mask = 1 << ((mmTPC_PLL_CLK_RLX_0 & 0x7C) >> 2);
2361 
2362     WREG32(pb_addr + word_offset, mask);
2363 
2364     goya_init_mme_protection_bits(hdev);
2365 
2366     goya_init_dma_protection_bits(hdev);
2367 
2368     goya_init_tpc_protection_bits(hdev);
2369 }
2370 
2371 /*
2372  * goya_init_security - Initialize security model
2373  *
2374  * @hdev: pointer to hl_device structure
2375  *
2376  * Initialize the security model of the device
2377  * That includes range registers and protection bit per register
2378  *
2379  */
2380 void goya_init_security(struct hl_device *hdev)
2381 {
2382     struct goya_device *goya = hdev->asic_specific;
2383 
2384     u32 dram_addr_lo = lower_32_bits(DRAM_PHYS_BASE);
2385     u32 dram_addr_hi = upper_32_bits(DRAM_PHYS_BASE);
2386 
2387     u32 lbw_rng0_base = 0xFC440000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2388     u32 lbw_rng0_mask = 0xFFFF0000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2389 
2390     u32 lbw_rng1_base = 0xFC480000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2391     u32 lbw_rng1_mask = 0xFFF80000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2392 
2393     u32 lbw_rng2_base = 0xFC600000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2394     u32 lbw_rng2_mask = 0xFFE00000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2395 
2396     u32 lbw_rng3_base = 0xFC800000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2397     u32 lbw_rng3_mask = 0xFFF00000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2398 
2399     u32 lbw_rng4_base = 0xFCC02000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2400     u32 lbw_rng4_mask = 0xFFFFF000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2401 
2402     u32 lbw_rng5_base = 0xFCC40000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2403     u32 lbw_rng5_mask = 0xFFFF8000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2404 
2405     u32 lbw_rng6_base = 0xFCC48000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2406     u32 lbw_rng6_mask = 0xFFFFF000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2407 
2408     u32 lbw_rng7_base = 0xFCC4A000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2409     u32 lbw_rng7_mask = 0xFFFFE000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2410 
2411     u32 lbw_rng8_base = 0xFCC4C000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2412     u32 lbw_rng8_mask = 0xFFFFC000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2413 
2414     u32 lbw_rng9_base = 0xFCC50000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2415     u32 lbw_rng9_mask = 0xFFFF0000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2416 
2417     u32 lbw_rng10_base = 0xFCC60000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2418     u32 lbw_rng10_mask = 0xFFFE0000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2419 
2420     u32 lbw_rng11_base = 0xFCE02000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2421     u32 lbw_rng11_mask = 0xFFFFE000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2422 
2423     u32 lbw_rng12_base = 0xFE484000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2424     u32 lbw_rng12_mask = 0xFFFFF000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2425 
2426     u32 lbw_rng13_base = 0xFEC43000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2427     u32 lbw_rng13_mask = 0xFFFFF000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
2428 
2429     WREG32(mmDMA_MACRO_LBW_RANGE_HIT_BLOCK, 0xFFFF);
2430     WREG32(mmDMA_MACRO_HBW_RANGE_HIT_BLOCK, 0xFF);
2431 
2432     if (!(goya->hw_cap_initialized & HW_CAP_MMU)) {
2433         WREG32(mmDMA_MACRO_HBW_RANGE_HIT_BLOCK, 0xFE);
2434 
2435         /* Protect HOST */
2436         WREG32(mmDMA_MACRO_HBW_RANGE_BASE_31_0_0, 0);
2437         WREG32(mmDMA_MACRO_HBW_RANGE_BASE_49_32_0, 0);
2438         WREG32(mmDMA_MACRO_HBW_RANGE_MASK_31_0_0, 0);
2439         WREG32(mmDMA_MACRO_HBW_RANGE_MASK_49_32_0, 0xFFF80);
2440     }
2441 
2442     /*
2443      * Protect DDR @
2444      * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END
2445      * The mask protects the first 512MB
2446      */
2447     WREG32(mmDMA_MACRO_HBW_RANGE_BASE_31_0_1, dram_addr_lo);
2448     WREG32(mmDMA_MACRO_HBW_RANGE_BASE_49_32_1, dram_addr_hi);
2449     WREG32(mmDMA_MACRO_HBW_RANGE_MASK_31_0_1, 0xE0000000);
2450     WREG32(mmDMA_MACRO_HBW_RANGE_MASK_49_32_1, 0x3FFFF);
2451 
2452     /* Protect registers */
2453 
2454     WREG32(mmDMA_MACRO_LBW_RANGE_BASE_0, lbw_rng0_base);
2455     WREG32(mmDMA_MACRO_LBW_RANGE_MASK_0, lbw_rng0_mask);
2456     WREG32(mmDMA_MACRO_LBW_RANGE_BASE_1, lbw_rng1_base);
2457     WREG32(mmDMA_MACRO_LBW_RANGE_MASK_1, lbw_rng1_mask);
2458     WREG32(mmDMA_MACRO_LBW_RANGE_BASE_2, lbw_rng2_base);
2459     WREG32(mmDMA_MACRO_LBW_RANGE_MASK_2, lbw_rng2_mask);
2460     WREG32(mmDMA_MACRO_LBW_RANGE_BASE_3, lbw_rng3_base);
2461     WREG32(mmDMA_MACRO_LBW_RANGE_MASK_3, lbw_rng3_mask);
2462     WREG32(mmDMA_MACRO_LBW_RANGE_BASE_4, lbw_rng4_base);
2463     WREG32(mmDMA_MACRO_LBW_RANGE_MASK_4, lbw_rng4_mask);
2464     WREG32(mmDMA_MACRO_LBW_RANGE_BASE_5, lbw_rng5_base);
2465     WREG32(mmDMA_MACRO_LBW_RANGE_MASK_5, lbw_rng5_mask);
2466     WREG32(mmDMA_MACRO_LBW_RANGE_BASE_6, lbw_rng6_base);
2467     WREG32(mmDMA_MACRO_LBW_RANGE_MASK_6, lbw_rng6_mask);
2468     WREG32(mmDMA_MACRO_LBW_RANGE_BASE_7, lbw_rng7_base);
2469     WREG32(mmDMA_MACRO_LBW_RANGE_MASK_7, lbw_rng7_mask);
2470     WREG32(mmDMA_MACRO_LBW_RANGE_BASE_8, lbw_rng8_base);
2471     WREG32(mmDMA_MACRO_LBW_RANGE_MASK_8, lbw_rng8_mask);
2472     WREG32(mmDMA_MACRO_LBW_RANGE_BASE_9, lbw_rng9_base);
2473     WREG32(mmDMA_MACRO_LBW_RANGE_MASK_9, lbw_rng9_mask);
2474     WREG32(mmDMA_MACRO_LBW_RANGE_BASE_10, lbw_rng10_base);
2475     WREG32(mmDMA_MACRO_LBW_RANGE_MASK_10, lbw_rng10_mask);
2476     WREG32(mmDMA_MACRO_LBW_RANGE_BASE_11, lbw_rng11_base);
2477     WREG32(mmDMA_MACRO_LBW_RANGE_MASK_11, lbw_rng11_mask);
2478     WREG32(mmDMA_MACRO_LBW_RANGE_BASE_12, lbw_rng12_base);
2479     WREG32(mmDMA_MACRO_LBW_RANGE_MASK_12, lbw_rng12_mask);
2480     WREG32(mmDMA_MACRO_LBW_RANGE_BASE_13, lbw_rng13_base);
2481     WREG32(mmDMA_MACRO_LBW_RANGE_MASK_13, lbw_rng13_mask);
2482 
2483     WREG32(mmMME1_RTR_LBW_RANGE_HIT, 0xFFFF);
2484     WREG32(mmMME2_RTR_LBW_RANGE_HIT, 0xFFFF);
2485     WREG32(mmMME3_RTR_LBW_RANGE_HIT, 0xFFFF);
2486     WREG32(mmMME4_RTR_LBW_RANGE_HIT, 0xFFFF);
2487     WREG32(mmMME5_RTR_LBW_RANGE_HIT, 0xFFFF);
2488     WREG32(mmMME6_RTR_LBW_RANGE_HIT, 0xFFFF);
2489 
2490     WREG32(mmMME1_RTR_HBW_RANGE_HIT, 0xFE);
2491     WREG32(mmMME2_RTR_HBW_RANGE_HIT, 0xFE);
2492     WREG32(mmMME3_RTR_HBW_RANGE_HIT, 0xFE);
2493     WREG32(mmMME4_RTR_HBW_RANGE_HIT, 0xFE);
2494     WREG32(mmMME5_RTR_HBW_RANGE_HIT, 0xFE);
2495     WREG32(mmMME6_RTR_HBW_RANGE_HIT, 0xFE);
2496 
2497     /* Protect HOST */
2498     WREG32(mmMME1_RTR_HBW_RANGE_BASE_L_0, 0);
2499     WREG32(mmMME1_RTR_HBW_RANGE_BASE_H_0, 0);
2500     WREG32(mmMME1_RTR_HBW_RANGE_MASK_L_0, 0);
2501     WREG32(mmMME1_RTR_HBW_RANGE_MASK_H_0, 0xFFF80);
2502 
2503     WREG32(mmMME2_RTR_HBW_RANGE_BASE_L_0, 0);
2504     WREG32(mmMME2_RTR_HBW_RANGE_BASE_H_0, 0);
2505     WREG32(mmMME2_RTR_HBW_RANGE_MASK_L_0, 0);
2506     WREG32(mmMME2_RTR_HBW_RANGE_MASK_H_0, 0xFFF80);
2507 
2508     WREG32(mmMME3_RTR_HBW_RANGE_BASE_L_0, 0);
2509     WREG32(mmMME3_RTR_HBW_RANGE_BASE_H_0, 0);
2510     WREG32(mmMME3_RTR_HBW_RANGE_MASK_L_0, 0);
2511     WREG32(mmMME3_RTR_HBW_RANGE_MASK_H_0, 0xFFF80);
2512 
2513     WREG32(mmMME4_RTR_HBW_RANGE_BASE_L_0, 0);
2514     WREG32(mmMME4_RTR_HBW_RANGE_BASE_H_0, 0);
2515     WREG32(mmMME4_RTR_HBW_RANGE_MASK_L_0, 0);
2516     WREG32(mmMME4_RTR_HBW_RANGE_MASK_H_0, 0xFFF80);
2517 
2518     WREG32(mmMME5_RTR_HBW_RANGE_BASE_L_0, 0);
2519     WREG32(mmMME5_RTR_HBW_RANGE_BASE_H_0, 0);
2520     WREG32(mmMME5_RTR_HBW_RANGE_MASK_L_0, 0);
2521     WREG32(mmMME5_RTR_HBW_RANGE_MASK_H_0, 0xFFF80);
2522 
2523     WREG32(mmMME6_RTR_HBW_RANGE_BASE_L_0, 0);
2524     WREG32(mmMME6_RTR_HBW_RANGE_BASE_H_0, 0);
2525     WREG32(mmMME6_RTR_HBW_RANGE_MASK_L_0, 0);
2526     WREG32(mmMME6_RTR_HBW_RANGE_MASK_H_0, 0xFFF80);
2527 
2528     /*
2529      * Protect DDR @
2530      * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END
2531      * The mask protects the first 512MB
2532      */
2533     WREG32(mmMME1_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
2534     WREG32(mmMME1_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
2535     WREG32(mmMME1_RTR_HBW_RANGE_MASK_L_1, 0xE0000000);
2536     WREG32(mmMME1_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
2537 
2538     WREG32(mmMME2_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
2539     WREG32(mmMME2_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
2540     WREG32(mmMME2_RTR_HBW_RANGE_MASK_L_1, 0xE0000000);
2541     WREG32(mmMME2_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
2542 
2543     WREG32(mmMME3_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
2544     WREG32(mmMME3_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
2545     WREG32(mmMME3_RTR_HBW_RANGE_MASK_L_1, 0xE0000000);
2546     WREG32(mmMME3_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
2547 
2548     WREG32(mmMME4_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
2549     WREG32(mmMME4_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
2550     WREG32(mmMME4_RTR_HBW_RANGE_MASK_L_1, 0xE0000000);
2551     WREG32(mmMME4_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
2552 
2553     WREG32(mmMME5_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
2554     WREG32(mmMME5_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
2555     WREG32(mmMME5_RTR_HBW_RANGE_MASK_L_1, 0xE0000000);
2556     WREG32(mmMME5_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
2557 
2558     WREG32(mmMME6_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
2559     WREG32(mmMME6_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
2560     WREG32(mmMME6_RTR_HBW_RANGE_MASK_L_1, 0xE0000000);
2561     WREG32(mmMME6_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
2562 
2563     WREG32(mmMME1_RTR_LBW_RANGE_BASE_0, lbw_rng0_base);
2564     WREG32(mmMME1_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
2565     WREG32(mmMME1_RTR_LBW_RANGE_BASE_1, lbw_rng1_base);
2566     WREG32(mmMME1_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
2567     WREG32(mmMME1_RTR_LBW_RANGE_BASE_2, lbw_rng2_base);
2568     WREG32(mmMME1_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
2569     WREG32(mmMME1_RTR_LBW_RANGE_BASE_3, lbw_rng3_base);
2570     WREG32(mmMME1_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
2571     WREG32(mmMME1_RTR_LBW_RANGE_BASE_4, lbw_rng4_base);
2572     WREG32(mmMME1_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
2573     WREG32(mmMME1_RTR_LBW_RANGE_BASE_5, lbw_rng5_base);
2574     WREG32(mmMME1_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
2575     WREG32(mmMME1_RTR_LBW_RANGE_BASE_6, lbw_rng6_base);
2576     WREG32(mmMME1_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
2577     WREG32(mmMME1_RTR_LBW_RANGE_BASE_7, lbw_rng7_base);
2578     WREG32(mmMME1_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
2579     WREG32(mmMME1_RTR_LBW_RANGE_BASE_8, lbw_rng8_base);
2580     WREG32(mmMME1_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
2581     WREG32(mmMME1_RTR_LBW_RANGE_BASE_9, lbw_rng9_base);
2582     WREG32(mmMME1_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
2583     WREG32(mmMME1_RTR_LBW_RANGE_BASE_10, lbw_rng10_base);
2584     WREG32(mmMME1_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
2585     WREG32(mmMME1_RTR_LBW_RANGE_BASE_11, lbw_rng11_base);
2586     WREG32(mmMME1_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
2587     WREG32(mmMME1_RTR_LBW_RANGE_BASE_12, lbw_rng12_base);
2588     WREG32(mmMME1_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
2589     WREG32(mmMME1_RTR_LBW_RANGE_BASE_13, lbw_rng13_base);
2590     WREG32(mmMME1_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
2591 
2592     WREG32(mmMME2_RTR_LBW_RANGE_BASE_0, lbw_rng0_base);
2593     WREG32(mmMME2_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
2594     WREG32(mmMME2_RTR_LBW_RANGE_BASE_1, lbw_rng1_base);
2595     WREG32(mmMME2_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
2596     WREG32(mmMME2_RTR_LBW_RANGE_BASE_2, lbw_rng2_base);
2597     WREG32(mmMME2_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
2598     WREG32(mmMME2_RTR_LBW_RANGE_BASE_3, lbw_rng3_base);
2599     WREG32(mmMME2_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
2600     WREG32(mmMME2_RTR_LBW_RANGE_BASE_4, lbw_rng4_base);
2601     WREG32(mmMME2_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
2602     WREG32(mmMME2_RTR_LBW_RANGE_BASE_5, lbw_rng5_base);
2603     WREG32(mmMME2_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
2604     WREG32(mmMME2_RTR_LBW_RANGE_BASE_6, lbw_rng6_base);
2605     WREG32(mmMME2_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
2606     WREG32(mmMME2_RTR_LBW_RANGE_BASE_7, lbw_rng7_base);
2607     WREG32(mmMME2_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
2608     WREG32(mmMME2_RTR_LBW_RANGE_BASE_8, lbw_rng8_base);
2609     WREG32(mmMME2_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
2610     WREG32(mmMME2_RTR_LBW_RANGE_BASE_9, lbw_rng9_base);
2611     WREG32(mmMME2_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
2612     WREG32(mmMME2_RTR_LBW_RANGE_BASE_10, lbw_rng10_base);
2613     WREG32(mmMME2_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
2614     WREG32(mmMME2_RTR_LBW_RANGE_BASE_11, lbw_rng11_base);
2615     WREG32(mmMME2_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
2616     WREG32(mmMME2_RTR_LBW_RANGE_BASE_12, lbw_rng12_base);
2617     WREG32(mmMME2_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
2618     WREG32(mmMME2_RTR_LBW_RANGE_BASE_13, lbw_rng13_base);
2619     WREG32(mmMME2_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
2620 
2621     WREG32(mmMME3_RTR_LBW_RANGE_BASE_0, lbw_rng0_base);
2622     WREG32(mmMME3_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
2623     WREG32(mmMME3_RTR_LBW_RANGE_BASE_1, lbw_rng1_base);
2624     WREG32(mmMME3_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
2625     WREG32(mmMME3_RTR_LBW_RANGE_BASE_2, lbw_rng2_base);
2626     WREG32(mmMME3_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
2627     WREG32(mmMME3_RTR_LBW_RANGE_BASE_3, lbw_rng3_base);
2628     WREG32(mmMME3_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
2629     WREG32(mmMME3_RTR_LBW_RANGE_BASE_4, lbw_rng4_base);
2630     WREG32(mmMME3_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
2631     WREG32(mmMME3_RTR_LBW_RANGE_BASE_5, lbw_rng5_base);
2632     WREG32(mmMME3_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
2633     WREG32(mmMME3_RTR_LBW_RANGE_BASE_6, lbw_rng6_base);
2634     WREG32(mmMME3_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
2635     WREG32(mmMME3_RTR_LBW_RANGE_BASE_7, lbw_rng7_base);
2636     WREG32(mmMME3_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
2637     WREG32(mmMME3_RTR_LBW_RANGE_BASE_8, lbw_rng8_base);
2638     WREG32(mmMME3_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
2639     WREG32(mmMME3_RTR_LBW_RANGE_BASE_9, lbw_rng9_base);
2640     WREG32(mmMME3_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
2641     WREG32(mmMME3_RTR_LBW_RANGE_BASE_10, lbw_rng10_base);
2642     WREG32(mmMME3_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
2643     WREG32(mmMME3_RTR_LBW_RANGE_BASE_11, lbw_rng11_base);
2644     WREG32(mmMME3_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
2645     WREG32(mmMME3_RTR_LBW_RANGE_BASE_12, lbw_rng12_base);
2646     WREG32(mmMME3_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
2647     WREG32(mmMME3_RTR_LBW_RANGE_BASE_13, lbw_rng13_base);
2648     WREG32(mmMME3_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
2649 
2650     WREG32(mmMME4_RTR_LBW_RANGE_BASE_0, lbw_rng0_base);
2651     WREG32(mmMME4_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
2652     WREG32(mmMME4_RTR_LBW_RANGE_BASE_1, lbw_rng1_base);
2653     WREG32(mmMME4_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
2654     WREG32(mmMME4_RTR_LBW_RANGE_BASE_2, lbw_rng2_base);
2655     WREG32(mmMME4_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
2656     WREG32(mmMME4_RTR_LBW_RANGE_BASE_3, lbw_rng3_base);
2657     WREG32(mmMME4_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
2658     WREG32(mmMME4_RTR_LBW_RANGE_BASE_4, lbw_rng4_base);
2659     WREG32(mmMME4_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
2660     WREG32(mmMME4_RTR_LBW_RANGE_BASE_5, lbw_rng5_base);
2661     WREG32(mmMME4_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
2662     WREG32(mmMME4_RTR_LBW_RANGE_BASE_6, lbw_rng6_base);
2663     WREG32(mmMME4_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
2664     WREG32(mmMME4_RTR_LBW_RANGE_BASE_7, lbw_rng7_base);
2665     WREG32(mmMME4_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
2666     WREG32(mmMME4_RTR_LBW_RANGE_BASE_8, lbw_rng8_base);
2667     WREG32(mmMME4_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
2668     WREG32(mmMME4_RTR_LBW_RANGE_BASE_9, lbw_rng9_base);
2669     WREG32(mmMME4_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
2670     WREG32(mmMME4_RTR_LBW_RANGE_BASE_10, lbw_rng10_base);
2671     WREG32(mmMME4_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
2672     WREG32(mmMME4_RTR_LBW_RANGE_BASE_11, lbw_rng11_base);
2673     WREG32(mmMME4_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
2674     WREG32(mmMME4_RTR_LBW_RANGE_BASE_12, lbw_rng12_base);
2675     WREG32(mmMME4_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
2676     WREG32(mmMME4_RTR_LBW_RANGE_BASE_13, lbw_rng13_base);
2677     WREG32(mmMME4_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
2678 
2679     WREG32(mmMME5_RTR_LBW_RANGE_BASE_0, lbw_rng0_base);
2680     WREG32(mmMME5_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
2681     WREG32(mmMME5_RTR_LBW_RANGE_BASE_1, lbw_rng1_base);
2682     WREG32(mmMME5_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
2683     WREG32(mmMME5_RTR_LBW_RANGE_BASE_2, lbw_rng2_base);
2684     WREG32(mmMME5_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
2685     WREG32(mmMME5_RTR_LBW_RANGE_BASE_3, lbw_rng3_base);
2686     WREG32(mmMME5_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
2687     WREG32(mmMME5_RTR_LBW_RANGE_BASE_4, lbw_rng4_base);
2688     WREG32(mmMME5_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
2689     WREG32(mmMME5_RTR_LBW_RANGE_BASE_5, lbw_rng5_base);
2690     WREG32(mmMME5_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
2691     WREG32(mmMME5_RTR_LBW_RANGE_BASE_6, lbw_rng6_base);
2692     WREG32(mmMME5_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
2693     WREG32(mmMME5_RTR_LBW_RANGE_BASE_7, lbw_rng7_base);
2694     WREG32(mmMME5_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
2695     WREG32(mmMME5_RTR_LBW_RANGE_BASE_8, lbw_rng8_base);
2696     WREG32(mmMME5_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
2697     WREG32(mmMME5_RTR_LBW_RANGE_BASE_9, lbw_rng9_base);
2698     WREG32(mmMME5_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
2699     WREG32(mmMME5_RTR_LBW_RANGE_BASE_10, lbw_rng10_base);
2700     WREG32(mmMME5_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
2701     WREG32(mmMME5_RTR_LBW_RANGE_BASE_11, lbw_rng11_base);
2702     WREG32(mmMME5_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
2703     WREG32(mmMME5_RTR_LBW_RANGE_BASE_12, lbw_rng12_base);
2704     WREG32(mmMME5_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
2705     WREG32(mmMME5_RTR_LBW_RANGE_BASE_13, lbw_rng13_base);
2706     WREG32(mmMME5_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
2707 
2708     WREG32(mmMME6_RTR_LBW_RANGE_BASE_0, lbw_rng0_base);
2709     WREG32(mmMME6_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
2710     WREG32(mmMME6_RTR_LBW_RANGE_BASE_1, lbw_rng1_base);
2711     WREG32(mmMME6_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
2712     WREG32(mmMME6_RTR_LBW_RANGE_BASE_2, lbw_rng2_base);
2713     WREG32(mmMME6_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
2714     WREG32(mmMME6_RTR_LBW_RANGE_BASE_3, lbw_rng3_base);
2715     WREG32(mmMME6_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
2716     WREG32(mmMME6_RTR_LBW_RANGE_BASE_4, lbw_rng4_base);
2717     WREG32(mmMME6_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
2718     WREG32(mmMME6_RTR_LBW_RANGE_BASE_5, lbw_rng5_base);
2719     WREG32(mmMME6_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
2720     WREG32(mmMME6_RTR_LBW_RANGE_BASE_6, lbw_rng6_base);
2721     WREG32(mmMME6_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
2722     WREG32(mmMME6_RTR_LBW_RANGE_BASE_7, lbw_rng7_base);
2723     WREG32(mmMME6_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
2724     WREG32(mmMME6_RTR_LBW_RANGE_BASE_8, lbw_rng8_base);
2725     WREG32(mmMME6_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
2726     WREG32(mmMME6_RTR_LBW_RANGE_BASE_9, lbw_rng9_base);
2727     WREG32(mmMME6_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
2728     WREG32(mmMME6_RTR_LBW_RANGE_BASE_10, lbw_rng10_base);
2729     WREG32(mmMME6_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
2730     WREG32(mmMME6_RTR_LBW_RANGE_BASE_11, lbw_rng11_base);
2731     WREG32(mmMME6_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
2732     WREG32(mmMME6_RTR_LBW_RANGE_BASE_12, lbw_rng12_base);
2733     WREG32(mmMME6_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
2734     WREG32(mmMME6_RTR_LBW_RANGE_BASE_13, lbw_rng13_base);
2735     WREG32(mmMME6_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
2736 
2737     WREG32(mmTPC0_NRTR_LBW_RANGE_HIT, 0xFFFF);
2738     WREG32(mmTPC0_NRTR_HBW_RANGE_HIT, 0xFE);
2739 
2740     /* Protect HOST */
2741     WREG32(mmTPC0_NRTR_HBW_RANGE_BASE_L_0, 0);
2742     WREG32(mmTPC0_NRTR_HBW_RANGE_BASE_H_0, 0);
2743     WREG32(mmTPC0_NRTR_HBW_RANGE_MASK_L_0, 0);
2744     WREG32(mmTPC0_NRTR_HBW_RANGE_MASK_H_0, 0xFFF80);
2745 
2746     /*
2747      * Protect DDR @
2748      * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END
2749      * The mask protects the first 512MB
2750      */
2751     WREG32(mmTPC0_NRTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
2752     WREG32(mmTPC0_NRTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
2753     WREG32(mmTPC0_NRTR_HBW_RANGE_MASK_L_1, 0xE0000000);
2754     WREG32(mmTPC0_NRTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
2755 
2756     WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_0, lbw_rng0_base);
2757     WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
2758     WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_1, lbw_rng1_base);
2759     WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
2760     WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_2, lbw_rng2_base);
2761     WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
2762     WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_3, lbw_rng3_base);
2763     WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
2764     WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_4, lbw_rng4_base);
2765     WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
2766     WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_5, lbw_rng5_base);
2767     WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
2768     WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_6, lbw_rng6_base);
2769     WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
2770     WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_7, lbw_rng7_base);
2771     WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
2772     WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_8, lbw_rng8_base);
2773     WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
2774     WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_9, lbw_rng9_base);
2775     WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
2776     WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_10, lbw_rng10_base);
2777     WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
2778     WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_11, lbw_rng11_base);
2779     WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
2780     WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_12, lbw_rng12_base);
2781     WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
2782     WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_13, lbw_rng13_base);
2783     WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
2784 
2785     WREG32(mmTPC1_RTR_LBW_RANGE_HIT, 0xFFFF);
2786     WREG32(mmTPC1_RTR_HBW_RANGE_HIT, 0xFE);
2787 
2788     /* Protect HOST */
2789     WREG32(mmTPC1_RTR_HBW_RANGE_BASE_L_0, 0);
2790     WREG32(mmTPC1_RTR_HBW_RANGE_BASE_H_0, 0);
2791     WREG32(mmTPC1_RTR_HBW_RANGE_MASK_L_0, 0);
2792     WREG32(mmTPC1_RTR_HBW_RANGE_MASK_H_0, 0xFFF80);
2793 
2794     /*
2795      * Protect DDR @
2796      * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END
2797      * The mask protects the first 512MB
2798      */
2799     WREG32(mmTPC1_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
2800     WREG32(mmTPC1_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
2801     WREG32(mmTPC1_RTR_HBW_RANGE_MASK_L_1, 0xE0000000);
2802     WREG32(mmTPC1_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
2803 
2804     WREG32(mmTPC1_RTR_LBW_RANGE_BASE_0, lbw_rng0_base);
2805     WREG32(mmTPC1_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
2806     WREG32(mmTPC1_RTR_LBW_RANGE_BASE_1, lbw_rng1_base);
2807     WREG32(mmTPC1_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
2808     WREG32(mmTPC1_RTR_LBW_RANGE_BASE_2, lbw_rng2_base);
2809     WREG32(mmTPC1_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
2810     WREG32(mmTPC1_RTR_LBW_RANGE_BASE_3, lbw_rng3_base);
2811     WREG32(mmTPC1_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
2812     WREG32(mmTPC1_RTR_LBW_RANGE_BASE_4, lbw_rng4_base);
2813     WREG32(mmTPC1_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
2814     WREG32(mmTPC1_RTR_LBW_RANGE_BASE_5, lbw_rng5_base);
2815     WREG32(mmTPC1_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
2816     WREG32(mmTPC1_RTR_LBW_RANGE_BASE_6, lbw_rng6_base);
2817     WREG32(mmTPC1_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
2818     WREG32(mmTPC1_RTR_LBW_RANGE_BASE_7, lbw_rng7_base);
2819     WREG32(mmTPC1_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
2820     WREG32(mmTPC1_RTR_LBW_RANGE_BASE_8, lbw_rng8_base);
2821     WREG32(mmTPC1_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
2822     WREG32(mmTPC1_RTR_LBW_RANGE_BASE_9, lbw_rng9_base);
2823     WREG32(mmTPC1_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
2824     WREG32(mmTPC1_RTR_LBW_RANGE_BASE_10, lbw_rng10_base);
2825     WREG32(mmTPC1_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
2826     WREG32(mmTPC1_RTR_LBW_RANGE_BASE_11, lbw_rng11_base);
2827     WREG32(mmTPC1_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
2828     WREG32(mmTPC1_RTR_LBW_RANGE_BASE_12, lbw_rng12_base);
2829     WREG32(mmTPC1_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
2830     WREG32(mmTPC1_RTR_LBW_RANGE_BASE_13, lbw_rng13_base);
2831     WREG32(mmTPC1_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
2832 
2833     WREG32(mmTPC2_RTR_LBW_RANGE_HIT, 0xFFFF);
2834     WREG32(mmTPC2_RTR_HBW_RANGE_HIT, 0xFE);
2835 
2836     /* Protect HOST */
2837     WREG32(mmTPC2_RTR_HBW_RANGE_BASE_L_0, 0);
2838     WREG32(mmTPC2_RTR_HBW_RANGE_BASE_H_0, 0);
2839     WREG32(mmTPC2_RTR_HBW_RANGE_MASK_L_0, 0);
2840     WREG32(mmTPC2_RTR_HBW_RANGE_MASK_H_0, 0xFFF80);
2841 
2842     /*
2843      * Protect DDR @
2844      * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END
2845      * The mask protects the first 512MB
2846      */
2847     WREG32(mmTPC2_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
2848     WREG32(mmTPC2_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
2849     WREG32(mmTPC2_RTR_HBW_RANGE_MASK_L_1, 0xE0000000);
2850     WREG32(mmTPC2_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
2851 
2852     WREG32(mmTPC2_RTR_LBW_RANGE_BASE_0, lbw_rng0_base);
2853     WREG32(mmTPC2_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
2854     WREG32(mmTPC2_RTR_LBW_RANGE_BASE_1, lbw_rng1_base);
2855     WREG32(mmTPC2_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
2856     WREG32(mmTPC2_RTR_LBW_RANGE_BASE_2, lbw_rng2_base);
2857     WREG32(mmTPC2_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
2858     WREG32(mmTPC2_RTR_LBW_RANGE_BASE_3, lbw_rng3_base);
2859     WREG32(mmTPC2_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
2860     WREG32(mmTPC2_RTR_LBW_RANGE_BASE_4, lbw_rng4_base);
2861     WREG32(mmTPC2_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
2862     WREG32(mmTPC2_RTR_LBW_RANGE_BASE_5, lbw_rng5_base);
2863     WREG32(mmTPC2_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
2864     WREG32(mmTPC2_RTR_LBW_RANGE_BASE_6, lbw_rng6_base);
2865     WREG32(mmTPC2_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
2866     WREG32(mmTPC2_RTR_LBW_RANGE_BASE_7, lbw_rng7_base);
2867     WREG32(mmTPC2_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
2868     WREG32(mmTPC2_RTR_LBW_RANGE_BASE_8, lbw_rng8_base);
2869     WREG32(mmTPC2_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
2870     WREG32(mmTPC2_RTR_LBW_RANGE_BASE_9, lbw_rng9_base);
2871     WREG32(mmTPC2_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
2872     WREG32(mmTPC2_RTR_LBW_RANGE_BASE_10, lbw_rng10_base);
2873     WREG32(mmTPC2_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
2874     WREG32(mmTPC2_RTR_LBW_RANGE_BASE_11, lbw_rng11_base);
2875     WREG32(mmTPC2_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
2876     WREG32(mmTPC2_RTR_LBW_RANGE_BASE_12, lbw_rng12_base);
2877     WREG32(mmTPC2_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
2878     WREG32(mmTPC2_RTR_LBW_RANGE_BASE_13, lbw_rng13_base);
2879     WREG32(mmTPC2_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
2880 
2881     WREG32(mmTPC3_RTR_LBW_RANGE_HIT, 0xFFFF);
2882     WREG32(mmTPC3_RTR_HBW_RANGE_HIT, 0xFE);
2883 
2884     /* Protect HOST */
2885     WREG32(mmTPC3_RTR_HBW_RANGE_BASE_L_0, 0);
2886     WREG32(mmTPC3_RTR_HBW_RANGE_BASE_H_0, 0);
2887     WREG32(mmTPC3_RTR_HBW_RANGE_MASK_L_0, 0);
2888     WREG32(mmTPC3_RTR_HBW_RANGE_MASK_H_0, 0xFFF80);
2889 
2890     /*
2891      * Protect DDR @
2892      * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END
2893      * The mask protects the first 512MB
2894      */
2895     WREG32(mmTPC3_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
2896     WREG32(mmTPC3_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
2897     WREG32(mmTPC3_RTR_HBW_RANGE_MASK_L_1, 0xE0000000);
2898     WREG32(mmTPC3_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
2899 
2900     WREG32(mmTPC3_RTR_LBW_RANGE_BASE_0, lbw_rng0_base);
2901     WREG32(mmTPC3_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
2902     WREG32(mmTPC3_RTR_LBW_RANGE_BASE_1, lbw_rng1_base);
2903     WREG32(mmTPC3_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
2904     WREG32(mmTPC3_RTR_LBW_RANGE_BASE_2, lbw_rng2_base);
2905     WREG32(mmTPC3_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
2906     WREG32(mmTPC3_RTR_LBW_RANGE_BASE_3, lbw_rng3_base);
2907     WREG32(mmTPC3_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
2908     WREG32(mmTPC3_RTR_LBW_RANGE_BASE_4, lbw_rng4_base);
2909     WREG32(mmTPC3_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
2910     WREG32(mmTPC3_RTR_LBW_RANGE_BASE_5, lbw_rng5_base);
2911     WREG32(mmTPC3_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
2912     WREG32(mmTPC3_RTR_LBW_RANGE_BASE_6, lbw_rng6_base);
2913     WREG32(mmTPC3_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
2914     WREG32(mmTPC3_RTR_LBW_RANGE_BASE_7, lbw_rng7_base);
2915     WREG32(mmTPC3_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
2916     WREG32(mmTPC3_RTR_LBW_RANGE_BASE_8, lbw_rng8_base);
2917     WREG32(mmTPC3_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
2918     WREG32(mmTPC3_RTR_LBW_RANGE_BASE_9, lbw_rng9_base);
2919     WREG32(mmTPC3_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
2920     WREG32(mmTPC3_RTR_LBW_RANGE_BASE_10, lbw_rng10_base);
2921     WREG32(mmTPC3_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
2922     WREG32(mmTPC3_RTR_LBW_RANGE_BASE_11, lbw_rng11_base);
2923     WREG32(mmTPC3_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
2924     WREG32(mmTPC3_RTR_LBW_RANGE_BASE_12, lbw_rng12_base);
2925     WREG32(mmTPC3_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
2926     WREG32(mmTPC3_RTR_LBW_RANGE_BASE_13, lbw_rng13_base);
2927     WREG32(mmTPC3_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
2928 
2929     WREG32(mmTPC4_RTR_LBW_RANGE_HIT, 0xFFFF);
2930     WREG32(mmTPC4_RTR_HBW_RANGE_HIT, 0xFE);
2931 
2932     /* Protect HOST */
2933     WREG32(mmTPC4_RTR_HBW_RANGE_BASE_L_0, 0);
2934     WREG32(mmTPC4_RTR_HBW_RANGE_BASE_H_0, 0);
2935     WREG32(mmTPC4_RTR_HBW_RANGE_MASK_L_0, 0);
2936     WREG32(mmTPC4_RTR_HBW_RANGE_MASK_H_0, 0xFFF80);
2937 
2938     /*
2939      * Protect DDR @
2940      * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END
2941      * The mask protects the first 512MB
2942      */
2943     WREG32(mmTPC4_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
2944     WREG32(mmTPC4_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
2945     WREG32(mmTPC4_RTR_HBW_RANGE_MASK_L_1, 0xE0000000);
2946     WREG32(mmTPC4_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
2947 
2948     WREG32(mmTPC4_RTR_LBW_RANGE_BASE_0, lbw_rng0_base);
2949     WREG32(mmTPC4_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
2950     WREG32(mmTPC4_RTR_LBW_RANGE_BASE_1, lbw_rng1_base);
2951     WREG32(mmTPC4_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
2952     WREG32(mmTPC4_RTR_LBW_RANGE_BASE_2, lbw_rng2_base);
2953     WREG32(mmTPC4_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
2954     WREG32(mmTPC4_RTR_LBW_RANGE_BASE_3, lbw_rng3_base);
2955     WREG32(mmTPC4_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
2956     WREG32(mmTPC4_RTR_LBW_RANGE_BASE_4, lbw_rng4_base);
2957     WREG32(mmTPC4_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
2958     WREG32(mmTPC4_RTR_LBW_RANGE_BASE_5, lbw_rng5_base);
2959     WREG32(mmTPC4_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
2960     WREG32(mmTPC4_RTR_LBW_RANGE_BASE_6, lbw_rng6_base);
2961     WREG32(mmTPC4_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
2962     WREG32(mmTPC4_RTR_LBW_RANGE_BASE_7, lbw_rng7_base);
2963     WREG32(mmTPC4_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
2964     WREG32(mmTPC4_RTR_LBW_RANGE_BASE_8, lbw_rng8_base);
2965     WREG32(mmTPC4_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
2966     WREG32(mmTPC4_RTR_LBW_RANGE_BASE_9, lbw_rng9_base);
2967     WREG32(mmTPC4_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
2968     WREG32(mmTPC4_RTR_LBW_RANGE_BASE_10, lbw_rng10_base);
2969     WREG32(mmTPC4_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
2970     WREG32(mmTPC4_RTR_LBW_RANGE_BASE_11, lbw_rng11_base);
2971     WREG32(mmTPC4_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
2972     WREG32(mmTPC4_RTR_LBW_RANGE_BASE_12, lbw_rng12_base);
2973     WREG32(mmTPC4_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
2974     WREG32(mmTPC4_RTR_LBW_RANGE_BASE_13, lbw_rng13_base);
2975     WREG32(mmTPC4_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
2976 
2977     WREG32(mmTPC5_RTR_LBW_RANGE_HIT, 0xFFFF);
2978     WREG32(mmTPC5_RTR_HBW_RANGE_HIT, 0xFE);
2979 
2980     /* Protect HOST */
2981     WREG32(mmTPC5_RTR_HBW_RANGE_BASE_L_0, 0);
2982     WREG32(mmTPC5_RTR_HBW_RANGE_BASE_H_0, 0);
2983     WREG32(mmTPC5_RTR_HBW_RANGE_MASK_L_0, 0);
2984     WREG32(mmTPC5_RTR_HBW_RANGE_MASK_H_0, 0xFFF80);
2985 
2986     /*
2987      * Protect DDR @
2988      * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END
2989      * The mask protects the first 512MB
2990      */
2991     WREG32(mmTPC5_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
2992     WREG32(mmTPC5_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
2993     WREG32(mmTPC5_RTR_HBW_RANGE_MASK_L_1, 0xE0000000);
2994     WREG32(mmTPC5_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
2995 
2996     WREG32(mmTPC5_RTR_LBW_RANGE_BASE_0, lbw_rng0_base);
2997     WREG32(mmTPC5_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
2998     WREG32(mmTPC5_RTR_LBW_RANGE_BASE_1, lbw_rng1_base);
2999     WREG32(mmTPC5_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
3000     WREG32(mmTPC5_RTR_LBW_RANGE_BASE_2, lbw_rng2_base);
3001     WREG32(mmTPC5_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
3002     WREG32(mmTPC5_RTR_LBW_RANGE_BASE_3, lbw_rng3_base);
3003     WREG32(mmTPC5_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
3004     WREG32(mmTPC5_RTR_LBW_RANGE_BASE_4, lbw_rng4_base);
3005     WREG32(mmTPC5_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
3006     WREG32(mmTPC5_RTR_LBW_RANGE_BASE_5, lbw_rng5_base);
3007     WREG32(mmTPC5_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
3008     WREG32(mmTPC5_RTR_LBW_RANGE_BASE_6, lbw_rng6_base);
3009     WREG32(mmTPC5_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
3010     WREG32(mmTPC5_RTR_LBW_RANGE_BASE_7, lbw_rng7_base);
3011     WREG32(mmTPC5_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
3012     WREG32(mmTPC5_RTR_LBW_RANGE_BASE_8, lbw_rng8_base);
3013     WREG32(mmTPC5_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
3014     WREG32(mmTPC5_RTR_LBW_RANGE_BASE_9, lbw_rng9_base);
3015     WREG32(mmTPC5_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
3016     WREG32(mmTPC5_RTR_LBW_RANGE_BASE_10, lbw_rng10_base);
3017     WREG32(mmTPC5_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
3018     WREG32(mmTPC5_RTR_LBW_RANGE_BASE_11, lbw_rng11_base);
3019     WREG32(mmTPC5_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
3020     WREG32(mmTPC5_RTR_LBW_RANGE_BASE_12, lbw_rng12_base);
3021     WREG32(mmTPC5_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
3022     WREG32(mmTPC5_RTR_LBW_RANGE_BASE_13, lbw_rng13_base);
3023     WREG32(mmTPC5_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
3024 
3025     WREG32(mmTPC6_RTR_LBW_RANGE_HIT, 0xFFFF);
3026     WREG32(mmTPC6_RTR_HBW_RANGE_HIT, 0xFE);
3027 
3028     /* Protect HOST */
3029     WREG32(mmTPC6_RTR_HBW_RANGE_BASE_L_0, 0);
3030     WREG32(mmTPC6_RTR_HBW_RANGE_BASE_H_0, 0);
3031     WREG32(mmTPC6_RTR_HBW_RANGE_MASK_L_0, 0);
3032     WREG32(mmTPC6_RTR_HBW_RANGE_MASK_H_0, 0xFFF80);
3033 
3034     /*
3035      * Protect DDR @
3036      * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END
3037      * The mask protects the first 512MB
3038      */
3039     WREG32(mmTPC6_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
3040     WREG32(mmTPC6_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
3041     WREG32(mmTPC6_RTR_HBW_RANGE_MASK_L_1, 0xE0000000);
3042     WREG32(mmTPC6_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
3043 
3044     WREG32(mmTPC6_RTR_LBW_RANGE_BASE_0, lbw_rng0_base);
3045     WREG32(mmTPC6_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
3046     WREG32(mmTPC6_RTR_LBW_RANGE_BASE_1, lbw_rng1_base);
3047     WREG32(mmTPC6_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
3048     WREG32(mmTPC6_RTR_LBW_RANGE_BASE_2, lbw_rng2_base);
3049     WREG32(mmTPC6_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
3050     WREG32(mmTPC6_RTR_LBW_RANGE_BASE_3, lbw_rng3_base);
3051     WREG32(mmTPC6_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
3052     WREG32(mmTPC6_RTR_LBW_RANGE_BASE_4, lbw_rng4_base);
3053     WREG32(mmTPC6_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
3054     WREG32(mmTPC6_RTR_LBW_RANGE_BASE_5, lbw_rng5_base);
3055     WREG32(mmTPC6_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
3056     WREG32(mmTPC6_RTR_LBW_RANGE_BASE_6, lbw_rng6_base);
3057     WREG32(mmTPC6_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
3058     WREG32(mmTPC6_RTR_LBW_RANGE_BASE_7, lbw_rng7_base);
3059     WREG32(mmTPC6_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
3060     WREG32(mmTPC6_RTR_LBW_RANGE_BASE_8, lbw_rng8_base);
3061     WREG32(mmTPC6_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
3062     WREG32(mmTPC6_RTR_LBW_RANGE_BASE_9, lbw_rng9_base);
3063     WREG32(mmTPC6_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
3064     WREG32(mmTPC6_RTR_LBW_RANGE_BASE_10, lbw_rng10_base);
3065     WREG32(mmTPC6_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
3066     WREG32(mmTPC6_RTR_LBW_RANGE_BASE_11, lbw_rng11_base);
3067     WREG32(mmTPC6_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
3068     WREG32(mmTPC6_RTR_LBW_RANGE_BASE_12, lbw_rng12_base);
3069     WREG32(mmTPC6_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
3070     WREG32(mmTPC6_RTR_LBW_RANGE_BASE_13, lbw_rng13_base);
3071     WREG32(mmTPC6_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
3072 
3073     WREG32(mmTPC7_NRTR_LBW_RANGE_HIT, 0xFFFF);
3074     WREG32(mmTPC7_NRTR_HBW_RANGE_HIT, 0xFE);
3075 
3076     /* Protect HOST */
3077     WREG32(mmTPC7_NRTR_HBW_RANGE_BASE_L_0, 0);
3078     WREG32(mmTPC7_NRTR_HBW_RANGE_BASE_H_0, 0);
3079     WREG32(mmTPC7_NRTR_HBW_RANGE_MASK_L_0, 0);
3080     WREG32(mmTPC7_NRTR_HBW_RANGE_MASK_H_0, 0xFFF80);
3081 
3082     /*
3083      * Protect DDR @
3084      * DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END
3085      * The mask protects the first 512MB
3086      */
3087     WREG32(mmTPC7_NRTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
3088     WREG32(mmTPC7_NRTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
3089     WREG32(mmTPC7_NRTR_HBW_RANGE_MASK_L_1, 0xE0000000);
3090     WREG32(mmTPC7_NRTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
3091 
3092     WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_0, lbw_rng0_base);
3093     WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
3094     WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_1, lbw_rng1_base);
3095     WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
3096     WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_2, lbw_rng2_base);
3097     WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
3098     WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_3, lbw_rng3_base);
3099     WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
3100     WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_4, lbw_rng4_base);
3101     WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
3102     WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_5, lbw_rng5_base);
3103     WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
3104     WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_6, lbw_rng6_base);
3105     WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
3106     WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_7, lbw_rng7_base);
3107     WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
3108     WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_8, lbw_rng8_base);
3109     WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
3110     WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_9, lbw_rng9_base);
3111     WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
3112     WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_10, lbw_rng10_base);
3113     WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
3114     WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_11, lbw_rng11_base);
3115     WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
3116     WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_12, lbw_rng12_base);
3117     WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
3118     WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_13, lbw_rng13_base);
3119     WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
3120 
3121     goya_init_protection_bits(hdev);
3122 }
3123 
3124 void goya_ack_protection_bits_errors(struct hl_device *hdev)
3125 {
3126 
3127 }
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