habanalabs/goya/goyaP.h

0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * Copyright 2016-2022 HabanaLabs, Ltd.
0004  * All Rights Reserved.
0005  *
0006  */
0007
0008 #ifndef GOYAP_H_
0009 #define GOYAP_H_
0010
0011 #include <uapi/misc/habanalabs.h>
0012 #include "../common/habanalabs.h"
0013 #include "../include/common/hl_boot_if.h"
0014 #include "../include/goya/goya_packets.h"
0015 #include "../include/goya/goya.h"
0016 #include "../include/goya/goya_async_events.h"
0017 #include "../include/goya/goya_fw_if.h"
0018
0019 #define NUMBER_OF_CMPLT_QUEUES      5
0020 #define NUMBER_OF_EXT_HW_QUEUES     5
0021 #define NUMBER_OF_CPU_HW_QUEUES     1
0022 #define NUMBER_OF_INT_HW_QUEUES     9
0023 #define NUMBER_OF_HW_QUEUES     (NUMBER_OF_EXT_HW_QUEUES + \
0024                     NUMBER_OF_CPU_HW_QUEUES + \
0025                     NUMBER_OF_INT_HW_QUEUES)
0026
0027 /*
0028  * Number of MSIX interrupts IDS:
0029  * Each completion queue has 1 ID
0030  * The event queue has 1 ID
0031  */
0032 #define NUMBER_OF_INTERRUPTS        (NUMBER_OF_CMPLT_QUEUES + 1)
0033
0034 #if (NUMBER_OF_INTERRUPTS > GOYA_MSIX_ENTRIES)
0035 #error "Number of MSIX interrupts must be smaller or equal to GOYA_MSIX_ENTRIES"
0036 #endif
0037
0038 #define QMAN_FENCE_TIMEOUT_USEC     10000       /* 10 ms */
0039
0040 #define QMAN_STOP_TIMEOUT_USEC      100000      /* 100 ms */
0041
0042 #define CORESIGHT_TIMEOUT_USEC      100000      /* 100 ms */
0043
0044 #define GOYA_CPU_TIMEOUT_USEC       15000000    /* 15s */
0045
0046 #define TPC_ENABLED_MASK        0xFF
0047
0048 #define PLL_HIGH_DEFAULT        1575000000  /* 1.575 GHz */
0049
0050 #define MAX_POWER_DEFAULT       200000      /* 200W */
0051
0052 #define DC_POWER_DEFAULT        20000       /* 20W */
0053
0054 #define DRAM_PHYS_DEFAULT_SIZE      0x100000000ull  /* 4GB */
0055
0056 #define GOYA_DEFAULT_CARD_NAME      "HL1000"
0057
0058 #define GOYA_MAX_PENDING_CS     64
0059
0060 #if !IS_MAX_PENDING_CS_VALID(GOYA_MAX_PENDING_CS)
0061 #error "GOYA_MAX_PENDING_CS must be power of 2 and greater than 1"
0062 #endif
0063
0064 /* DRAM Memory Map */
0065
0066 #define CPU_FW_IMAGE_SIZE       0x10000000  /* 256MB */
0067 #define MMU_PAGE_TABLES_SIZE        0x0FC00000  /* 252MB */
0068 #define MMU_DRAM_DEFAULT_PAGE_SIZE  0x00200000  /* 2MB */
0069 #define MMU_CACHE_MNG_SIZE      0x00001000  /* 4KB */
0070
0071 #define CPU_FW_IMAGE_ADDR       DRAM_PHYS_BASE
0072 #define MMU_PAGE_TABLES_ADDR        (CPU_FW_IMAGE_ADDR + CPU_FW_IMAGE_SIZE)
0073 #define MMU_DRAM_DEFAULT_PAGE_ADDR  (MMU_PAGE_TABLES_ADDR + \
0074                         MMU_PAGE_TABLES_SIZE)
0075 #define MMU_CACHE_MNG_ADDR      (MMU_DRAM_DEFAULT_PAGE_ADDR + \
0076                     MMU_DRAM_DEFAULT_PAGE_SIZE)
0077 #define DRAM_DRIVER_END_ADDR        (MMU_CACHE_MNG_ADDR + \
0078                         MMU_CACHE_MNG_SIZE)
0079
0080 #define DRAM_BASE_ADDR_USER     0x20000000
0081
0082 #if (DRAM_DRIVER_END_ADDR > DRAM_BASE_ADDR_USER)
0083 #error "Driver must reserve no more than 512MB"
0084 #endif
0085
0086 /*
0087  * SRAM Memory Map for Driver
0088  *
0089  * Driver occupies DRIVER_SRAM_SIZE bytes from the start of SRAM. It is used for
0090  * MME/TPC QMANs
0091  *
0092  */
0093
0094 #define MME_QMAN_BASE_OFFSET    0x000000    /* Must be 0 */
0095 #define MME_QMAN_LENGTH     64
0096 #define TPC_QMAN_LENGTH     64
0097
0098 #define TPC0_QMAN_BASE_OFFSET   (MME_QMAN_BASE_OFFSET + \
0099                 (MME_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
0100 #define TPC1_QMAN_BASE_OFFSET   (TPC0_QMAN_BASE_OFFSET + \
0101                 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
0102 #define TPC2_QMAN_BASE_OFFSET   (TPC1_QMAN_BASE_OFFSET + \
0103                 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
0104 #define TPC3_QMAN_BASE_OFFSET   (TPC2_QMAN_BASE_OFFSET + \
0105                 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
0106 #define TPC4_QMAN_BASE_OFFSET   (TPC3_QMAN_BASE_OFFSET + \
0107                 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
0108 #define TPC5_QMAN_BASE_OFFSET   (TPC4_QMAN_BASE_OFFSET + \
0109                 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
0110 #define TPC6_QMAN_BASE_OFFSET   (TPC5_QMAN_BASE_OFFSET + \
0111                 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
0112 #define TPC7_QMAN_BASE_OFFSET   (TPC6_QMAN_BASE_OFFSET + \
0113                 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
0114
0115 #define SRAM_DRIVER_RES_OFFSET  (TPC7_QMAN_BASE_OFFSET + \
0116                 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
0117
0118 #if (SRAM_DRIVER_RES_OFFSET >= GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START)
0119 #error "MME/TPC QMANs SRAM space exceeds limit"
0120 #endif
0121
0122 #define SRAM_USER_BASE_OFFSET   GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START
0123
0124 /* Virtual address space */
0125 #define VA_HOST_SPACE_START 0x1000000000000ull  /* 256TB */
0126 #define VA_HOST_SPACE_END   0x3FF8000000000ull  /* 1PB - 1TB */
0127 #define VA_HOST_SPACE_SIZE  (VA_HOST_SPACE_END - \
0128                     VA_HOST_SPACE_START) /* 767TB */
0129
0130 #define VA_DDR_SPACE_START  0x800000000ull      /* 32GB */
0131 #define VA_DDR_SPACE_END    0x2000000000ull     /* 128GB */
0132 #define VA_DDR_SPACE_SIZE   (VA_DDR_SPACE_END - \
0133                     VA_DDR_SPACE_START) /* 128GB */
0134
0135 #if (HL_CPU_ACCESSIBLE_MEM_SIZE != SZ_2M)
0136 #error "HL_CPU_ACCESSIBLE_MEM_SIZE must be exactly 2MB to enable MMU mapping"
0137 #endif
0138
0139 #define VA_CPU_ACCESSIBLE_MEM_ADDR  0x8000000000ull
0140
0141 #define DMA_MAX_TRANSFER_SIZE   U32_MAX
0142
0143 #define HW_CAP_PLL      0x00000001
0144 #define HW_CAP_DDR_0        0x00000002
0145 #define HW_CAP_DDR_1        0x00000004
0146 #define HW_CAP_MME      0x00000008
0147 #define HW_CAP_CPU      0x00000010
0148 #define HW_CAP_DMA      0x00000020
0149 #define HW_CAP_MSIX     0x00000040
0150 #define HW_CAP_CPU_Q        0x00000080
0151 #define HW_CAP_MMU      0x00000100
0152 #define HW_CAP_TPC_MBIST    0x00000200
0153 #define HW_CAP_GOLDEN       0x00000400
0154 #define HW_CAP_TPC      0x00000800
0155
0156 struct goya_work_freq {
0157     struct hl_device *hdev;
0158     struct delayed_work work_freq;
0159 };
0160
0161 struct goya_device {
0162     /* TODO: remove hw_queues_lock after moving to scheduler code */
0163     spinlock_t  hw_queues_lock;
0164     struct goya_work_freq   *goya_work;
0165
0166     u64     mme_clk;
0167     u64     tpc_clk;
0168     u64     ic_clk;
0169
0170     u64     ddr_bar_cur_addr;
0171     u32     events_stat[GOYA_ASYNC_EVENT_ID_SIZE];
0172     u32     events_stat_aggregate[GOYA_ASYNC_EVENT_ID_SIZE];
0173     u32     hw_cap_initialized;
0174     u8      device_cpu_mmu_mappings_done;
0175
0176     enum hl_pll_frequency       curr_pll_profile;
0177     enum hl_pm_mng_profile      pm_mng_profile;
0178 };
0179
0180 int goya_set_fixed_properties(struct hl_device *hdev);
0181 int goya_mmu_init(struct hl_device *hdev);
0182 void goya_init_dma_qmans(struct hl_device *hdev);
0183 void goya_init_mme_qmans(struct hl_device *hdev);
0184 void goya_init_tpc_qmans(struct hl_device *hdev);
0185 int goya_init_cpu_queues(struct hl_device *hdev);
0186 void goya_init_security(struct hl_device *hdev);
0187 void goya_ack_protection_bits_errors(struct hl_device *hdev);
0188 int goya_late_init(struct hl_device *hdev);
0189 void goya_late_fini(struct hl_device *hdev);
0190
0191 void goya_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi);
0192 void goya_pqe_write(struct hl_device *hdev, __le64 *pqe, struct hl_bd *bd);
0193 void goya_update_eq_ci(struct hl_device *hdev, u32 val);
0194 void goya_restore_phase_topology(struct hl_device *hdev);
0195 int goya_context_switch(struct hl_device *hdev, u32 asid);
0196
0197 int goya_debugfs_i2c_read(struct hl_device *hdev, u8 i2c_bus,
0198             u8 i2c_addr, u8 i2c_reg, u32 *val);
0199 int goya_debugfs_i2c_write(struct hl_device *hdev, u8 i2c_bus,
0200             u8 i2c_addr, u8 i2c_reg, u32 val);
0201 void goya_debugfs_led_set(struct hl_device *hdev, u8 led, u8 state);
0202
0203 int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id);
0204 int goya_test_queues(struct hl_device *hdev);
0205 int goya_test_cpu_queue(struct hl_device *hdev);
0206 int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len,
0207                 u32 timeout, u64 *result);
0208
0209 long goya_get_temperature(struct hl_device *hdev, int sensor_index, u32 attr);
0210 long goya_get_voltage(struct hl_device *hdev, int sensor_index, u32 attr);
0211 long goya_get_current(struct hl_device *hdev, int sensor_index, u32 attr);
0212 long goya_get_fan_speed(struct hl_device *hdev, int sensor_index, u32 attr);
0213 long goya_get_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr);
0214 void goya_set_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr,
0215             long value);
0216 u64 goya_get_max_power(struct hl_device *hdev);
0217 void goya_set_max_power(struct hl_device *hdev, u64 value);
0218
0219 void goya_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq);
0220 void goya_add_device_attr(struct hl_device *hdev, struct attribute_group *dev_clk_attr_grp,
0221                 struct attribute_group *dev_vrm_attr_grp);
0222 int goya_cpucp_info_get(struct hl_device *hdev);
0223 int goya_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data);
0224 void goya_halt_coresight(struct hl_device *hdev, struct hl_ctx *ctx);
0225
0226 int goya_suspend(struct hl_device *hdev);
0227 int goya_resume(struct hl_device *hdev);
0228
0229 void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry);
0230 void *goya_get_events_stat(struct hl_device *hdev, bool aggregate, u32 *size);
0231
0232 void goya_add_end_of_cb_packets(struct hl_device *hdev, void *kernel_address,
0233                 u32 len, u32 original_len, u64 cq_addr, u32 cq_val,
0234                 u32 msix_vec, bool eb);
0235 int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser);
0236 int goya_scrub_device_mem(struct hl_device *hdev);
0237 void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id,
0238                 dma_addr_t *dma_handle, u16 *queue_len);
0239 u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt);
0240 int goya_send_heartbeat(struct hl_device *hdev);
0241 void *goya_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
0242                     dma_addr_t *dma_handle);
0243 void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
0244                     void *vaddr);
0245 void goya_mmu_remove_device_cpu_mappings(struct hl_device *hdev);
0246
0247 u32 goya_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx);
0248 u64 goya_get_device_time(struct hl_device *hdev);
0249 int goya_set_frequency(struct hl_device *hdev, enum hl_pll_frequency freq);
0250
0251 #endif /* GOYAP_H_ */