habanalabs/gaudi2/gaudi2_security.c

0001 // SPDX-License-Identifier: GPL-2.0
0002
0003 /*
0004  * Copyright 2020-2022 HabanaLabs, Ltd.
0005  * All Rights Reserved.
0006  */
0007
0008 #include "gaudi2P.h"
0009 #include "../include/gaudi2/asic_reg/gaudi2_regs.h"
0010
0011 #define UNSET_GLBL_SEC_BIT(array, b) ((array)[((b) / 32)] |= (1 << ((b) % 32)))
0012
0013 #define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD_MASK
0014 #define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD_MASK
0015 #define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR_MASK
0016 #define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR_MASK
0017 #define SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR_MASK
0018 #define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD \
0019         PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD_MASK
0020 #define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR \
0021         PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR_MASK
0022 #define SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR \
0023         PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR_MASK
0024
0025 /* LBW RR */
0026 #define SFT_NUM_OF_LBW_RTR      1
0027 #define SFT_LBW_RTR_OFFSET      0
0028 #define RR_LBW_LONG_MASK        0x7FFFFFFull
0029 #define RR_LBW_SHORT_MASK       0x7FFF000ull
0030
0031 /* HBW RR */
0032 #define SFT_NUM_OF_HBW_RTR      2
0033 #define RR_HBW_SHORT_LO_MASK        0xFFFFFFFF000ull
0034 #define RR_HBW_SHORT_HI_MASK        0xF00000000000ull
0035 #define RR_HBW_LONG_LO_MASK     0xFFFFFFFF000ull
0036 #define RR_HBW_LONG_HI_MASK     0xFFFFF00000000000ull
0037
0038 struct rr_config {
0039     u64 min;
0040     u64 max;
0041     u32 index;
0042     u8 type;
0043 };
0044
0045 struct gaudi2_atypical_bp_blocks {
0046     u32 mm_block_base_addr;
0047     u32 block_size;
0048     u32 glbl_sec_offset;
0049     u32 glbl_sec_length;
0050 };
0051
0052 static const struct gaudi2_atypical_bp_blocks gaudi2_pb_dcr0_sm_objs = {
0053     mmDCORE0_SYNC_MNGR_OBJS_BASE,
0054     128 * 1024,
0055     SM_OBJS_PROT_BITS_OFFS,
0056     640
0057 };
0058
0059 static const u32 gaudi2_pb_sft0[] = {
0060     mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE,
0061     mmSFT0_HBW_RTR_IF0_RTR_H3_BASE,
0062     mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE,
0063     mmSFT0_HBW_RTR_IF0_ADDR_DEC_HBW_BASE,
0064     mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE,
0065     mmSFT0_HBW_RTR_IF1_RTR_H3_BASE,
0066     mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE,
0067     mmSFT0_HBW_RTR_IF1_ADDR_DEC_HBW_BASE,
0068     mmSFT0_LBW_RTR_IF_RTR_CTRL_BASE,
0069     mmSFT0_LBW_RTR_IF_RTR_H3_BASE,
0070     mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE,
0071     mmSFT0_LBW_RTR_IF_ADDR_DEC_HBW_BASE,
0072     mmSFT0_BASE,
0073 };
0074
0075 static const u32 gaudi2_pb_dcr0_hif[] = {
0076     mmDCORE0_HIF0_BASE,
0077 };
0078
0079 static const u32 gaudi2_pb_dcr0_rtr0[] = {
0080     mmDCORE0_RTR0_CTRL_BASE,
0081     mmDCORE0_RTR0_H3_BASE,
0082     mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE,
0083     mmDCORE0_RTR0_ADD_DEC_HBW_BASE,
0084     mmDCORE0_RTR0_BASE,
0085     mmDCORE0_RTR0_DBG_ADDR_BASE,
0086 };
0087
0088 static const u32 gaudi2_pb_dcr0_hmmu0[] = {
0089     mmDCORE0_HMMU0_MMU_BASE,
0090     mmDCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE,
0091     mmDCORE0_HMMU0_SCRAMB_OUT_BASE,
0092     mmDCORE0_HMMU0_STLB_BASE,
0093 };
0094
0095 static const u32 gaudi2_pb_cpu_if[] = {
0096     mmCPU_IF_BASE,
0097 };
0098
0099 static const u32 gaudi2_pb_cpu[] = {
0100     mmCPU_CA53_CFG_BASE,
0101     mmCPU_MSTR_IF_RR_SHRD_HBW_BASE,
0102 };
0103
0104 static const u32 gaudi2_pb_kdma[] = {
0105     mmARC_FARM_KDMA_BASE,
0106     mmARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_BASE,
0107 };
0108
0109 static const u32 gaudi2_pb_pdma0[] = {
0110     mmPDMA0_CORE_BASE,
0111     mmPDMA0_MSTR_IF_RR_SHRD_HBW_BASE,
0112     mmPDMA0_QM_BASE,
0113 };
0114
0115 static const u32 gaudi2_pb_pdma0_arc[] = {
0116     mmPDMA0_QM_ARC_AUX_BASE,
0117 };
0118
0119 static const struct range gaudi2_pb_pdma0_arc_unsecured_regs[] = {
0120     {mmPDMA0_QM_ARC_AUX_RUN_HALT_REQ, mmPDMA0_QM_ARC_AUX_RUN_HALT_ACK},
0121     {mmPDMA0_QM_ARC_AUX_CLUSTER_NUM, mmPDMA0_QM_ARC_AUX_WAKE_UP_EVENT},
0122     {mmPDMA0_QM_ARC_AUX_ARC_RST_REQ, mmPDMA0_QM_ARC_AUX_CID_OFFSET_7},
0123     {mmPDMA0_QM_ARC_AUX_SCRATCHPAD_0, mmPDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
0124     {mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
0125     {mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
0126     {mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
0127     {mmPDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, mmPDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
0128     {mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmPDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
0129 };
0130
0131 static const u32 gaudi2_pb_pdma0_unsecured_regs[] = {
0132     mmPDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION,
0133     mmPDMA0_CORE_CTX_WR_COMP_ADDR_HI,
0134     mmPDMA0_CORE_CTX_WR_COMP_ADDR_LO,
0135     mmPDMA0_CORE_CTX_WR_COMP_WDATA,
0136     mmPDMA0_CORE_CTX_SRC_BASE_LO,
0137     mmPDMA0_CORE_CTX_SRC_BASE_HI,
0138     mmPDMA0_CORE_CTX_DST_BASE_LO,
0139     mmPDMA0_CORE_CTX_DST_BASE_HI,
0140     mmPDMA0_CORE_CTX_SRC_TSIZE_0,
0141     mmPDMA0_CORE_CTX_SRC_TSIZE_1,
0142     mmPDMA0_CORE_CTX_SRC_TSIZE_2,
0143     mmPDMA0_CORE_CTX_SRC_TSIZE_3,
0144     mmPDMA0_CORE_CTX_SRC_TSIZE_4,
0145     mmPDMA0_CORE_CTX_SRC_STRIDE_1,
0146     mmPDMA0_CORE_CTX_SRC_STRIDE_2,
0147     mmPDMA0_CORE_CTX_SRC_STRIDE_3,
0148     mmPDMA0_CORE_CTX_SRC_STRIDE_4,
0149     mmPDMA0_CORE_CTX_SRC_OFFSET_LO,
0150     mmPDMA0_CORE_CTX_SRC_OFFSET_HI,
0151     mmPDMA0_CORE_CTX_DST_TSIZE_0,
0152     mmPDMA0_CORE_CTX_DST_TSIZE_1,
0153     mmPDMA0_CORE_CTX_DST_TSIZE_2,
0154     mmPDMA0_CORE_CTX_DST_TSIZE_3,
0155     mmPDMA0_CORE_CTX_DST_TSIZE_4,
0156     mmPDMA0_CORE_CTX_DST_STRIDE_1,
0157     mmPDMA0_CORE_CTX_DST_STRIDE_2,
0158     mmPDMA0_CORE_CTX_DST_STRIDE_3,
0159     mmPDMA0_CORE_CTX_DST_STRIDE_4,
0160     mmPDMA0_CORE_CTX_DST_OFFSET_LO,
0161     mmPDMA0_CORE_CTX_DST_OFFSET_HI,
0162     mmPDMA0_CORE_CTX_COMMIT,
0163     mmPDMA0_CORE_CTX_CTRL,
0164     mmPDMA0_CORE_CTX_TE_NUMROWS,
0165     mmPDMA0_CORE_CTX_IDX,
0166     mmPDMA0_CORE_CTX_IDX_INC,
0167     mmPDMA0_QM_CQ_CFG0_0,
0168     mmPDMA0_QM_CQ_CFG0_1,
0169     mmPDMA0_QM_CQ_CFG0_2,
0170     mmPDMA0_QM_CQ_CFG0_3,
0171     mmPDMA0_QM_CQ_CFG0_4,
0172     mmPDMA0_QM_CP_FENCE0_RDATA_0,
0173     mmPDMA0_QM_CP_FENCE0_RDATA_1,
0174     mmPDMA0_QM_CP_FENCE0_RDATA_2,
0175     mmPDMA0_QM_CP_FENCE0_RDATA_3,
0176     mmPDMA0_QM_CP_FENCE0_RDATA_4,
0177     mmPDMA0_QM_CP_FENCE1_RDATA_0,
0178     mmPDMA0_QM_CP_FENCE1_RDATA_1,
0179     mmPDMA0_QM_CP_FENCE1_RDATA_2,
0180     mmPDMA0_QM_CP_FENCE1_RDATA_3,
0181     mmPDMA0_QM_CP_FENCE1_RDATA_4,
0182     mmPDMA0_QM_CP_FENCE2_RDATA_0,
0183     mmPDMA0_QM_CP_FENCE2_RDATA_1,
0184     mmPDMA0_QM_CP_FENCE2_RDATA_2,
0185     mmPDMA0_QM_CP_FENCE2_RDATA_3,
0186     mmPDMA0_QM_CP_FENCE2_RDATA_4,
0187     mmPDMA0_QM_CP_FENCE3_RDATA_0,
0188     mmPDMA0_QM_CP_FENCE3_RDATA_1,
0189     mmPDMA0_QM_CP_FENCE3_RDATA_2,
0190     mmPDMA0_QM_CP_FENCE3_RDATA_3,
0191     mmPDMA0_QM_CP_FENCE3_RDATA_4,
0192     mmPDMA0_QM_CP_FENCE0_CNT_0,
0193     mmPDMA0_QM_CP_FENCE0_CNT_1,
0194     mmPDMA0_QM_CP_FENCE0_CNT_2,
0195     mmPDMA0_QM_CP_FENCE0_CNT_3,
0196     mmPDMA0_QM_CP_FENCE0_CNT_4,
0197     mmPDMA0_QM_CP_FENCE1_CNT_0,
0198     mmPDMA0_QM_CP_FENCE1_CNT_1,
0199     mmPDMA0_QM_CP_FENCE1_CNT_2,
0200     mmPDMA0_QM_CP_FENCE1_CNT_3,
0201     mmPDMA0_QM_CP_FENCE1_CNT_4,
0202     mmPDMA0_QM_CP_FENCE2_CNT_0,
0203     mmPDMA0_QM_CP_FENCE2_CNT_1,
0204     mmPDMA0_QM_CP_FENCE2_CNT_2,
0205     mmPDMA0_QM_CP_FENCE2_CNT_3,
0206     mmPDMA0_QM_CP_FENCE2_CNT_4,
0207     mmPDMA0_QM_CP_FENCE3_CNT_0,
0208     mmPDMA0_QM_CP_FENCE3_CNT_1,
0209     mmPDMA0_QM_CP_FENCE3_CNT_2,
0210     mmPDMA0_QM_CP_FENCE3_CNT_3,
0211     mmPDMA0_QM_CP_FENCE3_CNT_4,
0212     mmPDMA0_QM_CQ_PTR_LO_0,
0213     mmPDMA0_QM_CQ_PTR_HI_0,
0214     mmPDMA0_QM_CQ_TSIZE_0,
0215     mmPDMA0_QM_CQ_CTL_0,
0216     mmPDMA0_QM_CQ_PTR_LO_1,
0217     mmPDMA0_QM_CQ_PTR_HI_1,
0218     mmPDMA0_QM_CQ_TSIZE_1,
0219     mmPDMA0_QM_CQ_CTL_1,
0220     mmPDMA0_QM_CQ_PTR_LO_2,
0221     mmPDMA0_QM_CQ_PTR_HI_2,
0222     mmPDMA0_QM_CQ_TSIZE_2,
0223     mmPDMA0_QM_CQ_CTL_2,
0224     mmPDMA0_QM_CQ_PTR_LO_3,
0225     mmPDMA0_QM_CQ_PTR_HI_3,
0226     mmPDMA0_QM_CQ_TSIZE_3,
0227     mmPDMA0_QM_CQ_CTL_3,
0228     mmPDMA0_QM_CQ_PTR_LO_4,
0229     mmPDMA0_QM_CQ_PTR_HI_4,
0230     mmPDMA0_QM_CQ_TSIZE_4,
0231     mmPDMA0_QM_CQ_CTL_4,
0232     mmPDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE,
0233     mmPDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
0234     mmPDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE,
0235     mmPDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
0236     mmPDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE,
0237     mmPDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
0238     mmPDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE,
0239     mmPDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
0240     mmPDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE,
0241     mmPDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
0242     mmPDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE,
0243     mmPDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
0244     mmPDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE,
0245     mmPDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
0246     mmPDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE,
0247     mmPDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
0248     mmPDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE,
0249     mmPDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
0250     mmPDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE,
0251     mmPDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
0252     mmPDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE,
0253     mmPDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
0254     mmPDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE,
0255     mmPDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
0256     mmPDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE,
0257     mmPDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
0258     mmPDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE,
0259     mmPDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
0260     mmPDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE,
0261     mmPDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
0262     mmPDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE,
0263     mmPDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
0264     mmPDMA0_QM_ARC_CQ_PTR_LO,
0265     mmPDMA0_QM_ARC_CQ_PTR_LO_STS,
0266     mmPDMA0_QM_ARC_CQ_PTR_HI,
0267     mmPDMA0_QM_ARC_CQ_PTR_HI_STS,
0268     mmPDMA0_QM_ARB_CFG_0,
0269     mmPDMA0_QM_ARB_MST_QUIET_PER,
0270     mmPDMA0_QM_ARB_CHOICE_Q_PUSH,
0271     mmPDMA0_QM_ARB_WRR_WEIGHT_0,
0272     mmPDMA0_QM_ARB_WRR_WEIGHT_1,
0273     mmPDMA0_QM_ARB_WRR_WEIGHT_2,
0274     mmPDMA0_QM_ARB_WRR_WEIGHT_3,
0275     mmPDMA0_QM_ARB_BASE_LO,
0276     mmPDMA0_QM_ARB_BASE_HI,
0277     mmPDMA0_QM_ARB_MST_SLAVE_EN,
0278     mmPDMA0_QM_ARB_MST_SLAVE_EN_1,
0279     mmPDMA0_QM_ARB_MST_CRED_INC,
0280     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0,
0281     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1,
0282     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2,
0283     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3,
0284     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4,
0285     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5,
0286     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6,
0287     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7,
0288     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8,
0289     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9,
0290     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10,
0291     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11,
0292     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12,
0293     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13,
0294     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14,
0295     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15,
0296     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16,
0297     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17,
0298     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18,
0299     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19,
0300     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20,
0301     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21,
0302     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22,
0303     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23,
0304     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24,
0305     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25,
0306     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26,
0307     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27,
0308     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28,
0309     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29,
0310     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30,
0311     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31,
0312     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32,
0313     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33,
0314     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34,
0315     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35,
0316     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36,
0317     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37,
0318     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38,
0319     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39,
0320     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40,
0321     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41,
0322     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42,
0323     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43,
0324     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44,
0325     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45,
0326     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46,
0327     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47,
0328     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48,
0329     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49,
0330     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50,
0331     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51,
0332     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52,
0333     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53,
0334     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54,
0335     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55,
0336     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56,
0337     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57,
0338     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58,
0339     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59,
0340     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60,
0341     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61,
0342     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62,
0343     mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63,
0344     mmPDMA0_QM_ARB_SLV_ID,
0345     mmPDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST,
0346     mmPDMA0_QM_ARC_CQ_CFG0,
0347     mmPDMA0_QM_CQ_IFIFO_CI_0,
0348     mmPDMA0_QM_CQ_IFIFO_CI_1,
0349     mmPDMA0_QM_CQ_IFIFO_CI_2,
0350     mmPDMA0_QM_CQ_IFIFO_CI_3,
0351     mmPDMA0_QM_CQ_IFIFO_CI_4,
0352     mmPDMA0_QM_ARC_CQ_IFIFO_CI,
0353     mmPDMA0_QM_CQ_CTL_CI_0,
0354     mmPDMA0_QM_CQ_CTL_CI_1,
0355     mmPDMA0_QM_CQ_CTL_CI_2,
0356     mmPDMA0_QM_CQ_CTL_CI_3,
0357     mmPDMA0_QM_CQ_CTL_CI_4,
0358     mmPDMA0_QM_ARC_CQ_CTL_CI,
0359     mmPDMA0_QM_ARC_CQ_TSIZE,
0360     mmPDMA0_QM_ARC_CQ_CTL,
0361     mmPDMA0_QM_CP_SWITCH_WD_SET,
0362     mmPDMA0_QM_CP_EXT_SWITCH,
0363     mmPDMA0_QM_CP_PRED_0,
0364     mmPDMA0_QM_CP_PRED_1,
0365     mmPDMA0_QM_CP_PRED_2,
0366     mmPDMA0_QM_CP_PRED_3,
0367     mmPDMA0_QM_CP_PRED_4,
0368     mmPDMA0_QM_CP_PRED_UPEN_0,
0369     mmPDMA0_QM_CP_PRED_UPEN_1,
0370     mmPDMA0_QM_CP_PRED_UPEN_2,
0371     mmPDMA0_QM_CP_PRED_UPEN_3,
0372     mmPDMA0_QM_CP_PRED_UPEN_4,
0373     mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_0,
0374     mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_1,
0375     mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_2,
0376     mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_3,
0377     mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_4,
0378     mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_0,
0379     mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_1,
0380     mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_2,
0381     mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_3,
0382     mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_4,
0383     mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_0,
0384     mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_1,
0385     mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_2,
0386     mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_3,
0387     mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_4,
0388     mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_0,
0389     mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_1,
0390     mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_2,
0391     mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_3,
0392     mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_4,
0393     mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_0,
0394     mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_1,
0395     mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_2,
0396     mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_3,
0397     mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_4,
0398     mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_0,
0399     mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_1,
0400     mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_2,
0401     mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_3,
0402     mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_4,
0403     mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_0,
0404     mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_1,
0405     mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_2,
0406     mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_3,
0407     mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_4,
0408     mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_0,
0409     mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_1,
0410     mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_2,
0411     mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_3,
0412     mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_4,
0413     mmPDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
0414     mmPDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO,
0415     mmPDMA0_QM_CQ_IFIFO_MSG_BASE_LO,
0416     mmPDMA0_QM_CQ_CTL_MSG_BASE_LO
0417 };
0418
0419 static const u32 gaudi2_pb_dcr0_edma0[] = {
0420     mmDCORE0_EDMA0_CORE_BASE,
0421     mmDCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE,
0422     mmDCORE0_EDMA0_QM_BASE,
0423 };
0424
0425 static const u32 gaudi2_pb_dcr0_edma0_arc[] = {
0426     mmDCORE0_EDMA0_QM_ARC_AUX_BASE,
0427 };
0428
0429 static const struct range gaudi2_pb_dcr0_edma0_arc_unsecured_regs[] = {
0430     {mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_ACK},
0431     {mmDCORE0_EDMA0_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_EDMA0_QM_ARC_AUX_WAKE_UP_EVENT},
0432     {mmDCORE0_EDMA0_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_7},
0433     {mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_EDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
0434     {mmDCORE0_EDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN,
0435         mmDCORE0_EDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
0436     {mmDCORE0_EDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN,
0437         mmDCORE0_EDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
0438     {mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0,
0439         mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
0440     {mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT,
0441         mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
0442     {mmDCORE0_EDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT,
0443         mmDCORE0_EDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
0444 };
0445
0446 static const u32 gaudi2_pb_dcr0_edma0_unsecured_regs[] = {
0447     mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION,
0448     mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_HI,
0449     mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_LO,
0450     mmDCORE0_EDMA0_CORE_CTX_WR_COMP_WDATA,
0451     mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_LO,
0452     mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_HI,
0453     mmDCORE0_EDMA0_CORE_CTX_DST_BASE_LO,
0454     mmDCORE0_EDMA0_CORE_CTX_DST_BASE_HI,
0455     mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_0,
0456     mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_1,
0457     mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_2,
0458     mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_3,
0459     mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_4,
0460     mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_1,
0461     mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_2,
0462     mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_3,
0463     mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_4,
0464     mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_LO,
0465     mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_HI,
0466     mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_0,
0467     mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_1,
0468     mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_2,
0469     mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_3,
0470     mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_4,
0471     mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_1,
0472     mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_2,
0473     mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_3,
0474     mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_4,
0475     mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_LO,
0476     mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_HI,
0477     mmDCORE0_EDMA0_CORE_CTX_COMMIT,
0478     mmDCORE0_EDMA0_CORE_CTX_CTRL,
0479     mmDCORE0_EDMA0_CORE_CTX_TE_NUMROWS,
0480     mmDCORE0_EDMA0_CORE_CTX_IDX,
0481     mmDCORE0_EDMA0_CORE_CTX_IDX_INC,
0482     mmDCORE0_EDMA0_QM_CQ_CFG0_0,
0483     mmDCORE0_EDMA0_QM_CQ_CFG0_1,
0484     mmDCORE0_EDMA0_QM_CQ_CFG0_2,
0485     mmDCORE0_EDMA0_QM_CQ_CFG0_3,
0486     mmDCORE0_EDMA0_QM_CQ_CFG0_4,
0487     mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_0,
0488     mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_1,
0489     mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_2,
0490     mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_3,
0491     mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_4,
0492     mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_0,
0493     mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_1,
0494     mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_2,
0495     mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_3,
0496     mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_4,
0497     mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_0,
0498     mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_1,
0499     mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_2,
0500     mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_3,
0501     mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_4,
0502     mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_0,
0503     mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_1,
0504     mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_2,
0505     mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_3,
0506     mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_4,
0507     mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_0,
0508     mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_1,
0509     mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_2,
0510     mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_3,
0511     mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_4,
0512     mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_0,
0513     mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_1,
0514     mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_2,
0515     mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_3,
0516     mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_4,
0517     mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_0,
0518     mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_1,
0519     mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_2,
0520     mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_3,
0521     mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_4,
0522     mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_0,
0523     mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_1,
0524     mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_2,
0525     mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_3,
0526     mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_4,
0527     mmDCORE0_EDMA0_QM_CQ_PTR_LO_0,
0528     mmDCORE0_EDMA0_QM_CQ_PTR_HI_0,
0529     mmDCORE0_EDMA0_QM_CQ_TSIZE_0,
0530     mmDCORE0_EDMA0_QM_CQ_CTL_0,
0531     mmDCORE0_EDMA0_QM_CQ_PTR_LO_1,
0532     mmDCORE0_EDMA0_QM_CQ_PTR_HI_1,
0533     mmDCORE0_EDMA0_QM_CQ_TSIZE_1,
0534     mmDCORE0_EDMA0_QM_CQ_CTL_1,
0535     mmDCORE0_EDMA0_QM_CQ_PTR_LO_2,
0536     mmDCORE0_EDMA0_QM_CQ_PTR_HI_2,
0537     mmDCORE0_EDMA0_QM_CQ_TSIZE_2,
0538     mmDCORE0_EDMA0_QM_CQ_CTL_2,
0539     mmDCORE0_EDMA0_QM_CQ_PTR_LO_3,
0540     mmDCORE0_EDMA0_QM_CQ_PTR_HI_3,
0541     mmDCORE0_EDMA0_QM_CQ_TSIZE_3,
0542     mmDCORE0_EDMA0_QM_CQ_CTL_3,
0543     mmDCORE0_EDMA0_QM_CQ_PTR_LO_4,
0544     mmDCORE0_EDMA0_QM_CQ_PTR_HI_4,
0545     mmDCORE0_EDMA0_QM_CQ_TSIZE_4,
0546     mmDCORE0_EDMA0_QM_CQ_CTL_4,
0547     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE,
0548     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
0549     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE,
0550     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
0551     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE,
0552     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
0553     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE,
0554     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
0555     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE,
0556     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
0557     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE,
0558     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
0559     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE,
0560     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
0561     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE,
0562     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
0563     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE,
0564     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
0565     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE,
0566     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
0567     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE,
0568     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
0569     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE,
0570     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
0571     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE,
0572     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
0573     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE,
0574     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
0575     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE,
0576     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
0577     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE,
0578     mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
0579     mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO,
0580     mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS,
0581     mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI,
0582     mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS,
0583     mmDCORE0_EDMA0_QM_ARB_CFG_0,
0584     mmDCORE0_EDMA0_QM_ARB_MST_QUIET_PER,
0585     mmDCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH,
0586     mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_0,
0587     mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_1,
0588     mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_2,
0589     mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_3,
0590     mmDCORE0_EDMA0_QM_ARB_BASE_LO,
0591     mmDCORE0_EDMA0_QM_ARB_BASE_HI,
0592     mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN,
0593     mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1,
0594     mmDCORE0_EDMA0_QM_ARB_MST_CRED_INC,
0595     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0,
0596     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1,
0597     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2,
0598     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3,
0599     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4,
0600     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5,
0601     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6,
0602     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7,
0603     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8,
0604     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9,
0605     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10,
0606     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11,
0607     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12,
0608     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13,
0609     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14,
0610     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15,
0611     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16,
0612     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17,
0613     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18,
0614     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19,
0615     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20,
0616     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21,
0617     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22,
0618     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23,
0619     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24,
0620     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25,
0621     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26,
0622     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27,
0623     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28,
0624     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29,
0625     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30,
0626     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31,
0627     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32,
0628     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33,
0629     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34,
0630     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35,
0631     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36,
0632     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37,
0633     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38,
0634     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39,
0635     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40,
0636     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41,
0637     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42,
0638     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43,
0639     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44,
0640     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45,
0641     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46,
0642     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47,
0643     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48,
0644     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49,
0645     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50,
0646     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51,
0647     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52,
0648     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53,
0649     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54,
0650     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55,
0651     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56,
0652     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57,
0653     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58,
0654     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59,
0655     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60,
0656     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61,
0657     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62,
0658     mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63,
0659     mmDCORE0_EDMA0_QM_ARB_SLV_ID,
0660     mmDCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST,
0661     mmDCORE0_EDMA0_QM_ARC_CQ_CFG0,
0662     mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_0,
0663     mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_1,
0664     mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_2,
0665     mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_3,
0666     mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_4,
0667     mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI,
0668     mmDCORE0_EDMA0_QM_CQ_CTL_CI_0,
0669     mmDCORE0_EDMA0_QM_CQ_CTL_CI_1,
0670     mmDCORE0_EDMA0_QM_CQ_CTL_CI_2,
0671     mmDCORE0_EDMA0_QM_CQ_CTL_CI_3,
0672     mmDCORE0_EDMA0_QM_CQ_CTL_CI_4,
0673     mmDCORE0_EDMA0_QM_ARC_CQ_CTL_CI,
0674     mmDCORE0_EDMA0_QM_ARC_CQ_TSIZE,
0675     mmDCORE0_EDMA0_QM_ARC_CQ_CTL,
0676     mmDCORE0_EDMA0_QM_CP_SWITCH_WD_SET,
0677     mmDCORE0_EDMA0_QM_CP_EXT_SWITCH,
0678     mmDCORE0_EDMA0_QM_CP_PRED_0,
0679     mmDCORE0_EDMA0_QM_CP_PRED_1,
0680     mmDCORE0_EDMA0_QM_CP_PRED_2,
0681     mmDCORE0_EDMA0_QM_CP_PRED_3,
0682     mmDCORE0_EDMA0_QM_CP_PRED_4,
0683     mmDCORE0_EDMA0_QM_CP_PRED_UPEN_0,
0684     mmDCORE0_EDMA0_QM_CP_PRED_UPEN_1,
0685     mmDCORE0_EDMA0_QM_CP_PRED_UPEN_2,
0686     mmDCORE0_EDMA0_QM_CP_PRED_UPEN_3,
0687     mmDCORE0_EDMA0_QM_CP_PRED_UPEN_4,
0688     mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_0,
0689     mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_1,
0690     mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_2,
0691     mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_3,
0692     mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_4,
0693     mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_0,
0694     mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_1,
0695     mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_2,
0696     mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_3,
0697     mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_4,
0698     mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_0,
0699     mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_1,
0700     mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_2,
0701     mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_3,
0702     mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_4,
0703     mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_0,
0704     mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_1,
0705     mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_2,
0706     mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_3,
0707     mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_4,
0708     mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_0,
0709     mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_1,
0710     mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_2,
0711     mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_3,
0712     mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_4,
0713     mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_0,
0714     mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_1,
0715     mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_2,
0716     mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_3,
0717     mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_4,
0718     mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_0,
0719     mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_1,
0720     mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_2,
0721     mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_3,
0722     mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_4,
0723     mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_0,
0724     mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_1,
0725     mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_2,
0726     mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_3,
0727     mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_4,
0728     mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
0729     mmDCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO,
0730     mmDCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO,
0731     mmDCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO
0732 };
0733
0734 static const u32 gaudi2_pb_dcr0_mme_sbte[] = {
0735     mmDCORE0_MME_SBTE0_BASE,
0736     mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE,
0737 };
0738
0739 static const u32 gaudi2_pb_dcr0_mme_qm[] = {
0740     mmDCORE0_MME_QM_BASE,
0741 };
0742
0743 static const u32 gaudi2_pb_dcr0_mme_eng[] = {
0744     mmDCORE0_MME_ACC_BASE,
0745     mmDCORE0_MME_CTRL_HI_BASE,
0746     mmDCORE0_MME_CTRL_LO_BASE,
0747     mmDCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE,
0748     mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE,
0749     mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE,
0750 };
0751
0752 static const u32 gaudi2_pb_dcr0_mme_arc[] = {
0753     mmDCORE0_MME_QM_ARC_AUX_BASE,
0754     mmDCORE0_MME_QM_ARC_DUP_ENG_BASE,
0755 };
0756
0757 static const struct range gaudi2_pb_dcr0_mme_arc_unsecured_regs[] = {
0758     {mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_ACK},
0759     {mmDCORE0_MME_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_MME_QM_ARC_AUX_WAKE_UP_EVENT},
0760     {mmDCORE0_MME_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_7},
0761     {mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
0762     {mmDCORE0_MME_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmDCORE0_MME_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
0763     {mmDCORE0_MME_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmDCORE0_MME_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
0764     {mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0,
0765         mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
0766     {mmDCORE0_MME_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT,
0767         mmDCORE0_MME_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
0768     {mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT,
0769         mmDCORE0_MME_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
0770     {mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_0,
0771         mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_63},
0772     {mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_STRONG_ORDER,
0773         mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_LB_OVRD},
0774 };
0775
0776 static const u32 gaudi2_pb_dcr0_mme_qm_unsecured_regs[] = {
0777     mmDCORE0_MME_QM_CQ_CFG0_0,
0778     mmDCORE0_MME_QM_CQ_CFG0_1,
0779     mmDCORE0_MME_QM_CQ_CFG0_2,
0780     mmDCORE0_MME_QM_CQ_CFG0_3,
0781     mmDCORE0_MME_QM_CQ_CFG0_4,
0782     mmDCORE0_MME_QM_CP_FENCE0_RDATA_0,
0783     mmDCORE0_MME_QM_CP_FENCE0_RDATA_1,
0784     mmDCORE0_MME_QM_CP_FENCE0_RDATA_2,
0785     mmDCORE0_MME_QM_CP_FENCE0_RDATA_3,
0786     mmDCORE0_MME_QM_CP_FENCE0_RDATA_4,
0787     mmDCORE0_MME_QM_CP_FENCE1_RDATA_0,
0788     mmDCORE0_MME_QM_CP_FENCE1_RDATA_1,
0789     mmDCORE0_MME_QM_CP_FENCE1_RDATA_2,
0790     mmDCORE0_MME_QM_CP_FENCE1_RDATA_3,
0791     mmDCORE0_MME_QM_CP_FENCE1_RDATA_4,
0792     mmDCORE0_MME_QM_CP_FENCE2_RDATA_0,
0793     mmDCORE0_MME_QM_CP_FENCE2_RDATA_1,
0794     mmDCORE0_MME_QM_CP_FENCE2_RDATA_2,
0795     mmDCORE0_MME_QM_CP_FENCE2_RDATA_3,
0796     mmDCORE0_MME_QM_CP_FENCE2_RDATA_4,
0797     mmDCORE0_MME_QM_CP_FENCE3_RDATA_0,
0798     mmDCORE0_MME_QM_CP_FENCE3_RDATA_1,
0799     mmDCORE0_MME_QM_CP_FENCE3_RDATA_2,
0800     mmDCORE0_MME_QM_CP_FENCE3_RDATA_3,
0801     mmDCORE0_MME_QM_CP_FENCE3_RDATA_4,
0802     mmDCORE0_MME_QM_CP_FENCE0_CNT_0,
0803     mmDCORE0_MME_QM_CP_FENCE0_CNT_1,
0804     mmDCORE0_MME_QM_CP_FENCE0_CNT_2,
0805     mmDCORE0_MME_QM_CP_FENCE0_CNT_3,
0806     mmDCORE0_MME_QM_CP_FENCE0_CNT_4,
0807     mmDCORE0_MME_QM_CP_FENCE1_CNT_0,
0808     mmDCORE0_MME_QM_CP_FENCE1_CNT_1,
0809     mmDCORE0_MME_QM_CP_FENCE1_CNT_2,
0810     mmDCORE0_MME_QM_CP_FENCE1_CNT_3,
0811     mmDCORE0_MME_QM_CP_FENCE1_CNT_4,
0812     mmDCORE0_MME_QM_CP_FENCE2_CNT_0,
0813     mmDCORE0_MME_QM_CP_FENCE2_CNT_1,
0814     mmDCORE0_MME_QM_CP_FENCE2_CNT_2,
0815     mmDCORE0_MME_QM_CP_FENCE2_CNT_3,
0816     mmDCORE0_MME_QM_CP_FENCE2_CNT_4,
0817     mmDCORE0_MME_QM_CP_FENCE3_CNT_0,
0818     mmDCORE0_MME_QM_CP_FENCE3_CNT_1,
0819     mmDCORE0_MME_QM_CP_FENCE3_CNT_2,
0820     mmDCORE0_MME_QM_CP_FENCE3_CNT_3,
0821     mmDCORE0_MME_QM_CP_FENCE3_CNT_4,
0822     mmDCORE0_MME_QM_CQ_PTR_LO_0,
0823     mmDCORE0_MME_QM_CQ_PTR_HI_0,
0824     mmDCORE0_MME_QM_CQ_TSIZE_0,
0825     mmDCORE0_MME_QM_CQ_CTL_0,
0826     mmDCORE0_MME_QM_CQ_PTR_LO_1,
0827     mmDCORE0_MME_QM_CQ_PTR_HI_1,
0828     mmDCORE0_MME_QM_CQ_TSIZE_1,
0829     mmDCORE0_MME_QM_CQ_CTL_1,
0830     mmDCORE0_MME_QM_CQ_PTR_LO_2,
0831     mmDCORE0_MME_QM_CQ_PTR_HI_2,
0832     mmDCORE0_MME_QM_CQ_TSIZE_2,
0833     mmDCORE0_MME_QM_CQ_CTL_2,
0834     mmDCORE0_MME_QM_CQ_PTR_LO_3,
0835     mmDCORE0_MME_QM_CQ_PTR_HI_3,
0836     mmDCORE0_MME_QM_CQ_TSIZE_3,
0837     mmDCORE0_MME_QM_CQ_CTL_3,
0838     mmDCORE0_MME_QM_CQ_PTR_LO_4,
0839     mmDCORE0_MME_QM_CQ_PTR_HI_4,
0840     mmDCORE0_MME_QM_CQ_TSIZE_4,
0841     mmDCORE0_MME_QM_CQ_CTL_4,
0842     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE,
0843     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
0844     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE,
0845     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
0846     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE,
0847     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
0848     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE,
0849     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
0850     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE,
0851     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
0852     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE,
0853     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
0854     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE,
0855     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
0856     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE,
0857     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
0858     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE,
0859     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
0860     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE,
0861     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
0862     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE,
0863     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
0864     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE,
0865     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
0866     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE,
0867     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
0868     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE,
0869     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
0870     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE,
0871     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
0872     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE,
0873     mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
0874     mmDCORE0_MME_QM_ARC_CQ_PTR_LO,
0875     mmDCORE0_MME_QM_ARC_CQ_PTR_LO_STS,
0876     mmDCORE0_MME_QM_ARC_CQ_PTR_HI,
0877     mmDCORE0_MME_QM_ARC_CQ_PTR_HI_STS,
0878     mmDCORE0_MME_QM_ARB_CFG_0,
0879     mmDCORE0_MME_QM_ARB_MST_QUIET_PER,
0880     mmDCORE0_MME_QM_ARB_CHOICE_Q_PUSH,
0881     mmDCORE0_MME_QM_ARB_WRR_WEIGHT_0,
0882     mmDCORE0_MME_QM_ARB_WRR_WEIGHT_1,
0883     mmDCORE0_MME_QM_ARB_WRR_WEIGHT_2,
0884     mmDCORE0_MME_QM_ARB_WRR_WEIGHT_3,
0885     mmDCORE0_MME_QM_ARB_BASE_LO,
0886     mmDCORE0_MME_QM_ARB_BASE_HI,
0887     mmDCORE0_MME_QM_ARB_MST_SLAVE_EN,
0888     mmDCORE0_MME_QM_ARB_MST_SLAVE_EN_1,
0889     mmDCORE0_MME_QM_ARB_MST_CRED_INC,
0890     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_0,
0891     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_1,
0892     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_2,
0893     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_3,
0894     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_4,
0895     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_5,
0896     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_6,
0897     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_7,
0898     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_8,
0899     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_9,
0900     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_10,
0901     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_11,
0902     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_12,
0903     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_13,
0904     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_14,
0905     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_15,
0906     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_16,
0907     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_17,
0908     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_18,
0909     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_19,
0910     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_20,
0911     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_21,
0912     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_22,
0913     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_23,
0914     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_24,
0915     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_25,
0916     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_26,
0917     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_27,
0918     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_28,
0919     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_29,
0920     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_30,
0921     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_31,
0922     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_32,
0923     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_33,
0924     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_34,
0925     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_35,
0926     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_36,
0927     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_37,
0928     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_38,
0929     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_39,
0930     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_40,
0931     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_41,
0932     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_42,
0933     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_43,
0934     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_44,
0935     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_45,
0936     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_46,
0937     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_47,
0938     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_48,
0939     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_49,
0940     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_50,
0941     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_51,
0942     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_52,
0943     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_53,
0944     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_54,
0945     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_55,
0946     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_56,
0947     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_57,
0948     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_58,
0949     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_59,
0950     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_60,
0951     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_61,
0952     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_62,
0953     mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_63,
0954     mmDCORE0_MME_QM_ARB_SLV_ID,
0955     mmDCORE0_MME_QM_ARB_SLV_MASTER_INC_CRED_OFST,
0956     mmDCORE0_MME_QM_ARC_CQ_CFG0,
0957     mmDCORE0_MME_QM_CQ_IFIFO_CI_0,
0958     mmDCORE0_MME_QM_CQ_IFIFO_CI_1,
0959     mmDCORE0_MME_QM_CQ_IFIFO_CI_2,
0960     mmDCORE0_MME_QM_CQ_IFIFO_CI_3,
0961     mmDCORE0_MME_QM_CQ_IFIFO_CI_4,
0962     mmDCORE0_MME_QM_ARC_CQ_IFIFO_CI,
0963     mmDCORE0_MME_QM_CQ_CTL_CI_0,
0964     mmDCORE0_MME_QM_CQ_CTL_CI_1,
0965     mmDCORE0_MME_QM_CQ_CTL_CI_2,
0966     mmDCORE0_MME_QM_CQ_CTL_CI_3,
0967     mmDCORE0_MME_QM_CQ_CTL_CI_4,
0968     mmDCORE0_MME_QM_ARC_CQ_CTL_CI,
0969     mmDCORE0_MME_QM_ARC_CQ_TSIZE,
0970     mmDCORE0_MME_QM_ARC_CQ_CTL,
0971     mmDCORE0_MME_QM_CP_SWITCH_WD_SET,
0972     mmDCORE0_MME_QM_CP_EXT_SWITCH,
0973     mmDCORE0_MME_QM_CP_PRED_0,
0974     mmDCORE0_MME_QM_CP_PRED_1,
0975     mmDCORE0_MME_QM_CP_PRED_2,
0976     mmDCORE0_MME_QM_CP_PRED_3,
0977     mmDCORE0_MME_QM_CP_PRED_4,
0978     mmDCORE0_MME_QM_CP_PRED_UPEN_0,
0979     mmDCORE0_MME_QM_CP_PRED_UPEN_1,
0980     mmDCORE0_MME_QM_CP_PRED_UPEN_2,
0981     mmDCORE0_MME_QM_CP_PRED_UPEN_3,
0982     mmDCORE0_MME_QM_CP_PRED_UPEN_4,
0983     mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_0,
0984     mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_1,
0985     mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_2,
0986     mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_3,
0987     mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_4,
0988     mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_0,
0989     mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_1,
0990     mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_2,
0991     mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_3,
0992     mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_4,
0993     mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_0,
0994     mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_1,
0995     mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_2,
0996     mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_3,
0997     mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_4,
0998     mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_0,
0999     mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_1,
1000     mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_2,
1001     mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_3,
1002     mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_4,
1003     mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_0,
1004     mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_1,
1005     mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_2,
1006     mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_3,
1007     mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_4,
1008     mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_0,
1009     mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_1,
1010     mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_2,
1011     mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_3,
1012     mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_4,
1013     mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_0,
1014     mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_1,
1015     mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_2,
1016     mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_3,
1017     mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_4,
1018     mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_0,
1019     mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_1,
1020     mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_2,
1021     mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_3,
1022     mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_4,
1023     mmDCORE0_MME_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
1024     mmDCORE0_MME_QM_ARC_CQ_CTL_MSG_BASE_LO,
1025     mmDCORE0_MME_QM_CQ_IFIFO_MSG_BASE_LO,
1026     mmDCORE0_MME_QM_CQ_CTL_MSG_BASE_LO
1027 };
1028
1029 static const u32 gaudi2_pb_dcr0_mme_eng_unsecured_regs[] = {
1030     mmDCORE0_MME_CTRL_LO_CMD,
1031     mmDCORE0_MME_CTRL_LO_AGU,
1032     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_0,
1033     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_1,
1034     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_2,
1035     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_3,
1036     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_4,
1037     mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_0,
1038     mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_1,
1039     mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_2,
1040     mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_3,
1041     mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_4,
1042     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_LOW,
1043     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_HIGH,
1044     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_LOW,
1045     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_HIGH,
1046     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_MASTER,
1047     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_SLAVE,
1048     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_KERNEL_SIZE_MINUS_1,
1049     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_LOW,
1050     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_HIGH,
1051     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_OUTER_LOOP,
1052     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_NUM_ITERATIONS_MINUS_1,
1053     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SB_REPEAT,
1054     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_FP8_BIAS,
1055     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_RATE_LIMITER,
1056     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_USER_DATA,
1057     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_IN,
1058     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_OUT,
1059     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PCU,
1060     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ0_ADDR,
1061     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ1_ADDR,
1062     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_POWER_LOOP,
1063     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_MASTER,
1064     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_MASTER,
1065     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_MASTER,
1066     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_MASTER,
1067     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_SLAVE,
1068     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_SLAVE,
1069     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_SLAVE,
1070     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_SLAVE,
1071     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_WKL_ID,
1072     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_0,
1073     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_1,
1074     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_2,
1075     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_3,
1076     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_4,
1077     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_0,
1078     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_1,
1079     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_2,
1080     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_3,
1081     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_4,
1082     mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_0,
1083     mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_1,
1084     mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_2,
1085     mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_3,
1086     mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_4,
1087     mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_0,
1088     mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_1,
1089     mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_2,
1090     mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_3,
1091     mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_4,
1092     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_0,
1093     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_1,
1094     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_2,
1095     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_3,
1096     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_4,
1097     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_0,
1098     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_1,
1099     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_2,
1100     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_3,
1101     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_4,
1102     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_0,
1103     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_1,
1104     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_2,
1105     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_3,
1106     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_4,
1107     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_0,
1108     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_1,
1109     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_2,
1110     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_3,
1111     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_4,
1112     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_0,
1113     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_1,
1114     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_2,
1115     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_3,
1116     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_0,
1117     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_1,
1118     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_2,
1119     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_3,
1120     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_0,
1121     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_1,
1122     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_2,
1123     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_3,
1124     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_0,
1125     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_1,
1126     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_2,
1127     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_3,
1128     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_4,
1129     mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_LOW,
1130     mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_HIGH,
1131     mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_LOW,
1132     mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_HIGH,
1133     mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_LOW,
1134     mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_HIGH,
1135     mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_LOW,
1136     mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_HIGH,
1137     mmDCORE0_MME_CTRL_LO_ARCH_STATUS,
1138     mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0,
1139     mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0,
1140     mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0,
1141     mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1,
1142     mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1,
1143     mmDCORE0_MME_CTRL_LO_ARCH_A_SS,
1144     mmDCORE0_MME_CTRL_LO_ARCH_B_SS,
1145     mmDCORE0_MME_CTRL_LO_ARCH_COUT_SS,
1146     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_0,
1147     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_1,
1148     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_2,
1149     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_3,
1150     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_4,
1151     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_0,
1152     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_1,
1153     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_2,
1154     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_3,
1155     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_4,
1156     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_0,
1157     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_1,
1158     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_2,
1159     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_3,
1160     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_4,
1161     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_0,
1162     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_1,
1163     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_2,
1164     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_3,
1165     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_4,
1166     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_0,
1167     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_1,
1168     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_2,
1169     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_3,
1170     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_0,
1171     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_1,
1172     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_2,
1173     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_3,
1174     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_0,
1175     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_1,
1176     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_2,
1177     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_3,
1178     mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_BASE,
1179     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE,
1180     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_BASE,
1181     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_BASE,
1182     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE,
1183     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE,
1184     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE,
1185     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE,
1186     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE,
1187     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE,
1188     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE,
1189     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE,
1190     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE,
1191     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE,
1192     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE,
1193     mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE,
1194     mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE,
1195     mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE,
1196     mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE,
1197     mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE,
1198     mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_0,
1199     mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_1,
1200     mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_2,
1201     mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_3,
1202     mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_4,
1203     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_0,
1204     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_1,
1205     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_2,
1206     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_3,
1207     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_4,
1208     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_0,
1209     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_1,
1210     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_2,
1211     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_3,
1212     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_4,
1213     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_0,
1214     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_1,
1215     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_2,
1216     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_3,
1217     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_4,
1218     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_0,
1219     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_1,
1220     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_2,
1221     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_3,
1222     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_0,
1223     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_1,
1224     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_2,
1225     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_3,
1226     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_0,
1227     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_1,
1228     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_2,
1229     mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_3,
1230     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_0,
1231     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_1,
1232     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_2,
1233     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_3,
1234     mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_4,
1235     mmDCORE0_MME_ACC_AP_LFSR_POLY,
1236     mmDCORE0_MME_ACC_AP_LFSR_SEED_WDATA,
1237     mmDCORE0_MME_ACC_AP_LFSR_SEED_SEL,
1238     mmDCORE0_MME_ACC_AP_LFSR_SEED_RDATA,
1239     mmDCORE0_MME_ACC_AP_LFSR_CLOSE_CGATE_DLY,
1240     mmDCORE0_MME_ACC_WBC_SRC_BP,
1241 };
1242
1243 static const u32 gaudi2_pb_dcr0_tpc0[] = {
1244     mmDCORE0_TPC0_QM_BASE,
1245     mmDCORE0_TPC0_CFG_BASE,
1246     mmDCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_BASE,
1247 };
1248
1249 static const u32 gaudi2_pb_dcr0_tpc0_arc[] = {
1250     mmDCORE0_TPC0_QM_ARC_AUX_BASE,
1251 };
1252
1253 static const struct range gaudi2_pb_dcr0_tpc0_arc_unsecured_regs[] = {
1254     {mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_ACK},
1255     {mmDCORE0_TPC0_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_TPC0_QM_ARC_AUX_WAKE_UP_EVENT},
1256     {mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_7},
1257     {mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
1258     {mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
1259     {mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
1260     {mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0,
1261         mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
1262     {mmDCORE0_TPC0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT,
1263         mmDCORE0_TPC0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
1264     {mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT,
1265         mmDCORE0_TPC0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
1266 };
1267
1268 static const u32 gaudi2_pb_dcr0_tpc0_unsecured_regs[] = {
1269     mmDCORE0_TPC0_QM_CQ_CFG0_0,
1270     mmDCORE0_TPC0_QM_CQ_CFG0_1,
1271     mmDCORE0_TPC0_QM_CQ_CFG0_2,
1272     mmDCORE0_TPC0_QM_CQ_CFG0_3,
1273     mmDCORE0_TPC0_QM_CQ_CFG0_4,
1274     mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_0,
1275     mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_1,
1276     mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_2,
1277     mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_3,
1278     mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_4,
1279     mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_0,
1280     mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_1,
1281     mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_2,
1282     mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_3,
1283     mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_4,
1284     mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_0,
1285     mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_1,
1286     mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_2,
1287     mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_3,
1288     mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_4,
1289     mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_0,
1290     mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_1,
1291     mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_2,
1292     mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_3,
1293     mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_4,
1294     mmDCORE0_TPC0_QM_CP_FENCE0_CNT_0,
1295     mmDCORE0_TPC0_QM_CP_FENCE0_CNT_1,
1296     mmDCORE0_TPC0_QM_CP_FENCE0_CNT_2,
1297     mmDCORE0_TPC0_QM_CP_FENCE0_CNT_3,
1298     mmDCORE0_TPC0_QM_CP_FENCE0_CNT_4,
1299     mmDCORE0_TPC0_QM_CP_FENCE1_CNT_0,
1300     mmDCORE0_TPC0_QM_CP_FENCE1_CNT_1,
1301     mmDCORE0_TPC0_QM_CP_FENCE1_CNT_2,
1302     mmDCORE0_TPC0_QM_CP_FENCE1_CNT_3,
1303     mmDCORE0_TPC0_QM_CP_FENCE1_CNT_4,
1304     mmDCORE0_TPC0_QM_CP_FENCE2_CNT_0,
1305     mmDCORE0_TPC0_QM_CP_FENCE2_CNT_1,
1306     mmDCORE0_TPC0_QM_CP_FENCE2_CNT_2,
1307     mmDCORE0_TPC0_QM_CP_FENCE2_CNT_3,
1308     mmDCORE0_TPC0_QM_CP_FENCE2_CNT_4,
1309     mmDCORE0_TPC0_QM_CP_FENCE3_CNT_0,
1310     mmDCORE0_TPC0_QM_CP_FENCE3_CNT_1,
1311     mmDCORE0_TPC0_QM_CP_FENCE3_CNT_2,
1312     mmDCORE0_TPC0_QM_CP_FENCE3_CNT_3,
1313     mmDCORE0_TPC0_QM_CP_FENCE3_CNT_4,
1314     mmDCORE0_TPC0_QM_CQ_PTR_LO_0,
1315     mmDCORE0_TPC0_QM_CQ_PTR_HI_0,
1316     mmDCORE0_TPC0_QM_CQ_TSIZE_0,
1317     mmDCORE0_TPC0_QM_CQ_CTL_0,
1318     mmDCORE0_TPC0_QM_CQ_PTR_LO_1,
1319     mmDCORE0_TPC0_QM_CQ_PTR_HI_1,
1320     mmDCORE0_TPC0_QM_CQ_TSIZE_1,
1321     mmDCORE0_TPC0_QM_CQ_CTL_1,
1322     mmDCORE0_TPC0_QM_CQ_PTR_LO_2,
1323     mmDCORE0_TPC0_QM_CQ_PTR_HI_2,
1324     mmDCORE0_TPC0_QM_CQ_TSIZE_2,
1325     mmDCORE0_TPC0_QM_CQ_CTL_2,
1326     mmDCORE0_TPC0_QM_CQ_PTR_LO_3,
1327     mmDCORE0_TPC0_QM_CQ_PTR_HI_3,
1328     mmDCORE0_TPC0_QM_CQ_TSIZE_3,
1329     mmDCORE0_TPC0_QM_CQ_CTL_3,
1330     mmDCORE0_TPC0_QM_CQ_PTR_LO_4,
1331     mmDCORE0_TPC0_QM_CQ_PTR_HI_4,
1332     mmDCORE0_TPC0_QM_CQ_TSIZE_4,
1333     mmDCORE0_TPC0_QM_CQ_CTL_4,
1334     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE,
1335     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
1336     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE,
1337     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
1338     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE,
1339     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
1340     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE,
1341     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
1342     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE,
1343     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
1344     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE,
1345     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
1346     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE,
1347     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
1348     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE,
1349     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
1350     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE,
1351     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
1352     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE,
1353     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
1354     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE,
1355     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
1356     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE,
1357     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
1358     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE,
1359     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
1360     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE,
1361     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
1362     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE,
1363     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
1364     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE,
1365     mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
1366     mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO,
1367     mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO_STS,
1368     mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI,
1369     mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI_STS,
1370     mmDCORE0_TPC0_QM_ARB_CFG_0,
1371     mmDCORE0_TPC0_QM_ARB_MST_QUIET_PER,
1372     mmDCORE0_TPC0_QM_ARB_CHOICE_Q_PUSH,
1373     mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_0,
1374     mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_1,
1375     mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_2,
1376     mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_3,
1377     mmDCORE0_TPC0_QM_ARB_BASE_LO,
1378     mmDCORE0_TPC0_QM_ARB_BASE_HI,
1379     mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN,
1380     mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN_1,
1381     mmDCORE0_TPC0_QM_ARB_MST_CRED_INC,
1382     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_0,
1383     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_1,
1384     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_2,
1385     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_3,
1386     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_4,
1387     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_5,
1388     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_6,
1389     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_7,
1390     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_8,
1391     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_9,
1392     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_10,
1393     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_11,
1394     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_12,
1395     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_13,
1396     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_14,
1397     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_15,
1398     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_16,
1399     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_17,
1400     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_18,
1401     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_19,
1402     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_20,
1403     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_21,
1404     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_22,
1405     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_23,
1406     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_24,
1407     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_25,
1408     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_26,
1409     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_27,
1410     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_28,
1411     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_29,
1412     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_30,
1413     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_31,
1414     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_32,
1415     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_33,
1416     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_34,
1417     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_35,
1418     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_36,
1419     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_37,
1420     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_38,
1421     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_39,
1422     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_40,
1423     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_41,
1424     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_42,
1425     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_43,
1426     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_44,
1427     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_45,
1428     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_46,
1429     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_47,
1430     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_48,
1431     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_49,
1432     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_50,
1433     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_51,
1434     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_52,
1435     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_53,
1436     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_54,
1437     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_55,
1438     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_56,
1439     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_57,
1440     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_58,
1441     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_59,
1442     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_60,
1443     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_61,
1444     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_62,
1445     mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_63,
1446     mmDCORE0_TPC0_QM_ARB_SLV_ID,
1447     mmDCORE0_TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST,
1448     mmDCORE0_TPC0_QM_ARC_CQ_CFG0,
1449     mmDCORE0_TPC0_QM_CQ_IFIFO_CI_0,
1450     mmDCORE0_TPC0_QM_CQ_IFIFO_CI_1,
1451     mmDCORE0_TPC0_QM_CQ_IFIFO_CI_2,
1452     mmDCORE0_TPC0_QM_CQ_IFIFO_CI_3,
1453     mmDCORE0_TPC0_QM_CQ_IFIFO_CI_4,
1454     mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_CI,
1455     mmDCORE0_TPC0_QM_CQ_CTL_CI_0,
1456     mmDCORE0_TPC0_QM_CQ_CTL_CI_1,
1457     mmDCORE0_TPC0_QM_CQ_CTL_CI_2,
1458     mmDCORE0_TPC0_QM_CQ_CTL_CI_3,
1459     mmDCORE0_TPC0_QM_CQ_CTL_CI_4,
1460     mmDCORE0_TPC0_QM_ARC_CQ_CTL_CI,
1461     mmDCORE0_TPC0_QM_ARC_CQ_TSIZE,
1462     mmDCORE0_TPC0_QM_ARC_CQ_CTL,
1463     mmDCORE0_TPC0_QM_CP_SWITCH_WD_SET,
1464     mmDCORE0_TPC0_QM_CP_EXT_SWITCH,
1465     mmDCORE0_TPC0_QM_CP_PRED_0,
1466     mmDCORE0_TPC0_QM_CP_PRED_1,
1467     mmDCORE0_TPC0_QM_CP_PRED_2,
1468     mmDCORE0_TPC0_QM_CP_PRED_3,
1469     mmDCORE0_TPC0_QM_CP_PRED_4,
1470     mmDCORE0_TPC0_QM_CP_PRED_UPEN_0,
1471     mmDCORE0_TPC0_QM_CP_PRED_UPEN_1,
1472     mmDCORE0_TPC0_QM_CP_PRED_UPEN_2,
1473     mmDCORE0_TPC0_QM_CP_PRED_UPEN_3,
1474     mmDCORE0_TPC0_QM_CP_PRED_UPEN_4,
1475     mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_0,
1476     mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_1,
1477     mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_2,
1478     mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_3,
1479     mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_4,
1480     mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_0,
1481     mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_1,
1482     mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_2,
1483     mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_3,
1484     mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_4,
1485     mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_0,
1486     mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_1,
1487     mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_2,
1488     mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_3,
1489     mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_4,
1490     mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_0,
1491     mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_1,
1492     mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_2,
1493     mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_3,
1494     mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_4,
1495     mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_0,
1496     mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_1,
1497     mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_2,
1498     mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_3,
1499     mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_4,
1500     mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_0,
1501     mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_1,
1502     mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_2,
1503     mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_3,
1504     mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_4,
1505     mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_0,
1506     mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_1,
1507     mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_2,
1508     mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_3,
1509     mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_4,
1510     mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_0,
1511     mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_1,
1512     mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_2,
1513     mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_3,
1514     mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_4,
1515     mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
1516     mmDCORE0_TPC0_QM_ARC_CQ_CTL_MSG_BASE_LO,
1517     mmDCORE0_TPC0_QM_CQ_IFIFO_MSG_BASE_LO,
1518     mmDCORE0_TPC0_QM_CQ_CTL_MSG_BASE_LO,
1519     mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_MESSAGE,
1520     mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_ADDR,
1521     mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW,
1522     mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH,
1523     mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_0,
1524     mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_0,
1525     mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_1,
1526     mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_1,
1527     mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_2,
1528     mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_2,
1529     mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_3,
1530     mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_3,
1531     mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_4,
1532     mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_4,
1533     mmDCORE0_TPC0_CFG_QM_KERNEL_CONFIG,
1534     mmDCORE0_TPC0_CFG_QM_KERNEL_ID,
1535     mmDCORE0_TPC0_CFG_QM_POWER_LOOP,
1536     mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO,
1537     mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI,
1538     mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO,
1539     mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI,
1540     mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO,
1541     mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI,
1542     mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO,
1543     mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI,
1544     mmDCORE0_TPC0_CFG_ROUND_CSR,
1545     mmDCORE0_TPC0_CFG_CONV_ROUND_CSR,
1546     mmDCORE0_TPC0_CFG_SEMAPHORE,
1547     mmDCORE0_TPC0_CFG_LFSR_POLYNOM,
1548     mmDCORE0_TPC0_CFG_STATUS,
1549     mmDCORE0_TPC0_CFG_TPC_CMD,
1550     mmDCORE0_TPC0_CFG_TPC_EXECUTE,
1551     mmDCORE0_TPC0_CFG_TPC_DCACHE_L0CD,
1552     mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW,
1553     mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH,
1554     mmDCORE0_TPC0_CFG_RD_RATE_LIMIT,
1555     mmDCORE0_TPC0_CFG_WR_RATE_LIMIT,
1556     mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO,
1557     mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI,
1558     mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO,
1559     mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI,
1560     mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO,
1561     mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI,
1562     mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO,
1563     mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI,
1564     mmDCORE0_TPC0_CFG_KERNEL_SRF_0,
1565     mmDCORE0_TPC0_CFG_KERNEL_SRF_1,
1566     mmDCORE0_TPC0_CFG_KERNEL_SRF_2,
1567     mmDCORE0_TPC0_CFG_KERNEL_SRF_3,
1568     mmDCORE0_TPC0_CFG_KERNEL_SRF_4,
1569     mmDCORE0_TPC0_CFG_KERNEL_SRF_5,
1570     mmDCORE0_TPC0_CFG_KERNEL_SRF_6,
1571     mmDCORE0_TPC0_CFG_KERNEL_SRF_7,
1572     mmDCORE0_TPC0_CFG_KERNEL_SRF_8,
1573     mmDCORE0_TPC0_CFG_KERNEL_SRF_9,
1574     mmDCORE0_TPC0_CFG_KERNEL_SRF_10,
1575     mmDCORE0_TPC0_CFG_KERNEL_SRF_11,
1576     mmDCORE0_TPC0_CFG_KERNEL_SRF_12,
1577     mmDCORE0_TPC0_CFG_KERNEL_SRF_13,
1578     mmDCORE0_TPC0_CFG_KERNEL_SRF_14,
1579     mmDCORE0_TPC0_CFG_KERNEL_SRF_15,
1580     mmDCORE0_TPC0_CFG_KERNEL_SRF_16,
1581     mmDCORE0_TPC0_CFG_KERNEL_SRF_17,
1582     mmDCORE0_TPC0_CFG_KERNEL_SRF_18,
1583     mmDCORE0_TPC0_CFG_KERNEL_SRF_19,
1584     mmDCORE0_TPC0_CFG_KERNEL_SRF_20,
1585     mmDCORE0_TPC0_CFG_KERNEL_SRF_21,
1586     mmDCORE0_TPC0_CFG_KERNEL_SRF_22,
1587     mmDCORE0_TPC0_CFG_KERNEL_SRF_23,
1588     mmDCORE0_TPC0_CFG_KERNEL_SRF_24,
1589     mmDCORE0_TPC0_CFG_KERNEL_SRF_25,
1590     mmDCORE0_TPC0_CFG_KERNEL_SRF_26,
1591     mmDCORE0_TPC0_CFG_KERNEL_SRF_27,
1592     mmDCORE0_TPC0_CFG_KERNEL_SRF_28,
1593     mmDCORE0_TPC0_CFG_KERNEL_SRF_29,
1594     mmDCORE0_TPC0_CFG_KERNEL_SRF_30,
1595     mmDCORE0_TPC0_CFG_KERNEL_SRF_31,
1596     mmDCORE0_TPC0_CFG_TPC_SB_L0CD,
1597     mmDCORE0_TPC0_CFG_QM_KERNEL_ID_INC,
1598     mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_0,
1599     mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_1,
1600     mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_2,
1601     mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_3,
1602     mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_4,
1603     mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_0,
1604     mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_1,
1605     mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_2,
1606     mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_3
1607 };
1608
1609 static const u32 gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs[] = {
1610     mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW,
1611     mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH,
1612     mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE,
1613     mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG,
1614     mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE,
1615     mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE,
1616     mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE,
1617     mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE,
1618     mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE,
1619     mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE,
1620     mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE,
1621     mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE,
1622     mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE,
1623     mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE,
1624     mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PREF_STRIDE,
1625     mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH,
1626     mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH,
1627     mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH,
1628     mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH,
1629     mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH,
1630 };
1631
1632 static const u32 gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs[] = {
1633     mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW,
1634     mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH,
1635     mmDCORE0_TPC0_CFG_QM_TENSOR_0_PADDING_VALUE,
1636     mmDCORE0_TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG,
1637     mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE,
1638     mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE,
1639     mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE,
1640     mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE,
1641     mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE,
1642     mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE,
1643     mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE,
1644     mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE,
1645     mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE,
1646     mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE,
1647     mmDCORE0_TPC0_CFG_QM_TENSOR_0_PREF_STRIDE,
1648     mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH,
1649     mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH,
1650     mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH,
1651     mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH,
1652     mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH,
1653 };
1654
1655 static const u32 gaudi2_pb_dcr0_sram0[] = {
1656     mmDCORE0_SRAM0_BANK_BASE,
1657     mmDCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE,
1658     mmDCORE0_SRAM0_RTR_BASE,
1659 };
1660
1661 static const u32 gaudi2_pb_dcr0_sm_mstr_if[] = {
1662     mmDCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE,
1663 };
1664
1665 static const u32 gaudi2_pb_dcr0_sm_glbl[] = {
1666     mmDCORE0_SYNC_MNGR_GLBL_BASE,
1667 };
1668
1669 static const struct range gaudi2_pb_dcr0_sm_glbl_unsecured_regs[] = {
1670     {mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63},
1671     {mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63},
1672     {mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63},
1673     {mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_63},
1674     {mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_63},
1675     {mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_63},
1676     {mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_63},
1677     {mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_63},
1678 };
1679
1680 static const struct range gaudi2_pb_dcr_x_sm_glbl_unsecured_regs[] = {
1681     {mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63},
1682     {mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63},
1683     {mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0, mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63},
1684     {mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_0, mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_63},
1685     {mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_0, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_63},
1686     {mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_63},
1687     {mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_0, mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_63},
1688     {mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_0, mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_63},
1689 };
1690
1691 static const u32 gaudi2_pb_arc_sched[] = {
1692     mmARC_FARM_ARC0_AUX_BASE,
1693     mmARC_FARM_ARC0_DUP_ENG_BASE,
1694     mmARC_FARM_ARC0_ACP_ENG_BASE,
1695 };
1696
1697 static const struct range gaudi2_pb_arc_sched_unsecured_regs[] = {
1698     {mmARC_FARM_ARC0_AUX_RUN_HALT_REQ, mmARC_FARM_ARC0_AUX_RUN_HALT_ACK},
1699     {mmARC_FARM_ARC0_AUX_CLUSTER_NUM, mmARC_FARM_ARC0_AUX_WAKE_UP_EVENT},
1700     {mmARC_FARM_ARC0_AUX_ARC_RST_REQ, mmARC_FARM_ARC0_AUX_CID_OFFSET_7},
1701     {mmARC_FARM_ARC0_AUX_SCRATCHPAD_0, mmARC_FARM_ARC0_AUX_INFLIGHT_LBU_RD_CNT},
1702     {mmARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN, mmARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN},
1703     {mmARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN, mmARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN},
1704     {mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_0, mmARC_FARM_ARC0_AUX_DCCM_QUEUE_ALERT_MSG},
1705     {mmARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_CNT, mmARC_FARM_ARC0_AUX_QMAN_ARC_CQ_SHADOW_CI},
1706     {mmARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN},
1707     {mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_0, mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_63},
1708     {mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_STRONG_ORDER, mmARC_FARM_ARC0_DUP_ENG_AXUSER_LB_OVRD},
1709     {mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_0, mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_REG},
1710 };
1711
1712 static const u32 gaudi2_pb_xbar_mid[] = {
1713     mmXBAR_MID_0_BASE,
1714 };
1715
1716 static const u32 gaudi2_pb_xbar_mid_unsecured_regs[] = {
1717     mmXBAR_MID_0_UPSCALE,
1718     mmXBAR_MID_0_DOWN_CONV,
1719     mmXBAR_MID_0_DOWN_CONV_LFSR_EN,
1720     mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VLD,
1721     mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VALUE,
1722     mmXBAR_MID_0_DOWN_CONV_LFSR_CFG_POLY,
1723 };
1724
1725 static const u32 gaudi2_pb_xbar_edge[] = {
1726     mmXBAR_EDGE_0_BASE,
1727 };
1728
1729 static const u32 gaudi2_pb_xbar_edge_unsecured_regs[] = {
1730     mmXBAR_EDGE_0_UPSCALE,
1731     mmXBAR_EDGE_0_DOWN_CONV,
1732     mmXBAR_EDGE_0_DOWN_CONV_LFSR_EN,
1733     mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VLD,
1734     mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VALUE,
1735     mmXBAR_EDGE_0_DOWN_CONV_LFSR_CFG_POLY,
1736 };
1737
1738 static const u32 gaudi2_pb_nic0[] = {
1739     mmNIC0_TMR_BASE,
1740     mmNIC0_RXB_CORE_BASE,
1741     mmNIC0_RXE0_BASE,
1742     mmNIC0_RXE1_BASE,
1743     mmNIC0_RXE0_AXUSER_AXUSER_CQ0_BASE,
1744     mmNIC0_RXE1_AXUSER_AXUSER_CQ0_BASE,
1745     mmNIC0_TXS0_BASE,
1746     mmNIC0_TXS1_BASE,
1747     mmNIC0_TXE0_BASE,
1748     mmNIC0_TXE1_BASE,
1749     mmNIC0_TXB_BASE,
1750     mmNIC0_MSTR_IF_RR_SHRD_HBW_BASE,
1751 };
1752
1753 static const u32 gaudi2_pb_nic0_qm_qpc[] = {
1754     mmNIC0_QM0_BASE,
1755     mmNIC0_QPC0_BASE,
1756 };
1757
1758 static const u32 gaudi2_pb_nic0_qm_arc_aux0[] = {
1759     mmNIC0_QM_ARC_AUX0_BASE,
1760 };
1761
1762 static const struct range gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs[] = {
1763     {mmNIC0_QM_ARC_AUX0_RUN_HALT_REQ, mmNIC0_QM_ARC_AUX0_RUN_HALT_ACK},
1764     {mmNIC0_QM_ARC_AUX0_CLUSTER_NUM, mmNIC0_QM_ARC_AUX0_WAKE_UP_EVENT},
1765     {mmNIC0_QM_ARC_AUX0_ARC_RST_REQ, mmNIC0_QM_ARC_AUX0_CID_OFFSET_7},
1766     {mmNIC0_QM_ARC_AUX0_SCRATCHPAD_0, mmNIC0_QM_ARC_AUX0_INFLIGHT_LBU_RD_CNT},
1767     {mmNIC0_QM_ARC_AUX0_LBU_EARLY_BRESP_EN, mmNIC0_QM_ARC_AUX0_LBU_EARLY_BRESP_EN},
1768     {mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_0, mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_ALERT_MSG},
1769     {mmNIC0_QM_ARC_AUX0_DCCM_Q_PUSH_FIFO_CNT, mmNIC0_QM_ARC_AUX0_QMAN_ARC_CQ_SHADOW_CI},
1770     {mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_WR_IF_CNT, mmNIC0_QM_ARC_AUX0_MME_ARC_UPPER_DCCM_EN},
1771 };
1772
1773 static const u32 gaudi2_pb_nic0_umr[] = {
1774     mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE,
1775     mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 1, /* UMR0_1 */
1776     mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 2, /* UMR0_2 */
1777     mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 3, /* UMR0_3 */
1778     mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 4, /* UMR0_4 */
1779     mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 5, /* UMR0_5 */
1780     mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 6, /* UMR0_6 */
1781     mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 7, /* UMR0_7 */
1782     mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 8, /* UMR0_8 */
1783     mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 9, /* UMR0_9 */
1784     mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 10, /* UMR0_10 */
1785     mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 11, /* UMR0_11 */
1786     mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 12, /* UMR0_12 */
1787     mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 13, /* UMR0_13 */
1788     mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 14, /* UMR0_14 */
1789 };
1790
1791 static const struct range gaudi2_pb_nic0_umr_unsecured_regs[] = {
1792     {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32,
1793         mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX},
1794     {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 1, /* UMR0_1 */
1795         mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 1},
1796     {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 2, /* UMR0_2 */
1797         mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 2},
1798     {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 3, /* UMR0_3 */
1799         mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 3},
1800     {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 4, /* UMR0_4 */
1801         mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 4},
1802     {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 5, /* UMR0_5 */
1803         mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 5},
1804     {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 6, /* UMR0_6 */
1805         mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 6},
1806     {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 7, /* UMR0_7 */
1807         mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 7},
1808     {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 8, /* UMR0_8 */
1809         mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 8},
1810     {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 9, /* UMR0_9 */
1811         mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 9},
1812     {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 10, /* UMR0_10 */
1813         mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 10},
1814     {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 11, /* UMR0_11 */
1815         mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 11},
1816     {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 12, /* UMR0_12 */
1817         mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 12},
1818     {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 13, /* UMR0_13 */
1819         mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 13},
1820     {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 14, /* UMR0_14 */
1821         mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 14},
1822 };
1823
1824 /*
1825  * mmNIC0_QPC0_LINEAR_WQE_QPN and mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN are 32-bit
1826  * registers and since the user writes in bulks of 64 bits we need to un-secure
1827  * also the following 32 bits (that's why we added also the next 4 bytes to the
1828  * table). In the RTL, as part of ECO (2874), writing to the next 4 bytes
1829  * triggers a write to the SPECIAL_GLBL_SPARE register, hence it's must be
1830  * unsecured as well.
1831  */
1832 #define mmNIC0_QPC0_LINEAR_WQE_RSV (mmNIC0_QPC0_LINEAR_WQE_QPN + 4)
1833 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_RSV (mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN + 4)
1834 #define mmNIC0_QPC0_SPECIAL_GLBL_SPARE 0x541FF60
1835
1836 static const u32 gaudi2_pb_nic0_qm_qpc_unsecured_regs[] = {
1837     mmNIC0_QPC0_LINEAR_WQE_STATIC_0,
1838     mmNIC0_QPC0_LINEAR_WQE_STATIC_1,
1839     mmNIC0_QPC0_LINEAR_WQE_STATIC_2,
1840     mmNIC0_QPC0_LINEAR_WQE_STATIC_3,
1841     mmNIC0_QPC0_LINEAR_WQE_STATIC_4,
1842     mmNIC0_QPC0_LINEAR_WQE_STATIC_5,
1843     mmNIC0_QPC0_LINEAR_WQE_STATIC_6,
1844     mmNIC0_QPC0_LINEAR_WQE_STATIC_7,
1845     mmNIC0_QPC0_LINEAR_WQE_STATIC_8,
1846     mmNIC0_QPC0_LINEAR_WQE_STATIC_9,
1847     mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_0,
1848     mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_1,
1849     mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_2,
1850     mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_3,
1851     mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_4,
1852     mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_5,
1853     mmNIC0_QPC0_LINEAR_WQE_QPN,
1854     mmNIC0_QPC0_LINEAR_WQE_RSV,
1855     mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_0,
1856     mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_1,
1857     mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_2,
1858     mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_3,
1859     mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_4,
1860     mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_5,
1861     mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_6,
1862     mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_7,
1863     mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_8,
1864     mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_9,
1865     mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_10,
1866     mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_11,
1867     mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_12,
1868     mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_13,
1869     mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_14,
1870     mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_15,
1871     mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_16,
1872     mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_17,
1873     mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_0,
1874     mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_1,
1875     mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_2,
1876     mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_3,
1877     mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_4,
1878     mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_5,
1879     mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN,
1880     mmNIC0_QPC0_MULTI_STRIDE_WQE_RSV,
1881     mmNIC0_QPC0_QMAN_DOORBELL,
1882     mmNIC0_QPC0_QMAN_DOORBELL_QPN,
1883     mmNIC0_QPC0_SPECIAL_GLBL_SPARE,
1884     mmNIC0_QM0_CQ_CFG0_0,
1885     mmNIC0_QM0_CQ_CFG0_1,
1886     mmNIC0_QM0_CQ_CFG0_2,
1887     mmNIC0_QM0_CQ_CFG0_3,
1888     mmNIC0_QM0_CQ_CFG0_4,
1889     mmNIC0_QM0_CP_FENCE0_RDATA_0,
1890     mmNIC0_QM0_CP_FENCE0_RDATA_1,
1891     mmNIC0_QM0_CP_FENCE0_RDATA_2,
1892     mmNIC0_QM0_CP_FENCE0_RDATA_3,
1893     mmNIC0_QM0_CP_FENCE0_RDATA_4,
1894     mmNIC0_QM0_CP_FENCE1_RDATA_0,
1895     mmNIC0_QM0_CP_FENCE1_RDATA_1,
1896     mmNIC0_QM0_CP_FENCE1_RDATA_2,
1897     mmNIC0_QM0_CP_FENCE1_RDATA_3,
1898     mmNIC0_QM0_CP_FENCE1_RDATA_4,
1899     mmNIC0_QM0_CP_FENCE2_RDATA_0,
1900     mmNIC0_QM0_CP_FENCE2_RDATA_1,
1901     mmNIC0_QM0_CP_FENCE2_RDATA_2,
1902     mmNIC0_QM0_CP_FENCE2_RDATA_3,
1903     mmNIC0_QM0_CP_FENCE2_RDATA_4,
1904     mmNIC0_QM0_CP_FENCE3_RDATA_0,
1905     mmNIC0_QM0_CP_FENCE3_RDATA_1,
1906     mmNIC0_QM0_CP_FENCE3_RDATA_2,
1907     mmNIC0_QM0_CP_FENCE3_RDATA_3,
1908     mmNIC0_QM0_CP_FENCE3_RDATA_4,
1909     mmNIC0_QM0_CP_FENCE0_CNT_0,
1910     mmNIC0_QM0_CP_FENCE0_CNT_1,
1911     mmNIC0_QM0_CP_FENCE0_CNT_2,
1912     mmNIC0_QM0_CP_FENCE0_CNT_3,
1913     mmNIC0_QM0_CP_FENCE0_CNT_4,
1914     mmNIC0_QM0_CP_FENCE1_CNT_0,
1915     mmNIC0_QM0_CP_FENCE1_CNT_1,
1916     mmNIC0_QM0_CP_FENCE1_CNT_2,
1917     mmNIC0_QM0_CP_FENCE1_CNT_3,
1918     mmNIC0_QM0_CP_FENCE1_CNT_4,
1919     mmNIC0_QM0_CP_FENCE2_CNT_0,
1920     mmNIC0_QM0_CP_FENCE2_CNT_1,
1921     mmNIC0_QM0_CP_FENCE2_CNT_2,
1922     mmNIC0_QM0_CP_FENCE2_CNT_3,
1923     mmNIC0_QM0_CP_FENCE2_CNT_4,
1924     mmNIC0_QM0_CP_FENCE3_CNT_0,
1925     mmNIC0_QM0_CP_FENCE3_CNT_1,
1926     mmNIC0_QM0_CP_FENCE3_CNT_2,
1927     mmNIC0_QM0_CP_FENCE3_CNT_3,
1928     mmNIC0_QM0_CP_FENCE3_CNT_4,
1929     mmNIC0_QM0_CQ_PTR_LO_0,
1930     mmNIC0_QM0_CQ_PTR_HI_0,
1931     mmNIC0_QM0_CQ_TSIZE_0,
1932     mmNIC0_QM0_CQ_CTL_0,
1933     mmNIC0_QM0_CQ_PTR_LO_1,
1934     mmNIC0_QM0_CQ_PTR_HI_1,
1935     mmNIC0_QM0_CQ_TSIZE_1,
1936     mmNIC0_QM0_CQ_CTL_1,
1937     mmNIC0_QM0_CQ_PTR_LO_2,
1938     mmNIC0_QM0_CQ_PTR_HI_2,
1939     mmNIC0_QM0_CQ_TSIZE_2,
1940     mmNIC0_QM0_CQ_CTL_2,
1941     mmNIC0_QM0_CQ_PTR_LO_3,
1942     mmNIC0_QM0_CQ_PTR_HI_3,
1943     mmNIC0_QM0_CQ_TSIZE_3,
1944     mmNIC0_QM0_CQ_CTL_3,
1945     mmNIC0_QM0_CQ_PTR_LO_4,
1946     mmNIC0_QM0_CQ_PTR_HI_4,
1947     mmNIC0_QM0_CQ_TSIZE_4,
1948     mmNIC0_QM0_CQ_CTL_4,
1949     mmNIC0_QM0_QMAN_WR64_BASE_ADDR0_BASE,
1950     mmNIC0_QM0_QMAN_WR64_BASE_ADDR0_BASE + 4,
1951     mmNIC0_QM0_QMAN_WR64_BASE_ADDR1_BASE,
1952     mmNIC0_QM0_QMAN_WR64_BASE_ADDR1_BASE + 4,
1953     mmNIC0_QM0_QMAN_WR64_BASE_ADDR2_BASE,
1954     mmNIC0_QM0_QMAN_WR64_BASE_ADDR2_BASE + 4,
1955     mmNIC0_QM0_QMAN_WR64_BASE_ADDR3_BASE,
1956     mmNIC0_QM0_QMAN_WR64_BASE_ADDR3_BASE + 4,
1957     mmNIC0_QM0_QMAN_WR64_BASE_ADDR4_BASE,
1958     mmNIC0_QM0_QMAN_WR64_BASE_ADDR4_BASE + 4,
1959     mmNIC0_QM0_QMAN_WR64_BASE_ADDR5_BASE,
1960     mmNIC0_QM0_QMAN_WR64_BASE_ADDR5_BASE + 4,
1961     mmNIC0_QM0_QMAN_WR64_BASE_ADDR6_BASE,
1962     mmNIC0_QM0_QMAN_WR64_BASE_ADDR6_BASE + 4,
1963     mmNIC0_QM0_QMAN_WR64_BASE_ADDR7_BASE,
1964     mmNIC0_QM0_QMAN_WR64_BASE_ADDR7_BASE + 4,
1965     mmNIC0_QM0_QMAN_WR64_BASE_ADDR8_BASE,
1966     mmNIC0_QM0_QMAN_WR64_BASE_ADDR8_BASE + 4,
1967     mmNIC0_QM0_QMAN_WR64_BASE_ADDR9_BASE,
1968     mmNIC0_QM0_QMAN_WR64_BASE_ADDR9_BASE + 4,
1969     mmNIC0_QM0_QMAN_WR64_BASE_ADDR10_BASE,
1970     mmNIC0_QM0_QMAN_WR64_BASE_ADDR10_BASE + 4,
1971     mmNIC0_QM0_QMAN_WR64_BASE_ADDR11_BASE,
1972     mmNIC0_QM0_QMAN_WR64_BASE_ADDR11_BASE + 4,
1973     mmNIC0_QM0_QMAN_WR64_BASE_ADDR12_BASE,
1974     mmNIC0_QM0_QMAN_WR64_BASE_ADDR12_BASE + 4,
1975     mmNIC0_QM0_QMAN_WR64_BASE_ADDR13_BASE,
1976     mmNIC0_QM0_QMAN_WR64_BASE_ADDR13_BASE + 4,
1977     mmNIC0_QM0_QMAN_WR64_BASE_ADDR14_BASE,
1978     mmNIC0_QM0_QMAN_WR64_BASE_ADDR14_BASE + 4,
1979     mmNIC0_QM0_QMAN_WR64_BASE_ADDR15_BASE,
1980     mmNIC0_QM0_QMAN_WR64_BASE_ADDR15_BASE + 4,
1981     mmNIC0_QM0_ARC_CQ_PTR_LO,
1982     mmNIC0_QM0_ARC_CQ_PTR_LO_STS,
1983     mmNIC0_QM0_ARC_CQ_PTR_HI,
1984     mmNIC0_QM0_ARC_CQ_PTR_HI_STS,
1985     mmNIC0_QM0_ARB_CFG_0,
1986     mmNIC0_QM0_ARB_MST_QUIET_PER,
1987     mmNIC0_QM0_ARB_CHOICE_Q_PUSH,
1988     mmNIC0_QM0_ARB_WRR_WEIGHT_0,
1989     mmNIC0_QM0_ARB_WRR_WEIGHT_1,
1990     mmNIC0_QM0_ARB_WRR_WEIGHT_2,
1991     mmNIC0_QM0_ARB_WRR_WEIGHT_3,
1992     mmNIC0_QM0_ARB_BASE_LO,
1993     mmNIC0_QM0_ARB_BASE_HI,
1994     mmNIC0_QM0_ARB_MST_SLAVE_EN,
1995     mmNIC0_QM0_ARB_MST_SLAVE_EN_1,
1996     mmNIC0_QM0_ARB_MST_CRED_INC,
1997     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_0,
1998     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_1,
1999     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_2,
2000     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_3,
2001     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_4,
2002     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_5,
2003     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_6,
2004     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_7,
2005     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_8,
2006     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_9,
2007     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_10,
2008     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_11,
2009     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_12,
2010     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_13,
2011     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_14,
2012     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_15,
2013     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_16,
2014     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_17,
2015     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_18,
2016     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_19,
2017     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_20,
2018     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_21,
2019     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_22,
2020     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_23,
2021     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_24,
2022     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_25,
2023     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_26,
2024     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_27,
2025     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_28,
2026     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_29,
2027     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_30,
2028     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_31,
2029     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_32,
2030     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_33,
2031     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_34,
2032     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_35,
2033     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_36,
2034     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_37,
2035     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_38,
2036     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_39,
2037     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_40,
2038     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_41,
2039     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_42,
2040     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_43,
2041     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_44,
2042     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_45,
2043     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_46,
2044     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_47,
2045     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_48,
2046     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_49,
2047     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_50,
2048     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_51,
2049     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_52,
2050     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_53,
2051     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_54,
2052     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_55,
2053     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_56,
2054     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_57,
2055     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_58,
2056     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_59,
2057     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_60,
2058     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_61,
2059     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_62,
2060     mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_63,
2061     mmNIC0_QM0_ARB_SLV_ID,
2062     mmNIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST,
2063     mmNIC0_QM0_ARC_CQ_CFG0,
2064     mmNIC0_QM0_CQ_IFIFO_CI_0,
2065     mmNIC0_QM0_CQ_IFIFO_CI_1,
2066     mmNIC0_QM0_CQ_IFIFO_CI_2,
2067     mmNIC0_QM0_CQ_IFIFO_CI_3,
2068     mmNIC0_QM0_CQ_IFIFO_CI_4,
2069     mmNIC0_QM0_ARC_CQ_IFIFO_CI,
2070     mmNIC0_QM0_CQ_CTL_CI_0,
2071     mmNIC0_QM0_CQ_CTL_CI_1,
2072     mmNIC0_QM0_CQ_CTL_CI_2,
2073     mmNIC0_QM0_CQ_CTL_CI_3,
2074     mmNIC0_QM0_CQ_CTL_CI_4,
2075     mmNIC0_QM0_ARC_CQ_CTL_CI,
2076     mmNIC0_QM0_ARC_CQ_TSIZE,
2077     mmNIC0_QM0_ARC_CQ_CTL,
2078     mmNIC0_QM0_CP_SWITCH_WD_SET,
2079     mmNIC0_QM0_CP_EXT_SWITCH,
2080     mmNIC0_QM0_CP_PRED_0,
2081     mmNIC0_QM0_CP_PRED_1,
2082     mmNIC0_QM0_CP_PRED_2,
2083     mmNIC0_QM0_CP_PRED_3,
2084     mmNIC0_QM0_CP_PRED_4,
2085     mmNIC0_QM0_CP_PRED_UPEN_0,
2086     mmNIC0_QM0_CP_PRED_UPEN_1,
2087     mmNIC0_QM0_CP_PRED_UPEN_2,
2088     mmNIC0_QM0_CP_PRED_UPEN_3,
2089     mmNIC0_QM0_CP_PRED_UPEN_4,
2090     mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0,
2091     mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_1,
2092     mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_2,
2093     mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_3,
2094     mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_4,
2095     mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0,
2096     mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_1,
2097     mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_2,
2098     mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_3,
2099     mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_4,
2100     mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0,
2101     mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_1,
2102     mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_2,
2103     mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_3,
2104     mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_4,
2105     mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0,
2106     mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_1,
2107     mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_2,
2108     mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_3,
2109     mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_4,
2110     mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0,
2111     mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_1,
2112     mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2,
2113     mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_3,
2114     mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_4,
2115     mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0,
2116     mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_1,
2117     mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_2,
2118     mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_3,
2119     mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_4,
2120     mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0,
2121     mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_1,
2122     mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_2,
2123     mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_3,
2124     mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_4,
2125     mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0,
2126     mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_1,
2127     mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_2,
2128     mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_3,
2129     mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_4,
2130     mmNIC0_QM0_ARC_CQ_IFIFO_MSG_BASE_LO,
2131     mmNIC0_QM0_ARC_CQ_CTL_MSG_BASE_LO,
2132     mmNIC0_QM0_CQ_IFIFO_MSG_BASE_LO,
2133     mmNIC0_QM0_CQ_CTL_MSG_BASE_LO
2134 };
2135
2136 static const u32 gaudi2_pb_rot0[] = {
2137     mmROT0_BASE,
2138     mmROT0_MSTR_IF_RR_SHRD_HBW_BASE,
2139     mmROT0_QM_BASE,
2140 };
2141
2142 static const u32 gaudi2_pb_rot0_arc[] = {
2143     mmROT0_QM_ARC_AUX_BASE
2144 };
2145
2146 static const struct range gaudi2_pb_rot0_arc_unsecured_regs[] = {
2147     {mmROT0_QM_ARC_AUX_RUN_HALT_REQ, mmROT0_QM_ARC_AUX_RUN_HALT_ACK},
2148     {mmROT0_QM_ARC_AUX_CLUSTER_NUM, mmROT0_QM_ARC_AUX_WAKE_UP_EVENT},
2149     {mmROT0_QM_ARC_AUX_ARC_RST_REQ, mmROT0_QM_ARC_AUX_CID_OFFSET_7},
2150     {mmROT0_QM_ARC_AUX_SCRATCHPAD_0, mmROT0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
2151     {mmROT0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmROT0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
2152     {mmROT0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmROT0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
2153     {mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, mmROT0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
2154     {mmROT0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, mmROT0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
2155     {mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmROT0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
2156 };
2157
2158 static const u32 gaudi2_pb_rot0_unsecured_regs[] = {
2159     mmROT0_QM_CQ_CFG0_0,
2160     mmROT0_QM_CQ_CFG0_1,
2161     mmROT0_QM_CQ_CFG0_2,
2162     mmROT0_QM_CQ_CFG0_3,
2163     mmROT0_QM_CQ_CFG0_4,
2164     mmROT0_QM_CP_FENCE0_RDATA_0,
2165     mmROT0_QM_CP_FENCE0_RDATA_1,
2166     mmROT0_QM_CP_FENCE0_RDATA_2,
2167     mmROT0_QM_CP_FENCE0_RDATA_3,
2168     mmROT0_QM_CP_FENCE0_RDATA_4,
2169     mmROT0_QM_CP_FENCE1_RDATA_0,
2170     mmROT0_QM_CP_FENCE1_RDATA_1,
2171     mmROT0_QM_CP_FENCE1_RDATA_2,
2172     mmROT0_QM_CP_FENCE1_RDATA_3,
2173     mmROT0_QM_CP_FENCE1_RDATA_4,
2174     mmROT0_QM_CP_FENCE2_RDATA_0,
2175     mmROT0_QM_CP_FENCE2_RDATA_1,
2176     mmROT0_QM_CP_FENCE2_RDATA_2,
2177     mmROT0_QM_CP_FENCE2_RDATA_3,
2178     mmROT0_QM_CP_FENCE2_RDATA_4,
2179     mmROT0_QM_CP_FENCE3_RDATA_0,
2180     mmROT0_QM_CP_FENCE3_RDATA_1,
2181     mmROT0_QM_CP_FENCE3_RDATA_2,
2182     mmROT0_QM_CP_FENCE3_RDATA_3,
2183     mmROT0_QM_CP_FENCE3_RDATA_4,
2184     mmROT0_QM_CP_FENCE0_CNT_0,
2185     mmROT0_QM_CP_FENCE0_CNT_1,
2186     mmROT0_QM_CP_FENCE0_CNT_2,
2187     mmROT0_QM_CP_FENCE0_CNT_3,
2188     mmROT0_QM_CP_FENCE0_CNT_4,
2189     mmROT0_QM_CP_FENCE1_CNT_0,
2190     mmROT0_QM_CP_FENCE1_CNT_1,
2191     mmROT0_QM_CP_FENCE1_CNT_2,
2192     mmROT0_QM_CP_FENCE1_CNT_3,
2193     mmROT0_QM_CP_FENCE1_CNT_4,
2194     mmROT0_QM_CP_FENCE2_CNT_0,
2195     mmROT0_QM_CP_FENCE2_CNT_1,
2196     mmROT0_QM_CP_FENCE2_CNT_2,
2197     mmROT0_QM_CP_FENCE2_CNT_3,
2198     mmROT0_QM_CP_FENCE2_CNT_4,
2199     mmROT0_QM_CP_FENCE3_CNT_0,
2200     mmROT0_QM_CP_FENCE3_CNT_1,
2201     mmROT0_QM_CP_FENCE3_CNT_2,
2202     mmROT0_QM_CP_FENCE3_CNT_3,
2203     mmROT0_QM_CP_FENCE3_CNT_4,
2204     mmROT0_QM_CQ_PTR_LO_0,
2205     mmROT0_QM_CQ_PTR_HI_0,
2206     mmROT0_QM_CQ_TSIZE_0,
2207     mmROT0_QM_CQ_CTL_0,
2208     mmROT0_QM_CQ_PTR_LO_1,
2209     mmROT0_QM_CQ_PTR_HI_1,
2210     mmROT0_QM_CQ_TSIZE_1,
2211     mmROT0_QM_CQ_CTL_1,
2212     mmROT0_QM_CQ_PTR_LO_2,
2213     mmROT0_QM_CQ_PTR_HI_2,
2214     mmROT0_QM_CQ_TSIZE_2,
2215     mmROT0_QM_CQ_CTL_2,
2216     mmROT0_QM_CQ_PTR_LO_3,
2217     mmROT0_QM_CQ_PTR_HI_3,
2218     mmROT0_QM_CQ_TSIZE_3,
2219     mmROT0_QM_CQ_CTL_3,
2220     mmROT0_QM_CQ_PTR_LO_4,
2221     mmROT0_QM_CQ_PTR_HI_4,
2222     mmROT0_QM_CQ_TSIZE_4,
2223     mmROT0_QM_CQ_CTL_4,
2224     mmROT0_QM_QMAN_WR64_BASE_ADDR0_BASE,
2225     mmROT0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
2226     mmROT0_QM_QMAN_WR64_BASE_ADDR1_BASE,
2227     mmROT0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
2228     mmROT0_QM_QMAN_WR64_BASE_ADDR2_BASE,
2229     mmROT0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
2230     mmROT0_QM_QMAN_WR64_BASE_ADDR3_BASE,
2231     mmROT0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
2232     mmROT0_QM_QMAN_WR64_BASE_ADDR4_BASE,
2233     mmROT0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
2234     mmROT0_QM_QMAN_WR64_BASE_ADDR5_BASE,
2235     mmROT0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
2236     mmROT0_QM_QMAN_WR64_BASE_ADDR6_BASE,
2237     mmROT0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
2238     mmROT0_QM_QMAN_WR64_BASE_ADDR7_BASE,
2239     mmROT0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
2240     mmROT0_QM_QMAN_WR64_BASE_ADDR8_BASE,
2241     mmROT0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
2242     mmROT0_QM_QMAN_WR64_BASE_ADDR9_BASE,
2243     mmROT0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
2244     mmROT0_QM_QMAN_WR64_BASE_ADDR10_BASE,
2245     mmROT0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
2246     mmROT0_QM_QMAN_WR64_BASE_ADDR11_BASE,
2247     mmROT0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
2248     mmROT0_QM_QMAN_WR64_BASE_ADDR12_BASE,
2249     mmROT0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
2250     mmROT0_QM_QMAN_WR64_BASE_ADDR13_BASE,
2251     mmROT0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
2252     mmROT0_QM_QMAN_WR64_BASE_ADDR14_BASE,
2253     mmROT0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
2254     mmROT0_QM_QMAN_WR64_BASE_ADDR15_BASE,
2255     mmROT0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
2256     mmROT0_QM_ARC_CQ_PTR_LO,
2257     mmROT0_QM_ARC_CQ_PTR_LO_STS,
2258     mmROT0_QM_ARC_CQ_PTR_HI,
2259     mmROT0_QM_ARC_CQ_PTR_HI_STS,
2260     mmROT0_QM_ARB_CFG_0,
2261     mmROT0_QM_ARB_MST_QUIET_PER,
2262     mmROT0_QM_ARB_CHOICE_Q_PUSH,
2263     mmROT0_QM_ARB_WRR_WEIGHT_0,
2264     mmROT0_QM_ARB_WRR_WEIGHT_1,
2265     mmROT0_QM_ARB_WRR_WEIGHT_2,
2266     mmROT0_QM_ARB_WRR_WEIGHT_3,
2267     mmROT0_QM_ARB_BASE_LO,
2268     mmROT0_QM_ARB_BASE_HI,
2269     mmROT0_QM_ARB_MST_SLAVE_EN,
2270     mmROT0_QM_ARB_MST_SLAVE_EN_1,
2271     mmROT0_QM_ARB_MST_CRED_INC,
2272     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_0,
2273     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_1,
2274     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_2,
2275     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_3,
2276     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_4,
2277     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_5,
2278     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_6,
2279     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_7,
2280     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_8,
2281     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_9,
2282     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_10,
2283     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_11,
2284     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_12,
2285     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_13,
2286     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_14,
2287     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_15,
2288     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_16,
2289     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_17,
2290     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_18,
2291     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_19,
2292     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_20,
2293     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_21,
2294     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_22,
2295     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_23,
2296     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_24,
2297     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_25,
2298     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_26,
2299     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_27,
2300     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_28,
2301     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_29,
2302     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_30,
2303     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_31,
2304     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_32,
2305     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_33,
2306     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_34,
2307     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_35,
2308     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_36,
2309     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_37,
2310     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_38,
2311     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_39,
2312     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_40,
2313     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_41,
2314     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_42,
2315     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_43,
2316     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_44,
2317     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_45,
2318     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_46,
2319     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_47,
2320     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_48,
2321     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_49,
2322     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_50,
2323     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_51,
2324     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_52,
2325     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_53,
2326     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_54,
2327     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_55,
2328     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_56,
2329     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_57,
2330     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_58,
2331     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_59,
2332     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_60,
2333     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_61,
2334     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_62,
2335     mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_63,
2336     mmROT0_QM_ARB_SLV_ID,
2337     mmROT0_QM_ARB_SLV_MASTER_INC_CRED_OFST,
2338     mmROT0_QM_ARC_CQ_CFG0,
2339     mmROT0_QM_CQ_IFIFO_CI_0,
2340     mmROT0_QM_CQ_IFIFO_CI_1,
2341     mmROT0_QM_CQ_IFIFO_CI_2,
2342     mmROT0_QM_CQ_IFIFO_CI_3,
2343     mmROT0_QM_CQ_IFIFO_CI_4,
2344     mmROT0_QM_ARC_CQ_IFIFO_CI,
2345     mmROT0_QM_CQ_CTL_CI_0,
2346     mmROT0_QM_CQ_CTL_CI_1,
2347     mmROT0_QM_CQ_CTL_CI_2,
2348     mmROT0_QM_CQ_CTL_CI_3,
2349     mmROT0_QM_CQ_CTL_CI_4,
2350     mmROT0_QM_ARC_CQ_CTL_CI,
2351     mmROT0_QM_ARC_CQ_TSIZE,
2352     mmROT0_QM_ARC_CQ_CTL,
2353     mmROT0_QM_CP_SWITCH_WD_SET,
2354     mmROT0_QM_CP_EXT_SWITCH,
2355     mmROT0_QM_CP_PRED_0,
2356     mmROT0_QM_CP_PRED_1,
2357     mmROT0_QM_CP_PRED_2,
2358     mmROT0_QM_CP_PRED_3,
2359     mmROT0_QM_CP_PRED_4,
2360     mmROT0_QM_CP_PRED_UPEN_0,
2361     mmROT0_QM_CP_PRED_UPEN_1,
2362     mmROT0_QM_CP_PRED_UPEN_2,
2363     mmROT0_QM_CP_PRED_UPEN_3,
2364     mmROT0_QM_CP_PRED_UPEN_4,
2365     mmROT0_QM_CP_MSG_BASE0_ADDR_LO_0,
2366     mmROT0_QM_CP_MSG_BASE0_ADDR_LO_1,
2367     mmROT0_QM_CP_MSG_BASE0_ADDR_LO_2,
2368     mmROT0_QM_CP_MSG_BASE0_ADDR_LO_3,
2369     mmROT0_QM_CP_MSG_BASE0_ADDR_LO_4,
2370     mmROT0_QM_CP_MSG_BASE0_ADDR_HI_0,
2371     mmROT0_QM_CP_MSG_BASE0_ADDR_HI_1,
2372     mmROT0_QM_CP_MSG_BASE0_ADDR_HI_2,
2373     mmROT0_QM_CP_MSG_BASE0_ADDR_HI_3,
2374     mmROT0_QM_CP_MSG_BASE0_ADDR_HI_4,
2375     mmROT0_QM_CP_MSG_BASE1_ADDR_LO_0,
2376     mmROT0_QM_CP_MSG_BASE1_ADDR_LO_1,
2377     mmROT0_QM_CP_MSG_BASE1_ADDR_LO_2,
2378     mmROT0_QM_CP_MSG_BASE1_ADDR_LO_3,
2379     mmROT0_QM_CP_MSG_BASE1_ADDR_LO_4,
2380     mmROT0_QM_CP_MSG_BASE1_ADDR_HI_0,
2381     mmROT0_QM_CP_MSG_BASE1_ADDR_HI_1,
2382     mmROT0_QM_CP_MSG_BASE1_ADDR_HI_2,
2383     mmROT0_QM_CP_MSG_BASE1_ADDR_HI_3,
2384     mmROT0_QM_CP_MSG_BASE1_ADDR_HI_4,
2385     mmROT0_QM_CP_MSG_BASE2_ADDR_LO_0,
2386     mmROT0_QM_CP_MSG_BASE2_ADDR_LO_1,
2387     mmROT0_QM_CP_MSG_BASE2_ADDR_LO_2,
2388     mmROT0_QM_CP_MSG_BASE2_ADDR_LO_3,
2389     mmROT0_QM_CP_MSG_BASE2_ADDR_LO_4,
2390     mmROT0_QM_CP_MSG_BASE2_ADDR_HI_0,
2391     mmROT0_QM_CP_MSG_BASE2_ADDR_HI_1,
2392     mmROT0_QM_CP_MSG_BASE2_ADDR_HI_2,
2393     mmROT0_QM_CP_MSG_BASE2_ADDR_HI_3,
2394     mmROT0_QM_CP_MSG_BASE2_ADDR_HI_4,
2395     mmROT0_QM_CP_MSG_BASE3_ADDR_LO_0,
2396     mmROT0_QM_CP_MSG_BASE3_ADDR_LO_1,
2397     mmROT0_QM_CP_MSG_BASE3_ADDR_LO_2,
2398     mmROT0_QM_CP_MSG_BASE3_ADDR_LO_3,
2399     mmROT0_QM_CP_MSG_BASE3_ADDR_LO_4,
2400     mmROT0_QM_CP_MSG_BASE3_ADDR_HI_0,
2401     mmROT0_QM_CP_MSG_BASE3_ADDR_HI_1,
2402     mmROT0_QM_CP_MSG_BASE3_ADDR_HI_2,
2403     mmROT0_QM_CP_MSG_BASE3_ADDR_HI_3,
2404     mmROT0_QM_CP_MSG_BASE3_ADDR_HI_4,
2405     mmROT0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
2406     mmROT0_QM_ARC_CQ_CTL_MSG_BASE_LO,
2407     mmROT0_QM_CQ_IFIFO_MSG_BASE_LO,
2408     mmROT0_QM_CQ_CTL_MSG_BASE_LO,
2409     mmROT0_DESC_CONTEXT_ID,
2410     mmROT0_DESC_IN_IMG_START_ADDR_L,
2411     mmROT0_DESC_IN_IMG_START_ADDR_H,
2412     mmROT0_DESC_OUT_IMG_START_ADDR_L,
2413     mmROT0_DESC_OUT_IMG_START_ADDR_H,
2414     mmROT0_DESC_CFG,
2415     mmROT0_DESC_IM_READ_SLOPE,
2416     mmROT0_DESC_SIN_D,
2417     mmROT0_DESC_COS_D,
2418     mmROT0_DESC_IN_IMG,
2419     mmROT0_DESC_IN_STRIDE,
2420     mmROT0_DESC_IN_STRIPE,
2421     mmROT0_DESC_IN_CENTER,
2422     mmROT0_DESC_OUT_IMG,
2423     mmROT0_DESC_OUT_STRIDE,
2424     mmROT0_DESC_OUT_STRIPE,
2425     mmROT0_DESC_OUT_CENTER,
2426     mmROT0_DESC_BACKGROUND,
2427     mmROT0_DESC_CPL_MSG_EN,
2428     mmROT0_DESC_IDLE_STATE,
2429     mmROT0_DESC_CPL_MSG_ADDR,
2430     mmROT0_DESC_CPL_MSG_DATA,
2431     mmROT0_DESC_X_I_START_OFFSET,
2432     mmROT0_DESC_X_I_START_OFFSET_FLIP,
2433     mmROT0_DESC_X_I_FIRST,
2434     mmROT0_DESC_Y_I_FIRST,
2435     mmROT0_DESC_Y_I,
2436     mmROT0_DESC_OUT_STRIPE_SIZE,
2437     mmROT0_DESC_RSB_CFG_0,
2438     mmROT0_DESC_RSB_PAD_VAL,
2439     mmROT0_DESC_OWM_CFG,
2440     mmROT0_DESC_CTRL_CFG,
2441     mmROT0_DESC_PIXEL_PAD,
2442     mmROT0_DESC_PREC_SHIFT,
2443     mmROT0_DESC_MAX_VAL,
2444     mmROT0_DESC_A0_M11,
2445     mmROT0_DESC_A1_M12,
2446     mmROT0_DESC_A2,
2447     mmROT0_DESC_B0_M21,
2448     mmROT0_DESC_B1_M22,
2449     mmROT0_DESC_B2,
2450     mmROT0_DESC_C0,
2451     mmROT0_DESC_C1,
2452     mmROT0_DESC_C2,
2453     mmROT0_DESC_D0,
2454     mmROT0_DESC_D1,
2455     mmROT0_DESC_D2,
2456     mmROT0_DESC_INV_PROC_SIZE_M_1,
2457     mmROT0_DESC_MESH_IMG_START_ADDR_L,
2458     mmROT0_DESC_MESH_IMG_START_ADDR_H,
2459     mmROT0_DESC_MESH_IMG,
2460     mmROT0_DESC_MESH_STRIDE,
2461     mmROT0_DESC_MESH_STRIPE,
2462     mmROT0_DESC_MESH_CTRL,
2463     mmROT0_DESC_MESH_GH,
2464     mmROT0_DESC_MESH_GV,
2465     mmROT0_DESC_MRSB_CFG_0,
2466     mmROT0_DESC_MRSB_PAD_VAL,
2467     mmROT0_DESC_BUF_CFG,
2468     mmROT0_DESC_CID_OFFSET,
2469     mmROT0_DESC_PUSH_DESC
2470 };
2471
2472 static const u32 gaudi2_pb_psoc_global_conf[] = {
2473     mmPSOC_GLOBAL_CONF_BASE
2474 };
2475
2476 static const u32 gaudi2_pb_psoc[] = {
2477     mmPSOC_EFUSE_BASE,
2478     mmPSOC_BTL_BASE,
2479     mmPSOC_CS_TRACE_BASE,
2480     mmPSOC_DFT_EFUSE_BASE,
2481     mmPSOC_PID_BASE,
2482     mmPSOC_ARC0_CFG_BASE,
2483     mmPSOC_ARC0_MSTR_IF_RR_SHRD_HBW_BASE,
2484     mmPSOC_ARC0_AUX_BASE,
2485     mmPSOC_ARC1_CFG_BASE,
2486     mmPSOC_ARC1_MSTR_IF_RR_SHRD_HBW_BASE,
2487     mmPSOC_ARC1_AUX_BASE,
2488     mmJT_MSTR_IF_RR_SHRD_HBW_BASE,
2489     mmSMI_MSTR_IF_RR_SHRD_HBW_BASE,
2490     mmI2C_S_MSTR_IF_RR_SHRD_HBW_BASE,
2491     mmPSOC_SVID0_BASE,
2492     mmPSOC_SVID1_BASE,
2493     mmPSOC_SVID2_BASE,
2494     mmPSOC_AVS0_BASE,
2495     mmPSOC_AVS1_BASE,
2496     mmPSOC_AVS2_BASE,
2497     mmPSOC_PWM0_BASE,
2498     mmPSOC_PWM1_BASE,
2499     mmPSOC_MSTR_IF_RR_SHRD_HBW_BASE,
2500 };
2501
2502 static const u32 gaudi2_pb_pmmu[] = {
2503     mmPMMU_HBW_MMU_BASE,
2504     mmPMMU_HBW_STLB_BASE,
2505     mmPMMU_HBW_MSTR_IF_RR_SHRD_HBW_BASE,
2506     mmPMMU_PIF_BASE,
2507 };
2508
2509 static const u32 gaudi2_pb_psoc_pll[] = {
2510     mmPSOC_MME_PLL_CTRL_BASE,
2511     mmPSOC_CPU_PLL_CTRL_BASE,
2512     mmPSOC_VID_PLL_CTRL_BASE
2513 };
2514
2515 static const u32 gaudi2_pb_pmmu_pll[] = {
2516     mmPMMU_MME_PLL_CTRL_BASE,
2517     mmPMMU_VID_PLL_CTRL_BASE
2518 };
2519
2520 static const u32 gaudi2_pb_xbar_pll[] = {
2521     mmDCORE0_XBAR_DMA_PLL_CTRL_BASE,
2522     mmDCORE0_XBAR_MMU_PLL_CTRL_BASE,
2523     mmDCORE0_XBAR_IF_PLL_CTRL_BASE,
2524     mmDCORE0_XBAR_MESH_PLL_CTRL_BASE,
2525     mmDCORE1_XBAR_DMA_PLL_CTRL_BASE,
2526     mmDCORE1_XBAR_MMU_PLL_CTRL_BASE,
2527     mmDCORE1_XBAR_IF_PLL_CTRL_BASE,
2528     mmDCORE1_XBAR_MESH_PLL_CTRL_BASE,
2529     mmDCORE1_XBAR_HBM_PLL_CTRL_BASE,
2530     mmDCORE2_XBAR_DMA_PLL_CTRL_BASE,
2531     mmDCORE2_XBAR_MMU_PLL_CTRL_BASE,
2532     mmDCORE2_XBAR_IF_PLL_CTRL_BASE,
2533     mmDCORE2_XBAR_BANK_PLL_CTRL_BASE,
2534     mmDCORE2_XBAR_HBM_PLL_CTRL_BASE,
2535     mmDCORE3_XBAR_DMA_PLL_CTRL_BASE,
2536     mmDCORE3_XBAR_MMU_PLL_CTRL_BASE,
2537     mmDCORE3_XBAR_IF_PLL_CTRL_BASE,
2538     mmDCORE3_XBAR_BANK_PLL_CTRL_BASE
2539 };
2540
2541 static const u32 gaudi2_pb_xft_pll[] = {
2542     mmDCORE0_HBM_PLL_CTRL_BASE,
2543     mmDCORE0_TPC_PLL_CTRL_BASE,
2544     mmDCORE0_PCI_PLL_CTRL_BASE,
2545     mmDCORE1_HBM_PLL_CTRL_BASE,
2546     mmDCORE1_TPC_PLL_CTRL_BASE,
2547     mmDCORE1_NIC_PLL_CTRL_BASE,
2548     mmDCORE2_HBM_PLL_CTRL_BASE,
2549     mmDCORE2_TPC_PLL_CTRL_BASE,
2550     mmDCORE3_HBM_PLL_CTRL_BASE,
2551     mmDCORE3_TPC_PLL_CTRL_BASE,
2552     mmDCORE3_NIC_PLL_CTRL_BASE,
2553 };
2554
2555 static const u32 gaudi2_pb_pcie[] = {
2556     mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_BASE,
2557     mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_BASE,
2558     mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE,
2559     mmPCIE_WRAP_BASE,
2560 };
2561
2562 static const u32 gaudi2_pb_thermal_sensor0[] = {
2563     mmDCORE0_XFT_BASE,
2564     mmDCORE0_TSTDVS_BASE,
2565 };
2566
2567 static const u32 gaudi2_pb_hbm[] = {
2568     mmHBM0_MC0_BASE,
2569     mmHBM0_MC1_BASE,
2570 };
2571
2572 static const u32 gaudi2_pb_mme_qm_arc_acp_eng[] = {
2573     mmDCORE0_MME_QM_ARC_ACP_ENG_BASE,
2574 };
2575
2576 static const struct range gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs[] = {
2577     {mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_0, mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_REG},
2578 };
2579
2580 struct gaudi2_tpc_pb_data {
2581     struct hl_block_glbl_sec *glbl_sec;
2582     u32 block_array_size;
2583 };
2584
2585 static void gaudi2_config_tpcs_glbl_sec(struct hl_device *hdev, int dcore, int inst, u32 offset,
2586                     void *data)
2587 {
2588     struct gaudi2_tpc_pb_data *pb_data = (struct gaudi2_tpc_pb_data *)data;
2589
2590     hl_config_glbl_sec(hdev, gaudi2_pb_dcr0_tpc0, pb_data->glbl_sec,
2591                     offset, pb_data->block_array_size);
2592 }
2593
2594 static int gaudi2_init_pb_tpc(struct hl_device *hdev)
2595 {
2596     u32 stride, kernel_tensor_stride, qm_tensor_stride, block_array_size;
2597     struct gaudi2_tpc_pb_data tpc_pb_data;
2598     struct hl_block_glbl_sec *glbl_sec;
2599     struct iterate_module_ctx tpc_iter;
2600     int i;
2601
2602     block_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0);
2603
2604     glbl_sec = kcalloc(block_array_size, sizeof(struct hl_block_glbl_sec), GFP_KERNEL);
2605     if (!glbl_sec)
2606         return -ENOMEM;
2607
2608     kernel_tensor_stride = mmDCORE0_TPC0_CFG_KERNEL_TENSOR_1_BASE -
2609                 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE;
2610     qm_tensor_stride = mmDCORE0_TPC0_CFG_QM_TENSOR_1_BASE - mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE;
2611
2612     hl_secure_block(hdev, glbl_sec, block_array_size);
2613     hl_unsecure_registers(hdev, gaudi2_pb_dcr0_tpc0_unsecured_regs,
2614             ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_unsecured_regs),
2615             0, gaudi2_pb_dcr0_tpc0, glbl_sec,
2616             block_array_size);
2617
2618     /* Unsecure all TPC kernel tensors */
2619     for (i = 0 ; i < TPC_NUM_OF_KERNEL_TENSORS ; i++)
2620         hl_unsecure_registers(hdev,
2621             gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs,
2622             ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs),
2623             i * kernel_tensor_stride, gaudi2_pb_dcr0_tpc0,
2624             glbl_sec, block_array_size);
2625
2626     /* Unsecure all TPC QM tensors */
2627     for (i = 0 ; i < TPC_NUM_OF_QM_TENSORS ; i++)
2628         hl_unsecure_registers(hdev,
2629             gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs,
2630             ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs),
2631             i * qm_tensor_stride,
2632             gaudi2_pb_dcr0_tpc0, glbl_sec, block_array_size);
2633
2634     /* unsecure all 32 TPC QM SRF regs */
2635     stride = mmDCORE0_TPC0_CFG_QM_SRF_1 - mmDCORE0_TPC0_CFG_QM_SRF_0;
2636     for (i = 0 ; i < 32 ; i++)
2637         hl_unsecure_register(hdev, mmDCORE0_TPC0_CFG_QM_SRF_0,
2638                 i * stride, gaudi2_pb_dcr0_tpc0, glbl_sec,
2639                 block_array_size);
2640
2641     /* unsecure the 4 TPC LOCK VALUE regs */
2642     stride = mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_1 - mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0;
2643     for (i = 0 ; i < 4 ; i++)
2644         hl_unsecure_register(hdev, mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0,
2645                 i * stride, gaudi2_pb_dcr0_tpc0, glbl_sec,
2646                 block_array_size);
2647
2648     /* prepare data for TPC iterator */
2649     tpc_pb_data.glbl_sec = glbl_sec;
2650     tpc_pb_data.block_array_size = block_array_size;
2651     tpc_iter.fn = &gaudi2_config_tpcs_glbl_sec;
2652     tpc_iter.data = &tpc_pb_data;
2653     gaudi2_iterate_tpcs(hdev, &tpc_iter);
2654
2655     kfree(glbl_sec);
2656
2657     return 0;
2658 }
2659
2660 struct gaudi2_tpc_arc_pb_data {
2661     u32 unsecured_regs_arr_size;
2662     u32 arc_regs_arr_size;
2663     int rc;
2664 };
2665
2666 static void gaudi2_config_tpcs_pb_ranges(struct hl_device *hdev, int dcore, int inst, u32 offset,
2667                     void *data)
2668 {
2669     struct gaudi2_tpc_arc_pb_data *pb_data = (struct gaudi2_tpc_arc_pb_data *)data;
2670
2671     pb_data->rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, 1,
2672                     offset, gaudi2_pb_dcr0_tpc0_arc,
2673                     pb_data->arc_regs_arr_size,
2674                     gaudi2_pb_dcr0_tpc0_arc_unsecured_regs,
2675                     pb_data->unsecured_regs_arr_size);
2676 }
2677
2678 static int gaudi2_init_pb_tpc_arc(struct hl_device *hdev)
2679 {
2680     struct gaudi2_tpc_arc_pb_data tpc_arc_pb_data;
2681     struct iterate_module_ctx tpc_iter;
2682
2683     tpc_arc_pb_data.arc_regs_arr_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc);
2684     tpc_arc_pb_data.unsecured_regs_arr_size =
2685             ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc_unsecured_regs);
2686     tpc_arc_pb_data.rc = 0;
2687     tpc_iter.fn = &gaudi2_config_tpcs_pb_ranges;
2688     tpc_iter.data = &tpc_arc_pb_data;
2689     gaudi2_iterate_tpcs(hdev, &tpc_iter);
2690
2691     return tpc_arc_pb_data.rc;
2692 }
2693
2694 static int gaudi2_init_pb_sm_objs(struct hl_device *hdev)
2695 {
2696     int i, j, glbl_sec_array_len = gaudi2_pb_dcr0_sm_objs.glbl_sec_length;
2697     u32 sec_entry, *sec_array, array_base, first_sob, first_mon;
2698
2699     array_base = gaudi2_pb_dcr0_sm_objs.mm_block_base_addr +
2700                 gaudi2_pb_dcr0_sm_objs.glbl_sec_offset;
2701
2702     sec_array = kcalloc(glbl_sec_array_len, sizeof(u32), GFP_KERNEL);
2703     if (!sec_array)
2704         return -ENOMEM;
2705
2706     first_sob = GAUDI2_RESERVED_SOB_NUMBER;
2707     first_mon = GAUDI2_RESERVED_MON_NUMBER;
2708
2709     /* 8192 SOB_OBJs skipping first GAUDI2_MAX_PENDING_CS of them */
2710     for (j = i = first_sob ; i < DCORE_NUM_OF_SOB ; i++, j++)
2711         UNSET_GLBL_SEC_BIT(sec_array, j);
2712
2713     /* 2048 MON_PAY ADDR_L skipping first GAUDI2_MAX_PENDING_CS of them */
2714     for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
2715         UNSET_GLBL_SEC_BIT(sec_array, j);
2716
2717     /* 2048 MON_PAY ADDR_H skipping first GAUDI2_MAX_PENDING_CS of them */
2718     for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
2719         UNSET_GLBL_SEC_BIT(sec_array, j);
2720
2721     /* 2048 MON_PAY DATA skipping first GAUDI2_MAX_PENDING_CS of them */
2722     for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
2723         UNSET_GLBL_SEC_BIT(sec_array, j);
2724
2725     /* 2048 MON_ARM skipping first GAUDI2_MAX_PENDING_CS of them */
2726     for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
2727         UNSET_GLBL_SEC_BIT(sec_array, j);
2728
2729     /* 2048 MON_CONFIG skipping first GAUDI2_MAX_PENDING_CS of them */
2730     for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
2731         UNSET_GLBL_SEC_BIT(sec_array, j);
2732
2733     /* 2048 MON_STATUS skipping first GAUDI2_MAX_PENDING_CS of them */
2734     for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
2735         UNSET_GLBL_SEC_BIT(sec_array, j);
2736
2737     /* Unsecure selected Dcore0 registers */
2738     for (i = 0 ; i < glbl_sec_array_len ; i++) {
2739         sec_entry = array_base + i * sizeof(u32);
2740         WREG32(sec_entry, sec_array[i]);
2741     }
2742
2743     /* Unsecure Dcore1 - Dcore3 registers */
2744     memset(sec_array, -1, glbl_sec_array_len * sizeof(u32));
2745
2746     for (i = 1 ; i < NUM_OF_DCORES ; i++) {
2747         for (j = 0 ; j < glbl_sec_array_len ; j++) {
2748             sec_entry = DCORE_OFFSET * i + array_base + j * sizeof(u32);
2749             WREG32(sec_entry, sec_array[j]);
2750         }
2751     }
2752
2753     kfree(sec_array);
2754
2755     return 0;
2756 }
2757
2758 static void gaudi2_write_lbw_range_register(struct hl_device *hdev, u64 base, void *data)
2759 {
2760     u32 reg_min_offset, reg_max_offset, write_min, write_max;
2761     struct rr_config *rr_cfg = (struct rr_config *) data;
2762
2763     switch (rr_cfg->type) {
2764     case RR_TYPE_SHORT:
2765         reg_min_offset = RR_LBW_SEC_RANGE_MIN_SHORT_0_OFFSET;
2766         reg_max_offset = RR_LBW_SEC_RANGE_MAX_SHORT_0_OFFSET;
2767         break;
2768
2769     case RR_TYPE_LONG:
2770         reg_min_offset = RR_LBW_SEC_RANGE_MIN_0_OFFSET;
2771         reg_max_offset = RR_LBW_SEC_RANGE_MAX_0_OFFSET;
2772         break;
2773
2774     case RR_TYPE_SHORT_PRIV:
2775         reg_min_offset = RR_LBW_PRIV_RANGE_MIN_SHORT_0_OFFSET;
2776         reg_max_offset = RR_LBW_PRIV_RANGE_MAX_SHORT_0_OFFSET;
2777         break;
2778
2779     case RR_TYPE_LONG_PRIV:
2780         reg_min_offset = RR_LBW_PRIV_RANGE_MIN_0_OFFSET;
2781         reg_max_offset = RR_LBW_PRIV_RANGE_MAX_0_OFFSET;
2782         break;
2783
2784     default:
2785         dev_err(hdev->dev, "Invalid LBW RR type %u\n", rr_cfg->type);
2786         return;
2787     }
2788
2789     reg_min_offset += rr_cfg->index * sizeof(u32);
2790     reg_max_offset += rr_cfg->index * sizeof(u32);
2791
2792     if (rr_cfg->type == RR_TYPE_SHORT || rr_cfg->type == RR_TYPE_SHORT_PRIV) {
2793         write_min = FIELD_GET(RR_LBW_SHORT_MASK, lower_32_bits(rr_cfg->min));
2794         write_max = FIELD_GET(RR_LBW_SHORT_MASK, lower_32_bits(rr_cfg->max));
2795
2796     } else {
2797         write_min = FIELD_GET(RR_LBW_LONG_MASK, lower_32_bits(rr_cfg->min));
2798         write_max = FIELD_GET(RR_LBW_LONG_MASK, lower_32_bits(rr_cfg->max));
2799     }
2800
2801     /* Configure LBW RR:
2802      * Both RR types start blocking from base address 0x1000007FF8000000
2803      * SHORT RRs address bits [26:12]
2804      * LONG RRs address bits [26:0]
2805      */
2806     WREG32(base + reg_min_offset, write_min);
2807     WREG32(base + reg_max_offset, write_max);
2808 }
2809
2810 void gaudi2_write_rr_to_all_lbw_rtrs(struct hl_device *hdev, u8 rr_type, u32 rr_index, u64 min_val,
2811                     u64 max_val)
2812 {
2813     struct dup_block_ctx block_ctx;
2814     struct rr_config rr_cfg;
2815
2816     if ((rr_type == RR_TYPE_SHORT || rr_type == RR_TYPE_SHORT_PRIV) &&
2817                                 rr_index >= NUM_SHORT_LBW_RR) {
2818
2819         dev_err(hdev->dev, "invalid short LBW %s range register index: %u",
2820             rr_type == RR_TYPE_SHORT ? "secure" : "privileged", rr_index);
2821         return;
2822     }
2823
2824     if ((rr_type == RR_TYPE_LONG || rr_type == RR_TYPE_LONG_PRIV) &&
2825                                 rr_index >= NUM_LONG_LBW_RR) {
2826
2827         dev_err(hdev->dev, "invalid long LBW %s range register index: %u",
2828             rr_type == RR_TYPE_LONG ? "secure" : "privileged", rr_index);
2829         return;
2830     }
2831
2832     rr_cfg.type = rr_type;
2833     rr_cfg.index = rr_index;
2834     rr_cfg.min = min_val;
2835     rr_cfg.max = max_val;
2836
2837     block_ctx.instance_cfg_fn = &gaudi2_write_lbw_range_register;
2838     block_ctx.data = &rr_cfg;
2839
2840     /* SFT */
2841     block_ctx.base = mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE;
2842     block_ctx.blocks = NUM_OF_SFT;
2843     block_ctx.block_off = SFT_OFFSET;
2844     block_ctx.instances = SFT_NUM_OF_LBW_RTR;
2845     block_ctx.instance_off = SFT_LBW_RTR_OFFSET;
2846     gaudi2_init_blocks(hdev, &block_ctx);
2847
2848     /* SIF */
2849     block_ctx.base = mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE;
2850     block_ctx.blocks = NUM_OF_DCORES;
2851     block_ctx.block_off = DCORE_OFFSET;
2852     block_ctx.instances = NUM_OF_RTR_PER_DCORE;
2853     block_ctx.instance_off = DCORE_RTR_OFFSET;
2854     gaudi2_init_blocks(hdev, &block_ctx);
2855
2856     block_ctx.blocks = 1;
2857     block_ctx.block_off = 0;
2858     block_ctx.instances = 1;
2859     block_ctx.instance_off = 0;
2860
2861     /* PCIE ELBI */
2862     block_ctx.base = mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_BASE;
2863     gaudi2_init_blocks(hdev, &block_ctx);
2864
2865     /* PCIE MSTR */
2866     block_ctx.base = mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_BASE;
2867     gaudi2_init_blocks(hdev, &block_ctx);
2868
2869     /* PCIE LBW */
2870     block_ctx.base = mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_BASE;
2871     gaudi2_init_blocks(hdev, &block_ctx);
2872 }
2873
2874 static void gaudi2_init_lbw_range_registers_secure(struct hl_device *hdev)
2875 {
2876     int i;
2877
2878     /* Up to 14 14bit-address regs.
2879      *
2880      * - range 0: NIC0_CFG
2881      * - range 1: NIC1_CFG
2882      * - range 2: NIC2_CFG
2883      * - range 3: NIC3_CFG
2884      * - range 4: NIC4_CFG
2885      * - range 5: NIC5_CFG
2886      * - range 6: NIC6_CFG
2887      * - range 7: NIC7_CFG
2888      * - range 8: NIC8_CFG
2889      * - range 9: NIC9_CFG
2890      * - range 10: NIC10_CFG
2891      * - range 11: NIC11_CFG + *_DBG (not including TPC_DBG)
2892      *
2893      * If F/W security is not enabled:
2894      * - ranges 12,13: PSOC_CFG (excluding PSOC_TIMESTAMP)
2895      */
2896     u64 lbw_range_min_short[] = {
2897         mmNIC0_TX_AXUSER_BASE,
2898         mmNIC1_TX_AXUSER_BASE,
2899         mmNIC2_TX_AXUSER_BASE,
2900         mmNIC3_TX_AXUSER_BASE,
2901         mmNIC4_TX_AXUSER_BASE,
2902         mmNIC5_TX_AXUSER_BASE,
2903         mmNIC6_TX_AXUSER_BASE,
2904         mmNIC7_TX_AXUSER_BASE,
2905         mmNIC8_TX_AXUSER_BASE,
2906         mmNIC9_TX_AXUSER_BASE,
2907         mmNIC10_TX_AXUSER_BASE,
2908         mmNIC11_TX_AXUSER_BASE,
2909         mmPSOC_I2C_M0_BASE,
2910         mmPSOC_EFUSE_BASE
2911     };
2912     u64 lbw_range_max_short[] = {
2913         mmNIC0_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2914         mmNIC1_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2915         mmNIC2_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2916         mmNIC3_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2917         mmNIC4_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2918         mmNIC5_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2919         mmNIC6_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2920         mmNIC7_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2921         mmNIC8_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2922         mmNIC9_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2923         mmNIC10_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2924         mmNIC11_DBG_FUNNEL_NCH_BASE + HL_BLOCK_SIZE,
2925         mmPSOC_WDOG_BASE + HL_BLOCK_SIZE,
2926         mmSVID2_AC_BASE + HL_BLOCK_SIZE
2927     };
2928
2929     /* Up to 4 26bit-address regs.
2930      *
2931      * - range 0: TPC_DBG
2932      * - range 1: PCIE_DBI.MSIX_DOORBELL_OFF
2933      * - range 2/3: used in soft reset to block access to several blocks and are cleared here
2934      */
2935     u64 lbw_range_min_long[] = {
2936         mmDCORE0_TPC0_ROM_TABLE_BASE,
2937         mmPCIE_DBI_MSIX_DOORBELL_OFF,
2938         0x0,
2939         0x0
2940     };
2941     u64 lbw_range_max_long[] = {
2942         mmDCORE3_TPC5_EML_CS_BASE + HL_BLOCK_SIZE,
2943         mmPCIE_DBI_MSIX_DOORBELL_OFF + 0x4,
2944         0x0,
2945         0x0
2946     };
2947
2948     /* write short range registers to all lbw rtrs */
2949     for (i = 0 ; i < ARRAY_SIZE(lbw_range_min_short) ; i++) {
2950         if ((lbw_range_min_short[i] == mmPSOC_I2C_M0_BASE ||
2951                 lbw_range_min_short[i] == mmPSOC_EFUSE_BASE) &&
2952                 hdev->asic_prop.fw_security_enabled)
2953             continue;
2954
2955         gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_SHORT, i,
2956                 lbw_range_min_short[i], lbw_range_max_short[i]);
2957     }
2958
2959     /* write long range registers to all lbw rtrs */
2960     for (i = 0 ; i < ARRAY_SIZE(lbw_range_min_long) ; i++) {
2961         gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_LONG, i,
2962                 lbw_range_min_long[i], lbw_range_max_long[i]);
2963     }
2964 }
2965
2966 static void gaudi2_init_lbw_range_registers(struct hl_device *hdev)
2967 {
2968     gaudi2_init_lbw_range_registers_secure(hdev);
2969 }
2970
2971 static void gaudi2_write_hbw_range_register(struct hl_device *hdev, u64 base, void *data)
2972 {
2973     u32 min_lo_reg_offset, min_hi_reg_offset, max_lo_reg_offset, max_hi_reg_offset;
2974     struct rr_config *rr_cfg = (struct rr_config *) data;
2975     u64 val_min, val_max;
2976
2977     switch (rr_cfg->type) {
2978     case RR_TYPE_SHORT:
2979         min_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0_OFFSET;
2980         min_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0_OFFSET;
2981         max_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0_OFFSET;
2982         max_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0_OFFSET;
2983         break;
2984
2985     case RR_TYPE_LONG:
2986         min_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_LO_0_OFFSET;
2987         min_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_HI_0_OFFSET;
2988         max_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_LO_0_OFFSET;
2989         max_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_HI_0_OFFSET;
2990         break;
2991
2992     case RR_TYPE_SHORT_PRIV:
2993         min_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0_OFFSET;
2994         min_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0_OFFSET;
2995         max_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0_OFFSET;
2996         max_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0_OFFSET;
2997         break;
2998
2999     case RR_TYPE_LONG_PRIV:
3000         min_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0_OFFSET;
3001         min_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0_OFFSET;
3002         max_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0_OFFSET;
3003         max_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0_OFFSET;
3004         break;
3005
3006     default:
3007         dev_err(hdev->dev, "Invalid HBW RR type %u\n", rr_cfg->type);
3008         return;
3009     }
3010
3011     min_lo_reg_offset += rr_cfg->index * sizeof(u32);
3012     min_hi_reg_offset += rr_cfg->index * sizeof(u32);
3013     max_lo_reg_offset += rr_cfg->index * sizeof(u32);
3014     max_hi_reg_offset += rr_cfg->index * sizeof(u32);
3015
3016     if (rr_cfg->type == RR_TYPE_SHORT || rr_cfg->type == RR_TYPE_SHORT_PRIV) {
3017         val_min = FIELD_GET(RR_HBW_SHORT_HI_MASK, rr_cfg->min) |
3018                 FIELD_GET(RR_HBW_SHORT_LO_MASK, rr_cfg->min);
3019         val_max = FIELD_GET(RR_HBW_SHORT_HI_MASK, rr_cfg->max) |
3020                 FIELD_GET(RR_HBW_SHORT_LO_MASK, rr_cfg->max);
3021     } else {
3022         val_min = FIELD_GET(RR_HBW_LONG_HI_MASK, rr_cfg->min) |
3023                 FIELD_GET(RR_HBW_LONG_LO_MASK, rr_cfg->min);
3024         val_max = FIELD_GET(RR_HBW_LONG_HI_MASK, rr_cfg->max) |
3025                 FIELD_GET(RR_HBW_LONG_LO_MASK, rr_cfg->max);
3026     }
3027
3028     /* Configure HBW RR:
3029      * SHORT RRs (0x1000_<36bits>000) - HI: address bits [47:44], LO: address bits [43:12]
3030      * LONG  RRs (0x<52bits>000)      - HI: address bits [63:44], LO: address bits [43:12]
3031      */
3032     WREG32(base + min_lo_reg_offset, lower_32_bits(val_min));
3033     WREG32(base + min_hi_reg_offset, upper_32_bits(val_min));
3034     WREG32(base + max_lo_reg_offset, lower_32_bits(val_max));
3035     WREG32(base + max_hi_reg_offset, upper_32_bits(val_max));
3036 }
3037
3038 static void gaudi2_write_hbw_rr_to_all_mstr_if(struct hl_device *hdev, u8 rr_type, u32 rr_index,
3039                         u64 min_val, u64 max_val)
3040 {
3041     struct dup_block_ctx block_ctx;
3042     struct rr_config rr_cfg;
3043
3044     if ((rr_type == RR_TYPE_SHORT || rr_type == RR_TYPE_SHORT_PRIV) &&
3045                                 rr_index >= NUM_SHORT_HBW_RR) {
3046
3047         dev_err(hdev->dev, "invalid short HBW %s range register index: %u",
3048             rr_type == RR_TYPE_SHORT ? "secure" : "privileged", rr_index);
3049         return;
3050     }
3051
3052     if ((rr_type == RR_TYPE_LONG || rr_type == RR_TYPE_LONG_PRIV) &&
3053                                 rr_index >= NUM_LONG_HBW_RR) {
3054
3055         dev_err(hdev->dev, "invalid long HBW %s range register index: %u",
3056             rr_type == RR_TYPE_LONG ? "secure" : "privileged", rr_index);
3057         return;
3058     }
3059
3060     rr_cfg.type = rr_type;
3061     rr_cfg.index = rr_index;
3062     rr_cfg.min = min_val;
3063     rr_cfg.max = max_val;
3064
3065     block_ctx.instance_cfg_fn = &gaudi2_write_hbw_range_register;
3066     block_ctx.data = &rr_cfg;
3067
3068     /* SFT */
3069     block_ctx.base = mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE;
3070     block_ctx.blocks = NUM_OF_SFT;
3071     block_ctx.block_off = SFT_OFFSET;
3072     block_ctx.instances = SFT_NUM_OF_HBW_RTR;
3073     block_ctx.instance_off = SFT_IF_RTR_OFFSET;
3074     gaudi2_init_blocks(hdev, &block_ctx);
3075
3076     /* SIF */
3077     block_ctx.base = mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE;
3078     block_ctx.blocks = NUM_OF_DCORES;
3079     block_ctx.block_off = DCORE_OFFSET;
3080     block_ctx.instances = NUM_OF_RTR_PER_DCORE;
3081     block_ctx.instance_off = DCORE_RTR_OFFSET;
3082     gaudi2_init_blocks(hdev, &block_ctx);
3083
3084     /* PCIE MSTR */
3085     block_ctx.base = mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE;
3086     block_ctx.blocks = 1;
3087     block_ctx.block_off = 0;
3088     block_ctx.instances = 1;
3089     block_ctx.instance_off = 0;
3090     gaudi2_init_blocks(hdev, &block_ctx);
3091 }
3092
3093 static void gaudi2_init_hbw_range_registers(struct hl_device *hdev)
3094 {
3095     int i;
3096
3097     /* Up to 6 short RR (0x1000_<36bits>000) and 4 long RR (0x<52bits>000).
3098      *
3099      * - short range 0:
3100      *  SPI Flash, ARC0/1 ICCM/DCCM, Secure Boot ROM, PSOC_FW/Scratchpad/PCIE_FW SRAM
3101      */
3102     u64 hbw_range_min_short[] = {
3103         SPI_FLASH_BASE_ADDR
3104     };
3105     u64 hbw_range_max_short[] = {
3106         PCIE_FW_SRAM_ADDR + PCIE_FW_SRAM_SIZE
3107     };
3108
3109     for (i = 0 ; i < ARRAY_SIZE(hbw_range_min_short) ; i++) {
3110         gaudi2_write_hbw_rr_to_all_mstr_if(hdev, RR_TYPE_SHORT, i, hbw_range_min_short[i],
3111                             hbw_range_max_short[i]);
3112     }
3113 }
3114
3115 static void gaudi2_write_mmu_range_register(struct hl_device *hdev, u64 base,
3116                         struct rr_config *rr_cfg)
3117 {
3118     u32 min_lo_reg_offset, min_hi_reg_offset, max_lo_reg_offset, max_hi_reg_offset;
3119
3120     switch (rr_cfg->type) {
3121     case RR_TYPE_LONG:
3122         min_lo_reg_offset = MMU_RR_SEC_MIN_31_0_0_OFFSET;
3123         min_hi_reg_offset = MMU_RR_SEC_MIN_63_32_0_OFFSET;
3124         max_lo_reg_offset = MMU_RR_SEC_MAX_31_0_0_OFFSET;
3125         max_hi_reg_offset = MMU_RR_SEC_MAX_63_32_0_OFFSET;
3126         break;
3127
3128     case RR_TYPE_LONG_PRIV:
3129         min_lo_reg_offset = MMU_RR_PRIV_MIN_31_0_0_OFFSET;
3130         min_hi_reg_offset = MMU_RR_PRIV_MIN_63_32_0_OFFSET;
3131         max_lo_reg_offset = MMU_RR_PRIV_MAX_31_0_0_OFFSET;
3132         max_hi_reg_offset = MMU_RR_PRIV_MAX_63_32_0_OFFSET;
3133         break;
3134
3135     default:
3136         dev_err(hdev->dev, "Invalid MMU RR type %u\n", rr_cfg->type);
3137         return;
3138     }
3139
3140     min_lo_reg_offset += rr_cfg->index * sizeof(u32);
3141     min_hi_reg_offset += rr_cfg->index * sizeof(u32);
3142     max_lo_reg_offset += rr_cfg->index * sizeof(u32);
3143     max_hi_reg_offset += rr_cfg->index * sizeof(u32);
3144
3145     /* Configure MMU RR (address bits [63:0]) */
3146     WREG32(base + min_lo_reg_offset, lower_32_bits(rr_cfg->min));
3147     WREG32(base + min_hi_reg_offset, upper_32_bits(rr_cfg->min));
3148     WREG32(base + max_lo_reg_offset, lower_32_bits(rr_cfg->max));
3149     WREG32(base + max_hi_reg_offset, upper_32_bits(rr_cfg->max));
3150 }
3151
3152 static void gaudi2_init_mmu_range_registers(struct hl_device *hdev)
3153 {
3154     u32 dcore_id, hmmu_id, hmmu_base;
3155     struct rr_config rr_cfg;
3156
3157     /* Up to 8 ranges [63:0].
3158      *
3159      * - range 0: Reserved HBM area for F/W and driver
3160      */
3161
3162     /* The RRs are located after the HMMU so need to use the scrambled addresses */
3163     rr_cfg.min = hdev->asic_funcs->scramble_addr(hdev, DRAM_PHYS_BASE);
3164     rr_cfg.max = hdev->asic_funcs->scramble_addr(hdev, hdev->asic_prop.dram_user_base_address);
3165     rr_cfg.index = 0;
3166     rr_cfg.type = RR_TYPE_LONG;
3167
3168     for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {
3169         for (hmmu_id = 0 ; hmmu_id < NUM_OF_HMMU_PER_DCORE; hmmu_id++) {
3170             if (!gaudi2_is_hmmu_enabled(hdev, dcore_id, hmmu_id))
3171                 continue;
3172
3173             hmmu_base = mmDCORE0_HMMU0_MMU_BASE + dcore_id * DCORE_OFFSET +
3174                     hmmu_id * DCORE_HMMU_OFFSET;
3175
3176             gaudi2_write_mmu_range_register(hdev, hmmu_base, &rr_cfg);
3177         }
3178     }
3179 }
3180
3181 /**
3182  * gaudi2_init_range_registers -
3183  * Initialize range registers of all initiators
3184  *
3185  * @hdev: pointer to hl_device structure
3186  */
3187 static void gaudi2_init_range_registers(struct hl_device *hdev)
3188 {
3189     gaudi2_init_lbw_range_registers(hdev);
3190     gaudi2_init_hbw_range_registers(hdev);
3191     gaudi2_init_mmu_range_registers(hdev);
3192 }
3193
3194 /**
3195  * gaudi2_init_protection_bits -
3196  * Initialize protection bits of specific registers
3197  *
3198  * @hdev: pointer to hl_device structure
3199  *
3200  * All protection bits are 1 by default, means not protected. Need to set to 0
3201  * each bit that belongs to a protected register.
3202  *
3203  */
3204 static int gaudi2_init_protection_bits(struct hl_device *hdev)
3205 {
3206     struct asic_fixed_properties *prop = &hdev->asic_prop;
3207     u32 instance_offset;
3208     int rc = 0;
3209     u8 i;
3210
3211     /* SFT */
3212     instance_offset = mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE;
3213     rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
3214             gaudi2_pb_sft0, ARRAY_SIZE(gaudi2_pb_sft0),
3215             NULL, HL_PB_NA);
3216
3217     /* HIF */
3218     instance_offset = mmDCORE0_HIF1_BASE - mmDCORE0_HIF0_BASE;
3219     rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3220             NUM_OF_HIF_PER_DCORE, instance_offset,
3221             gaudi2_pb_dcr0_hif, ARRAY_SIZE(gaudi2_pb_dcr0_hif),
3222             NULL, HL_PB_NA, prop->hmmu_hif_enabled_mask);
3223
3224     /* RTR */
3225     instance_offset = mmDCORE0_RTR1_CTRL_BASE - mmDCORE0_RTR0_CTRL_BASE;
3226     rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
3227             gaudi2_pb_dcr0_rtr0, ARRAY_SIZE(gaudi2_pb_dcr0_rtr0),
3228             NULL, HL_PB_NA);
3229
3230     /* HMMU */
3231     rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3232             NUM_OF_HMMU_PER_DCORE, DCORE_HMMU_OFFSET,
3233             gaudi2_pb_dcr0_hmmu0, ARRAY_SIZE(gaudi2_pb_dcr0_hmmu0),
3234             NULL, HL_PB_NA, prop->hmmu_hif_enabled_mask);
3235
3236     /* CPU.
3237      * Except for CPU_IF, skip when security is enabled in F/W, because the blocks are protected
3238      * by privileged RR.
3239      */
3240     rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3241             HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3242             gaudi2_pb_cpu_if, ARRAY_SIZE(gaudi2_pb_cpu_if),
3243             NULL, HL_PB_NA);
3244
3245     if (!hdev->asic_prop.fw_security_enabled)
3246         rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3247                 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3248                 gaudi2_pb_cpu, ARRAY_SIZE(gaudi2_pb_cpu),
3249                 NULL, HL_PB_NA);
3250
3251     /* KDMA */
3252     rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3253             HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3254             gaudi2_pb_kdma, ARRAY_SIZE(gaudi2_pb_kdma),
3255             NULL, HL_PB_NA);
3256
3257     /* PDMA */
3258     instance_offset = mmPDMA1_CORE_BASE - mmPDMA0_CORE_BASE;
3259     rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,
3260             gaudi2_pb_pdma0, ARRAY_SIZE(gaudi2_pb_pdma0),
3261             gaudi2_pb_pdma0_unsecured_regs,
3262             ARRAY_SIZE(gaudi2_pb_pdma0_unsecured_regs));
3263
3264     /* ARC PDMA */
3265     rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, 2,
3266             instance_offset, gaudi2_pb_pdma0_arc,
3267             ARRAY_SIZE(gaudi2_pb_pdma0_arc),
3268             gaudi2_pb_pdma0_arc_unsecured_regs,
3269             ARRAY_SIZE(gaudi2_pb_pdma0_arc_unsecured_regs));
3270
3271     /* EDMA */
3272     instance_offset = mmDCORE0_EDMA1_CORE_BASE - mmDCORE0_EDMA0_CORE_BASE;
3273     rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
3274             instance_offset, gaudi2_pb_dcr0_edma0,
3275             ARRAY_SIZE(gaudi2_pb_dcr0_edma0),
3276             gaudi2_pb_dcr0_edma0_unsecured_regs,
3277             ARRAY_SIZE(gaudi2_pb_dcr0_edma0_unsecured_regs),
3278             prop->edma_enabled_mask);
3279
3280     /* ARC EDMA */
3281     rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
3282             instance_offset, gaudi2_pb_dcr0_edma0_arc,
3283             ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc),
3284             gaudi2_pb_dcr0_edma0_arc_unsecured_regs,
3285             ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc_unsecured_regs),
3286             prop->edma_enabled_mask);
3287
3288     /* MME */
3289     instance_offset = mmDCORE0_MME_SBTE1_BASE - mmDCORE0_MME_SBTE0_BASE;
3290
3291     for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {
3292         /* MME SBTE */
3293         rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i), 5,
3294                 instance_offset, gaudi2_pb_dcr0_mme_sbte,
3295                 ARRAY_SIZE(gaudi2_pb_dcr0_mme_sbte), NULL,
3296                 HL_PB_NA);
3297
3298         /* MME */
3299         rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3300                 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3301                 gaudi2_pb_dcr0_mme_eng,
3302                 ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng),
3303                 gaudi2_pb_dcr0_mme_eng_unsecured_regs,
3304                 ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng_unsecured_regs));
3305     }
3306
3307     /*
3308      * we have special iteration for case in which we would like to
3309      * configure stubbed MME's ARC/QMAN
3310      */
3311     for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {
3312         /* MME QM */
3313         rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3314                 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3315                 gaudi2_pb_dcr0_mme_qm,
3316                 ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm),
3317                 gaudi2_pb_dcr0_mme_qm_unsecured_regs,
3318                 ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm_unsecured_regs));
3319
3320         /* ARC MME */
3321         rc |= hl_init_pb_ranges_single_dcore(hdev, (DCORE_OFFSET * i),
3322             HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3323             gaudi2_pb_dcr0_mme_arc,
3324             ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc),
3325             gaudi2_pb_dcr0_mme_arc_unsecured_regs,
3326             ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc_unsecured_regs));
3327     }
3328
3329     /* MME QM ARC ACP ENG */
3330     rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3331             HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3332             gaudi2_pb_mme_qm_arc_acp_eng,
3333             ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng),
3334             gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs,
3335             ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs),
3336             (BIT(NUM_OF_DCORES * NUM_OF_MME_PER_DCORE) - 1));
3337
3338     /* TPC */
3339     rc |= gaudi2_init_pb_tpc(hdev);
3340     rc |= gaudi2_init_pb_tpc_arc(hdev);
3341
3342     /* SRAM */
3343     instance_offset = mmDCORE0_SRAM1_BANK_BASE - mmDCORE0_SRAM0_BANK_BASE;
3344     rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
3345             gaudi2_pb_dcr0_sram0, ARRAY_SIZE(gaudi2_pb_dcr0_sram0),
3346             NULL, HL_PB_NA);
3347
3348     /* Sync Manager MSTR IF */
3349     rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3350             HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3351             gaudi2_pb_dcr0_sm_mstr_if,
3352             ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if),
3353             NULL, HL_PB_NA);
3354
3355     /* Sync Manager GLBL */
3356
3357     /* Unsecure all CQ registers */
3358     rc |= hl_init_pb_ranges(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3359             HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3360             gaudi2_pb_dcr0_sm_glbl,
3361             ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl),
3362             gaudi2_pb_dcr_x_sm_glbl_unsecured_regs,
3363             ARRAY_SIZE(gaudi2_pb_dcr_x_sm_glbl_unsecured_regs));
3364
3365     /* Secure Dcore0 CQ0 registers */
3366     rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA,
3367             HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3368             gaudi2_pb_dcr0_sm_glbl,
3369             ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl),
3370             gaudi2_pb_dcr0_sm_glbl_unsecured_regs,
3371             ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl_unsecured_regs));
3372
3373     /* PSOC.
3374      * Except for PSOC_GLOBAL_CONF, skip when security is enabled in F/W, because the blocks are
3375      * protected by privileged RR.
3376      */
3377     rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3378             HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3379             gaudi2_pb_psoc_global_conf, ARRAY_SIZE(gaudi2_pb_psoc_global_conf),
3380             NULL, HL_PB_NA);
3381
3382     if (!hdev->asic_prop.fw_security_enabled)
3383         rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3384                 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3385                 gaudi2_pb_psoc, ARRAY_SIZE(gaudi2_pb_psoc),
3386                 NULL, HL_PB_NA);
3387
3388     /* PMMU */
3389     rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3390             HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3391             gaudi2_pb_pmmu, ARRAY_SIZE(gaudi2_pb_pmmu),
3392             NULL, HL_PB_NA);
3393
3394     /* PLL.
3395      * Skip PSOC/XFT PLL when security is enabled in F/W, because these blocks are protected by
3396      * privileged RR.
3397      */
3398     rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3399             HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3400             gaudi2_pb_pmmu_pll, ARRAY_SIZE(gaudi2_pb_pmmu_pll),
3401             NULL, HL_PB_NA);
3402     rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3403             HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3404             gaudi2_pb_xbar_pll, ARRAY_SIZE(gaudi2_pb_xbar_pll),
3405             NULL, HL_PB_NA);
3406
3407     if (!hdev->asic_prop.fw_security_enabled) {
3408         rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3409                 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3410                 gaudi2_pb_psoc_pll, ARRAY_SIZE(gaudi2_pb_psoc_pll),
3411                 NULL, HL_PB_NA);
3412         rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3413                 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3414                 gaudi2_pb_xft_pll, ARRAY_SIZE(gaudi2_pb_xft_pll),
3415                 NULL, HL_PB_NA);
3416     }
3417
3418     /* PCIE */
3419     rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3420             HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3421             gaudi2_pb_pcie, ARRAY_SIZE(gaudi2_pb_pcie),
3422             NULL, HL_PB_NA);
3423
3424     /* Thermal Sensor.
3425      * Skip when security is enabled in F/W, because the blocks are protected by privileged RR.
3426      */
3427     if (!hdev->asic_prop.fw_security_enabled) {
3428         instance_offset = mmDCORE1_XFT_BASE - mmDCORE0_XFT_BASE;
3429         rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
3430                 gaudi2_pb_thermal_sensor0,
3431                 ARRAY_SIZE(gaudi2_pb_thermal_sensor0), NULL, HL_PB_NA);
3432     }
3433
3434     /* HBM */
3435     /* Temporarily skip until SW-63348 is solved
3436      * instance_offset = mmHBM1_MC0_BASE - mmHBM0_MC0_BASE;
3437      * rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, GAUDI2_HBM_NUM,
3438      *      instance_offset, gaudi2_pb_hbm,
3439      *      ARRAY_SIZE(gaudi2_pb_hbm), NULL, HL_PB_NA,
3440      *      prop->dram_enabled_mask);
3441      */
3442
3443     /* Scheduler ARCs */
3444     instance_offset = mmARC_FARM_ARC1_AUX_BASE - mmARC_FARM_ARC0_AUX_BASE;
3445     rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA,
3446             NUM_OF_ARC_FARMS_ARC,
3447             instance_offset, gaudi2_pb_arc_sched,
3448             ARRAY_SIZE(gaudi2_pb_arc_sched),
3449             gaudi2_pb_arc_sched_unsecured_regs,
3450             ARRAY_SIZE(gaudi2_pb_arc_sched_unsecured_regs));
3451
3452     /* XBAR MIDs */
3453     instance_offset = mmXBAR_MID_1_BASE - mmXBAR_MID_0_BASE;
3454     rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
3455             instance_offset, gaudi2_pb_xbar_mid,
3456             ARRAY_SIZE(gaudi2_pb_xbar_mid),
3457             gaudi2_pb_xbar_mid_unsecured_regs,
3458             ARRAY_SIZE(gaudi2_pb_xbar_mid_unsecured_regs));
3459
3460     /* XBAR EDGEs */
3461     instance_offset = mmXBAR_EDGE_1_BASE - mmXBAR_EDGE_0_BASE;
3462     rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
3463             instance_offset, gaudi2_pb_xbar_edge,
3464             ARRAY_SIZE(gaudi2_pb_xbar_edge),
3465             gaudi2_pb_xbar_edge_unsecured_regs,
3466             ARRAY_SIZE(gaudi2_pb_xbar_edge_unsecured_regs),
3467             prop->xbar_edge_enabled_mask);
3468
3469     /* NIC */
3470     rc |= hl_init_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET,
3471             HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3472             gaudi2_pb_nic0, ARRAY_SIZE(gaudi2_pb_nic0),
3473             NULL, HL_PB_NA, hdev->nic_ports_mask);
3474
3475     /* NIC QM and QPC */
3476     rc |= hl_init_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET,
3477             NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET,
3478             gaudi2_pb_nic0_qm_qpc, ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc),
3479             gaudi2_pb_nic0_qm_qpc_unsecured_regs,
3480             ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc_unsecured_regs),
3481             hdev->nic_ports_mask);
3482
3483     /* NIC QM ARC */
3484     rc |= hl_init_pb_ranges_with_mask(hdev, NIC_NUMBER_OF_MACROS,
3485             NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET,
3486             gaudi2_pb_nic0_qm_arc_aux0,
3487             ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0),
3488             gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs,
3489             ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs),
3490             hdev->nic_ports_mask);
3491
3492     /* NIC UMR */
3493     rc |= hl_init_pb_ranges_with_mask(hdev, NIC_NUMBER_OF_MACROS,
3494             NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET,
3495             gaudi2_pb_nic0_umr,
3496             ARRAY_SIZE(gaudi2_pb_nic0_umr),
3497             gaudi2_pb_nic0_umr_unsecured_regs,
3498             ARRAY_SIZE(gaudi2_pb_nic0_umr_unsecured_regs),
3499             hdev->nic_ports_mask);
3500
3501     /* Rotators */
3502     instance_offset = mmROT1_BASE - mmROT0_BASE;
3503     rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT,
3504             instance_offset, gaudi2_pb_rot0,
3505             ARRAY_SIZE(gaudi2_pb_rot0),
3506             gaudi2_pb_rot0_unsecured_regs,
3507             ARRAY_SIZE(gaudi2_pb_rot0_unsecured_regs),
3508             (BIT(NUM_OF_ROT) - 1));
3509
3510     /* Rotators ARCS */
3511     rc |= hl_init_pb_ranges_with_mask(hdev, HL_PB_SHARED,
3512             HL_PB_NA, NUM_OF_ROT, instance_offset,
3513             gaudi2_pb_rot0_arc, ARRAY_SIZE(gaudi2_pb_rot0_arc),
3514             gaudi2_pb_rot0_arc_unsecured_regs,
3515             ARRAY_SIZE(gaudi2_pb_rot0_arc_unsecured_regs),
3516             (BIT(NUM_OF_ROT) - 1));
3517
3518     rc |= gaudi2_init_pb_sm_objs(hdev);
3519
3520     return rc;
3521 }
3522
3523 /**
3524  * gaudi2_init_security - Initialize security model
3525  *
3526  * @hdev: pointer to hl_device structure
3527  *
3528  * Initialize the security model of the device
3529  * That includes range registers and protection bit per register.
3530  */
3531 int gaudi2_init_security(struct hl_device *hdev)
3532 {
3533     int rc;
3534
3535     rc = gaudi2_init_protection_bits(hdev);
3536     if (rc)
3537         return rc;
3538
3539     gaudi2_init_range_registers(hdev);
3540
3541     return 0;
3542 }
3543
3544 struct gaudi2_ack_pb_tpc_data {
3545     u32 tpc_regs_array_size;
3546     u32 arc_tpc_regs_array_size;
3547 };
3548
3549 static void gaudi2_ack_pb_tpc_config(struct hl_device *hdev, int dcore, int inst, u32 offset,
3550                     void *data)
3551 {
3552     struct gaudi2_ack_pb_tpc_data *pb_data = (struct gaudi2_ack_pb_tpc_data *)data;
3553
3554     hl_ack_pb_single_dcore(hdev, offset, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3555                 gaudi2_pb_dcr0_tpc0, pb_data->tpc_regs_array_size);
3556
3557     hl_ack_pb_single_dcore(hdev, offset, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3558                 gaudi2_pb_dcr0_tpc0_arc, pb_data->arc_tpc_regs_array_size);
3559 }
3560
3561 static void gaudi2_ack_pb_tpc(struct hl_device *hdev)
3562 {
3563     struct iterate_module_ctx tpc_iter = {
3564         .fn = &gaudi2_ack_pb_tpc_config,
3565     };
3566     struct gaudi2_ack_pb_tpc_data data;
3567
3568     data.tpc_regs_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0);
3569     data.arc_tpc_regs_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc);
3570     tpc_iter.data = &data;
3571
3572     gaudi2_iterate_tpcs(hdev, &tpc_iter);
3573 }
3574
3575 /**
3576  * gaudi2_ack_protection_bits_errors - scan all blocks having protection bits
3577  * and for every protection error found, display the appropriate error message
3578  * and clear the error.
3579  *
3580  * @hdev: pointer to hl_device structure
3581  *
3582  * All protection bits are 1 by default, means not protected. Need to set to 0
3583  * each bit that belongs to a protected register.
3584  *
3585  */
3586 void gaudi2_ack_protection_bits_errors(struct hl_device *hdev)
3587 {
3588     struct asic_fixed_properties *prop = &hdev->asic_prop;
3589     u32 instance_offset;
3590     u8 i;
3591
3592     /* SFT */
3593     instance_offset = mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE;
3594     hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
3595             gaudi2_pb_sft0, ARRAY_SIZE(gaudi2_pb_sft0));
3596
3597     /* HIF */
3598     instance_offset = mmDCORE0_HIF1_BASE - mmDCORE0_HIF0_BASE;
3599     hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3600             NUM_OF_HIF_PER_DCORE, instance_offset,
3601             gaudi2_pb_dcr0_hif, ARRAY_SIZE(gaudi2_pb_dcr0_hif),
3602             prop->hmmu_hif_enabled_mask);
3603
3604     /* RTR */
3605     instance_offset = mmDCORE0_RTR1_CTRL_BASE - mmDCORE0_RTR0_CTRL_BASE;
3606     hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
3607             gaudi2_pb_dcr0_rtr0, ARRAY_SIZE(gaudi2_pb_dcr0_rtr0));
3608
3609     /* HMMU */
3610     hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3611             NUM_OF_HMMU_PER_DCORE, DCORE_HMMU_OFFSET,
3612             gaudi2_pb_dcr0_hmmu0, ARRAY_SIZE(gaudi2_pb_dcr0_hmmu0),
3613             prop->hmmu_hif_enabled_mask);
3614
3615     /* CPU.
3616      * Except for CPU_IF, skip when security is enabled in F/W, because the blocks are protected
3617      * by privileged RR.
3618      */
3619     hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3620             gaudi2_pb_cpu_if, ARRAY_SIZE(gaudi2_pb_cpu_if));
3621     if (!hdev->asic_prop.fw_security_enabled)
3622         hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3623                 gaudi2_pb_cpu, ARRAY_SIZE(gaudi2_pb_cpu));
3624
3625     /* KDMA */
3626     hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3627             gaudi2_pb_kdma, ARRAY_SIZE(gaudi2_pb_kdma));
3628
3629     /* PDMA */
3630     instance_offset = mmPDMA1_CORE_BASE - mmPDMA0_CORE_BASE;
3631     hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,
3632             gaudi2_pb_pdma0, ARRAY_SIZE(gaudi2_pb_pdma0));
3633
3634     /* ARC PDMA */
3635     hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,
3636             gaudi2_pb_pdma0_arc, ARRAY_SIZE(gaudi2_pb_pdma0_arc));
3637
3638     /* EDMA */
3639     instance_offset = mmDCORE0_EDMA1_CORE_BASE - mmDCORE0_EDMA0_CORE_BASE;
3640     hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
3641             instance_offset, gaudi2_pb_dcr0_edma0,
3642             ARRAY_SIZE(gaudi2_pb_dcr0_edma0),
3643             prop->edma_enabled_mask);
3644
3645     /* ARC EDMA */
3646     hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
3647             instance_offset, gaudi2_pb_dcr0_edma0_arc,
3648             ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc),
3649             prop->edma_enabled_mask);
3650
3651     /* MME */
3652     instance_offset = mmDCORE0_MME_SBTE1_BASE - mmDCORE0_MME_SBTE0_BASE;
3653
3654     for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {
3655         /* MME SBTE */
3656         hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i), 5,
3657                 instance_offset, gaudi2_pb_dcr0_mme_sbte,
3658                 ARRAY_SIZE(gaudi2_pb_dcr0_mme_sbte));
3659
3660         /* MME */
3661         hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3662                 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3663                 gaudi2_pb_dcr0_mme_eng,
3664                 ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng));
3665     }
3666
3667     /*
3668      * we have special iteration for case in which we would like to
3669      * configure stubbed MME's ARC/QMAN
3670      */
3671     for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {
3672         /* MME QM */
3673         hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3674                 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3675                 gaudi2_pb_dcr0_mme_qm,
3676                 ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm));
3677
3678         /* ARC MME */
3679         hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3680                 HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3681                 gaudi2_pb_dcr0_mme_arc,
3682                 ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc));
3683     }
3684
3685     /* MME QM ARC ACP ENG */
3686     hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3687             HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3688             gaudi2_pb_mme_qm_arc_acp_eng,
3689             ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng),
3690             (BIT(NUM_OF_DCORES * NUM_OF_MME_PER_DCORE) - 1));
3691
3692     /* TPC */
3693     gaudi2_ack_pb_tpc(hdev);
3694
3695     /* SRAM */
3696     instance_offset = mmDCORE0_SRAM1_BANK_BASE - mmDCORE0_SRAM0_BANK_BASE;
3697     hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
3698             gaudi2_pb_dcr0_sram0, ARRAY_SIZE(gaudi2_pb_dcr0_sram0));
3699
3700     /* Sync Manager MSTR IF */
3701     hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3702             gaudi2_pb_dcr0_sm_mstr_if, ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if));
3703
3704     /* Sync Manager */
3705     hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3706             gaudi2_pb_dcr0_sm_glbl, ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl));
3707
3708     hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3709             gaudi2_pb_dcr0_sm_mstr_if, ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if));
3710
3711     /* PSOC.
3712      * Except for PSOC_GLOBAL_CONF, skip when security is enabled in F/W, because the blocks are
3713      * protected by privileged RR.
3714      */
3715     hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3716             gaudi2_pb_psoc_global_conf, ARRAY_SIZE(gaudi2_pb_psoc_global_conf));
3717     if (!hdev->asic_prop.fw_security_enabled)
3718         hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3719                 gaudi2_pb_psoc, ARRAY_SIZE(gaudi2_pb_psoc));
3720
3721     /* PMMU */
3722     hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3723             gaudi2_pb_pmmu, ARRAY_SIZE(gaudi2_pb_pmmu));
3724
3725     /* PLL.
3726      * Skip PSOC/XFT PLL when security is enabled in F/W, because these blocks are protected by
3727      * privileged RR.
3728      */
3729     hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3730             gaudi2_pb_pmmu_pll, ARRAY_SIZE(gaudi2_pb_pmmu_pll));
3731     hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3732             gaudi2_pb_xbar_pll, ARRAY_SIZE(gaudi2_pb_xbar_pll));
3733     if (!hdev->asic_prop.fw_security_enabled) {
3734         hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3735                 gaudi2_pb_psoc_pll, ARRAY_SIZE(gaudi2_pb_psoc_pll));
3736         hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3737                 gaudi2_pb_xft_pll, ARRAY_SIZE(gaudi2_pb_xft_pll));
3738     }
3739
3740     /* PCIE */
3741     hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3742             gaudi2_pb_pcie, ARRAY_SIZE(gaudi2_pb_pcie));
3743
3744     /* Thermal Sensor.
3745      * Skip when security is enabled in F/W, because the blocks are protected by privileged RR.
3746      */
3747     if (!hdev->asic_prop.fw_security_enabled) {
3748         instance_offset = mmDCORE1_XFT_BASE - mmDCORE0_XFT_BASE;
3749         hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
3750                 gaudi2_pb_thermal_sensor0, ARRAY_SIZE(gaudi2_pb_thermal_sensor0));
3751     }
3752
3753     /* HBM */
3754     instance_offset = mmHBM1_MC0_BASE - mmHBM0_MC0_BASE;
3755     hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, GAUDI2_HBM_NUM,
3756             instance_offset, gaudi2_pb_hbm,
3757             ARRAY_SIZE(gaudi2_pb_hbm), prop->dram_enabled_mask);
3758
3759     /* Scheduler ARCs */
3760     instance_offset = mmARC_FARM_ARC1_AUX_BASE - mmARC_FARM_ARC0_AUX_BASE;
3761     hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ARC_FARMS_ARC,
3762             instance_offset, gaudi2_pb_arc_sched,
3763             ARRAY_SIZE(gaudi2_pb_arc_sched));
3764
3765     /* XBAR MIDs */
3766     instance_offset = mmXBAR_MID_1_BASE - mmXBAR_MID_0_BASE;
3767     hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
3768             instance_offset, gaudi2_pb_xbar_mid,
3769             ARRAY_SIZE(gaudi2_pb_xbar_mid));
3770
3771     /* XBAR EDGEs */
3772     instance_offset = mmXBAR_EDGE_1_BASE - mmXBAR_EDGE_0_BASE;
3773     hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
3774             instance_offset, gaudi2_pb_xbar_edge,
3775             ARRAY_SIZE(gaudi2_pb_xbar_edge), prop->xbar_edge_enabled_mask);
3776
3777     /* NIC */
3778     hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3779             gaudi2_pb_nic0, ARRAY_SIZE(gaudi2_pb_nic0), hdev->nic_ports_mask);
3780
3781     /* NIC QM and QPC */
3782     hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,
3783             NIC_QM_OFFSET, gaudi2_pb_nic0_qm_qpc, ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc),
3784             hdev->nic_ports_mask);
3785
3786     /* NIC QM ARC */
3787     hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,
3788             NIC_QM_OFFSET, gaudi2_pb_nic0_qm_arc_aux0,
3789             ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0), hdev->nic_ports_mask);
3790
3791     /* NIC UMR */
3792     hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,
3793             NIC_QM_OFFSET, gaudi2_pb_nic0_umr, ARRAY_SIZE(gaudi2_pb_nic0_umr),
3794             hdev->nic_ports_mask);
3795
3796     /* Rotators */
3797     instance_offset = mmROT1_BASE - mmROT0_BASE;
3798     hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset,
3799             gaudi2_pb_rot0, ARRAY_SIZE(gaudi2_pb_rot0), (BIT(NUM_OF_ROT) - 1));
3800
3801     /* Rotators ARCS */
3802     hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset,
3803             gaudi2_pb_rot0_arc, ARRAY_SIZE(gaudi2_pb_rot0_arc), (BIT(NUM_OF_ROT) - 1));
3804 }
3805
3806 /*
3807  * Print PB security errors
3808  */
3809
3810 void gaudi2_pb_print_security_errors(struct hl_device *hdev, u32 block_addr, u32 cause,
3811                     u32 offended_addr)
3812 {
3813     int i = 0;
3814     const char *error_format =
3815         "Security error at block 0x%x, offending address 0x%x\n"
3816         "Cause 0x%x: %s %s %s %s %s %s %s %s\n";
3817     char *mcause[8] = {"Unknown", "", "", "", "", "", "", "" };
3818
3819     if (!cause)
3820         return;
3821
3822     if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD)
3823         mcause[i++] = "APB_PRIV_RD";
3824
3825     if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD)
3826         mcause[i++] = "APB_SEC_RD";
3827
3828     if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD)
3829         mcause[i++] = "APB_UNMAPPED_RD";
3830
3831     if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR)
3832         mcause[i++] = "APB_PRIV_WR";
3833
3834     if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR)
3835         mcause[i++] = "APB_SEC_WR";
3836
3837     if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR)
3838         mcause[i++] = "APB_UNMAPPED_WR";
3839
3840     if (cause & SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR)
3841         mcause[i++] = "EXT_SEC_WR";
3842
3843     if (cause & SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR)
3844         mcause[i++] = "APB_EXT_UNMAPPED_WR";
3845
3846     dev_err_ratelimited(hdev->dev, error_format, block_addr, offended_addr,
3847             cause, mcause[0], mcause[1], mcause[2], mcause[3],
3848             mcause[4], mcause[5], mcause[6], mcause[7]);
3849 }