habanalabs/gaudi2/gaudi2P.h

0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * Copyright 2020-2022 HabanaLabs, Ltd.
0004  * All Rights Reserved.
0005  *
0006  */
0007
0008 #ifndef GAUDI2P_H_
0009 #define GAUDI2P_H_
0010
0011 #include <uapi/misc/habanalabs.h>
0012 #include "../common/habanalabs.h"
0013 #include "../include/common/hl_boot_if.h"
0014 #include "../include/gaudi2/gaudi2.h"
0015 #include "../include/gaudi2/gaudi2_packets.h"
0016 #include "../include/gaudi2/gaudi2_fw_if.h"
0017 #include "../include/gaudi2/gaudi2_async_events.h"
0018 #include "../include/gaudi2/gaudi2_async_virt_events.h"
0019
0020 #define GAUDI2_LINUX_FW_FILE    "habanalabs/gaudi2/gaudi2-fit.itb"
0021 #define GAUDI2_BOOT_FIT_FILE    "habanalabs/gaudi2/gaudi2-boot-fit.itb"
0022
0023 #define MMU_PAGE_TABLES_INITIAL_SIZE    0x10000000  /* 256MB */
0024
0025 #define GAUDI2_CPU_TIMEOUT_USEC     30000000    /* 30s */
0026
0027 #define GAUDI2_FPGA_CPU_TIMEOUT     100000000   /* 100s */
0028
0029 #define NUMBER_OF_PDMA_QUEUES       2
0030 #define NUMBER_OF_EDMA_QUEUES       8
0031 #define NUMBER_OF_MME_QUEUES        4
0032 #define NUMBER_OF_TPC_QUEUES        25
0033 #define NUMBER_OF_NIC_QUEUES        24
0034 #define NUMBER_OF_ROT_QUEUES        2
0035 #define NUMBER_OF_CPU_QUEUES        1
0036
0037 #define NUMBER_OF_HW_QUEUES     ((NUMBER_OF_PDMA_QUEUES + \
0038                     NUMBER_OF_EDMA_QUEUES + \
0039                     NUMBER_OF_MME_QUEUES + \
0040                     NUMBER_OF_TPC_QUEUES + \
0041                     NUMBER_OF_NIC_QUEUES + \
0042                     NUMBER_OF_ROT_QUEUES + \
0043                     NUMBER_OF_CPU_QUEUES) * \
0044                     NUM_OF_PQ_PER_QMAN)
0045
0046 #define NUMBER_OF_QUEUES        (NUMBER_OF_CPU_QUEUES + NUMBER_OF_HW_QUEUES)
0047
0048 #define DCORE_NUM_OF_SOB        \
0049     (((mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8191 - \
0050     mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0) + 4) >> 2)
0051
0052 #define DCORE_NUM_OF_MONITORS       \
0053     (((mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2047 - \
0054     mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_0) + 4) >> 2)
0055
0056 #define NUMBER_OF_DEC       ((NUM_OF_DEC_PER_DCORE * NUM_OF_DCORES) + NUMBER_OF_PCIE_DEC)
0057
0058 /* Map all arcs dccm + arc schedulers acp blocks */
0059 #define NUM_OF_USER_ACP_BLOCKS      (NUM_OF_SCHEDULER_ARC + 2)
0060 #define NUM_OF_USER_NIC_UMR_BLOCKS  15
0061 #define NUM_OF_EXPOSED_SM_BLOCKS    ((NUM_OF_DCORES - 1) * 2)
0062 #define NUM_USER_MAPPED_BLOCKS \
0063     (NUM_ARC_CPUS + NUM_OF_USER_ACP_BLOCKS + NUMBER_OF_DEC + \
0064     NUM_OF_EXPOSED_SM_BLOCKS + \
0065     (NIC_NUMBER_OF_ENGINES * NUM_OF_USER_NIC_UMR_BLOCKS))
0066
0067 /* Within the user mapped array, decoder entries start post all the ARC related
0068  * entries
0069  */
0070 #define USR_MAPPED_BLK_DEC_START_IDX \
0071     (NUM_ARC_CPUS + NUM_OF_USER_ACP_BLOCKS + \
0072     (NIC_NUMBER_OF_ENGINES * NUM_OF_USER_NIC_UMR_BLOCKS))
0073
0074 #define USR_MAPPED_BLK_SM_START_IDX \
0075     (NUM_ARC_CPUS + NUM_OF_USER_ACP_BLOCKS + NUMBER_OF_DEC + \
0076     (NIC_NUMBER_OF_ENGINES * NUM_OF_USER_NIC_UMR_BLOCKS))
0077
0078 #define SM_OBJS_BLOCK_SIZE      (mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_0 - \
0079                      mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0)
0080
0081 #define GAUDI2_MAX_PENDING_CS       64
0082
0083 #if !IS_MAX_PENDING_CS_VALID(GAUDI2_MAX_PENDING_CS)
0084 #error "GAUDI2_MAX_PENDING_CS must be power of 2 and greater than 1"
0085 #endif
0086
0087 #define CORESIGHT_TIMEOUT_USEC          100000      /* 100 ms */
0088
0089 #define GAUDI2_PREBOOT_REQ_TIMEOUT_USEC     25000000    /* 25s */
0090
0091 #define GAUDI2_BOOT_FIT_REQ_TIMEOUT_USEC    10000000    /* 10s */
0092
0093 #define GAUDI2_NIC_CLK_FREQ         450000000ull    /* 450 MHz */
0094
0095 #define DC_POWER_DEFAULT            60000       /* 60W */
0096
0097 #define GAUDI2_HBM_NUM              6
0098
0099 #define DMA_MAX_TRANSFER_SIZE           U32_MAX
0100
0101 #define GAUDI2_DEFAULT_CARD_NAME        "HL225"
0102
0103 #define QMAN_STREAMS                4
0104 #define PQ_FETCHER_CACHE_SIZE           8
0105 #define NUM_OF_MME_SBTE_PORTS           5
0106 #define NUM_OF_MME_WB_PORTS         2
0107
0108 #define GAUDI2_ENGINE_ID_DCORE_OFFSET \
0109     (GAUDI2_DCORE1_ENGINE_ID_EDMA_0 - GAUDI2_DCORE0_ENGINE_ID_EDMA_0)
0110
0111 /* DRAM Memory Map */
0112
0113 #define CPU_FW_IMAGE_SIZE           0x10000000  /* 256MB */
0114
0115 /* This define should be used only when working in a debug mode without dram.
0116  * When working with dram, the driver size will be calculated dynamically.
0117  */
0118 #define NIC_DEFAULT_DRV_SIZE            0x20000000  /* 512MB */
0119
0120 #define CPU_FW_IMAGE_ADDR           DRAM_PHYS_BASE
0121
0122 #define NIC_NUMBER_OF_PORTS         NIC_NUMBER_OF_ENGINES
0123
0124 #define NUMBER_OF_PCIE_DEC          2
0125 #define PCIE_DEC_SHIFT              8
0126
0127 #define SRAM_USER_BASE_OFFSET           0
0128
0129 /* cluster binning */
0130 #define MAX_FAULTY_HBMS             1
0131 #define GAUDI2_XBAR_EDGE_FULL_MASK      0xF
0132 #define GAUDI2_EDMA_FULL_MASK           0xFF
0133 #define GAUDI2_DRAM_FULL_MASK           0x3F
0134
0135 /* Host virtual address space. */
0136
0137 #define VA_HOST_SPACE_PAGE_START        0xFFF0000000000000ull
0138 #define VA_HOST_SPACE_PAGE_END          0xFFF0800000000000ull /* 140TB */
0139
0140 #define VA_HOST_SPACE_HPAGE_START       0xFFF0800000000000ull
0141 #define VA_HOST_SPACE_HPAGE_END         0xFFF1000000000000ull /* 140TB */
0142
0143 #define VA_HOST_SPACE_USER_MAPPED_CB_START  0xFFF1000000000000ull
0144 #define VA_HOST_SPACE_USER_MAPPED_CB_END    0xFFF1000100000000ull /* 4GB */
0145
0146 /* 140TB */
0147 #define VA_HOST_SPACE_PAGE_SIZE     (VA_HOST_SPACE_PAGE_END - VA_HOST_SPACE_PAGE_START)
0148
0149 /* 140TB */
0150 #define VA_HOST_SPACE_HPAGE_SIZE    (VA_HOST_SPACE_HPAGE_END - VA_HOST_SPACE_HPAGE_START)
0151
0152 #define VA_HOST_SPACE_SIZE      (VA_HOST_SPACE_PAGE_SIZE + VA_HOST_SPACE_HPAGE_SIZE)
0153
0154 #define HOST_SPACE_INTERNAL_CB_SZ       SZ_2M
0155
0156 /*
0157  * HBM virtual address space
0158  * Gaudi2 has 6 HBM devices, each supporting 16GB total of 96GB at most.
0159  * No core separation is supported so we can have one chunk of virtual address
0160  * space just above the physical ones.
0161  * The virtual address space starts immediately after the end of the physical
0162  * address space which is determined at run-time.
0163  */
0164 #define VA_HBM_SPACE_END        0x1002000000000000ull
0165
0166 #define HW_CAP_PLL          BIT_ULL(0)
0167 #define HW_CAP_DRAM         BIT_ULL(1)
0168 #define HW_CAP_PMMU         BIT_ULL(2)
0169 #define HW_CAP_CPU          BIT_ULL(3)
0170 #define HW_CAP_MSIX         BIT_ULL(4)
0171
0172 #define HW_CAP_CPU_Q            BIT_ULL(5)
0173 #define HW_CAP_CPU_Q_SHIFT      5
0174
0175 #define HW_CAP_CLK_GATE         BIT_ULL(6)
0176 #define HW_CAP_KDMA         BIT_ULL(7)
0177 #define HW_CAP_SRAM_SCRAMBLER       BIT_ULL(8)
0178
0179 #define HW_CAP_DCORE0_DMMU0     BIT_ULL(9)
0180 #define HW_CAP_DCORE0_DMMU1     BIT_ULL(10)
0181 #define HW_CAP_DCORE0_DMMU2     BIT_ULL(11)
0182 #define HW_CAP_DCORE0_DMMU3     BIT_ULL(12)
0183 #define HW_CAP_DCORE1_DMMU0     BIT_ULL(13)
0184 #define HW_CAP_DCORE1_DMMU1     BIT_ULL(14)
0185 #define HW_CAP_DCORE1_DMMU2     BIT_ULL(15)
0186 #define HW_CAP_DCORE1_DMMU3     BIT_ULL(16)
0187 #define HW_CAP_DCORE2_DMMU0     BIT_ULL(17)
0188 #define HW_CAP_DCORE2_DMMU1     BIT_ULL(18)
0189 #define HW_CAP_DCORE2_DMMU2     BIT_ULL(19)
0190 #define HW_CAP_DCORE2_DMMU3     BIT_ULL(20)
0191 #define HW_CAP_DCORE3_DMMU0     BIT_ULL(21)
0192 #define HW_CAP_DCORE3_DMMU1     BIT_ULL(22)
0193 #define HW_CAP_DCORE3_DMMU2     BIT_ULL(23)
0194 #define HW_CAP_DCORE3_DMMU3     BIT_ULL(24)
0195 #define HW_CAP_DMMU_MASK        GENMASK_ULL(24, 9)
0196 #define HW_CAP_DMMU_SHIFT       9
0197 #define HW_CAP_PDMA_MASK        BIT_ULL(26)
0198 #define HW_CAP_EDMA_MASK        GENMASK_ULL(34, 27)
0199 #define HW_CAP_EDMA_SHIFT       27
0200 #define HW_CAP_MME_MASK         GENMASK_ULL(38, 35)
0201 #define HW_CAP_MME_SHIFT        35
0202 #define HW_CAP_ROT_MASK         GENMASK_ULL(40, 39)
0203 #define HW_CAP_ROT_SHIFT        39
0204 #define HW_CAP_HBM_SCRAMBLER_HW_RESET   BIT_ULL(41)
0205 #define HW_CAP_HBM_SCRAMBLER_SW_RESET   BIT_ULL(42)
0206 #define HW_CAP_HBM_SCRAMBLER_MASK   (HW_CAP_HBM_SCRAMBLER_HW_RESET | \
0207                         HW_CAP_HBM_SCRAMBLER_SW_RESET)
0208 #define HW_CAP_HBM_SCRAMBLER_SHIFT  41
0209 #define HW_CAP_RESERVED         BIT(43)
0210 #define HW_CAP_MMU_MASK         (HW_CAP_PMMU | HW_CAP_DMMU_MASK)
0211
0212 /* Range Registers */
0213 #define RR_TYPE_SHORT           0
0214 #define RR_TYPE_LONG            1
0215 #define RR_TYPE_SHORT_PRIV      2
0216 #define RR_TYPE_LONG_PRIV       3
0217 #define NUM_SHORT_LBW_RR        14
0218 #define NUM_LONG_LBW_RR         4
0219 #define NUM_SHORT_HBW_RR        6
0220 #define NUM_LONG_HBW_RR         4
0221
0222 /* RAZWI initiator coordinates- X- 5 bits, Y- 4 bits */
0223 #define RAZWI_INITIATOR_X_SHIFT     0
0224 #define RAZWI_INITIATOR_X_MASK      0x1F
0225 #define RAZWI_INITIATOR_Y_SHIFT     5
0226 #define RAZWI_INITIATOR_Y_MASK      0xF
0227
0228 #define RTR_ID_X_Y(x, y) \
0229     ((((y) & RAZWI_INITIATOR_Y_MASK) << RAZWI_INITIATOR_Y_SHIFT) | \
0230         (((x) & RAZWI_INITIATOR_X_MASK) << RAZWI_INITIATOR_X_SHIFT))
0231
0232 /* decoders have separate mask */
0233 #define HW_CAP_DEC_SHIFT        0
0234 #define HW_CAP_DEC_MASK         GENMASK_ULL(9, 0)
0235
0236 /* TPCs have separate mask */
0237 #define HW_CAP_TPC_SHIFT        0
0238 #define HW_CAP_TPC_MASK         GENMASK_ULL(24, 0)
0239
0240 /* nics have separate mask */
0241 #define HW_CAP_NIC_SHIFT        0
0242 #define HW_CAP_NIC_MASK         GENMASK_ULL(NIC_NUMBER_OF_ENGINES - 1, 0)
0243
0244 #define GAUDI2_ARC_PCI_MSB_ADDR(addr)   (((addr) & GENMASK_ULL(49, 28)) >> 28)
0245
0246 #define GAUDI2_SOB_INCREMENT_BY_ONE (FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_MASK, 1) | \
0247                     FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_MASK, 1))
0248
0249 enum gaudi2_reserved_sob_id {
0250     GAUDI2_RESERVED_SOB_CS_COMPLETION_FIRST,
0251     GAUDI2_RESERVED_SOB_CS_COMPLETION_LAST =
0252             GAUDI2_RESERVED_SOB_CS_COMPLETION_FIRST + GAUDI2_MAX_PENDING_CS - 1,
0253     GAUDI2_RESERVED_SOB_KDMA_COMPLETION,
0254     GAUDI2_RESERVED_SOB_DEC_NRM_FIRST,
0255     GAUDI2_RESERVED_SOB_DEC_NRM_LAST =
0256             GAUDI2_RESERVED_SOB_DEC_NRM_FIRST + NUMBER_OF_DEC - 1,
0257     GAUDI2_RESERVED_SOB_DEC_ABNRM_FIRST,
0258     GAUDI2_RESERVED_SOB_DEC_ABNRM_LAST =
0259             GAUDI2_RESERVED_SOB_DEC_ABNRM_FIRST + NUMBER_OF_DEC - 1,
0260     GAUDI2_RESERVED_SOB_NUMBER
0261 };
0262
0263 enum gaudi2_reserved_mon_id {
0264     GAUDI2_RESERVED_MON_CS_COMPLETION_FIRST,
0265     GAUDI2_RESERVED_MON_CS_COMPLETION_LAST =
0266             GAUDI2_RESERVED_MON_CS_COMPLETION_FIRST + GAUDI2_MAX_PENDING_CS - 1,
0267     GAUDI2_RESERVED_MON_KDMA_COMPLETION,
0268     GAUDI2_RESERVED_MON_DEC_NRM_FIRST,
0269     GAUDI2_RESERVED_MON_DEC_NRM_LAST =
0270             GAUDI2_RESERVED_MON_DEC_NRM_FIRST + 3 * NUMBER_OF_DEC - 1,
0271     GAUDI2_RESERVED_MON_DEC_ABNRM_FIRST,
0272     GAUDI2_RESERVED_MON_DEC_ABNRM_LAST =
0273             GAUDI2_RESERVED_MON_DEC_ABNRM_FIRST + 3 * NUMBER_OF_DEC - 1,
0274     GAUDI2_RESERVED_MON_NUMBER
0275 };
0276
0277 enum gaudi2_reserved_cq_id {
0278     GAUDI2_RESERVED_CQ_CS_COMPLETION,
0279     GAUDI2_RESERVED_CQ_KDMA_COMPLETION,
0280     GAUDI2_RESERVED_CQ_NUMBER
0281 };
0282
0283 /*
0284  * Gaudi2 subtitute TPCs Numbering
0285  * At most- two faulty TPCs are allowed
0286  * First replacement to a faulty TPC will be TPC24, second- TPC23
0287  */
0288 enum substitude_tpc {
0289     FAULTY_TPC_SUBTS_1_TPC_24,
0290     FAULTY_TPC_SUBTS_2_TPC_23,
0291     MAX_FAULTY_TPCS
0292 };
0293
0294 enum gaudi2_dma_core_id {
0295     DMA_CORE_ID_PDMA0, /* Dcore 0 */
0296     DMA_CORE_ID_PDMA1, /* Dcore 0 */
0297     DMA_CORE_ID_EDMA0, /* Dcore 0 */
0298     DMA_CORE_ID_EDMA1, /* Dcore 0 */
0299     DMA_CORE_ID_EDMA2, /* Dcore 1 */
0300     DMA_CORE_ID_EDMA3, /* Dcore 1 */
0301     DMA_CORE_ID_EDMA4, /* Dcore 2 */
0302     DMA_CORE_ID_EDMA5, /* Dcore 2 */
0303     DMA_CORE_ID_EDMA6, /* Dcore 3 */
0304     DMA_CORE_ID_EDMA7, /* Dcore 3 */
0305     DMA_CORE_ID_KDMA, /* Dcore 0 */
0306     DMA_CORE_ID_SIZE
0307 };
0308
0309 enum gaudi2_rotator_id {
0310     ROTATOR_ID_0,
0311     ROTATOR_ID_1,
0312     ROTATOR_ID_SIZE,
0313 };
0314
0315 enum gaudi2_mme_id {
0316     MME_ID_DCORE0,
0317     MME_ID_DCORE1,
0318     MME_ID_DCORE2,
0319     MME_ID_DCORE3,
0320     MME_ID_SIZE,
0321 };
0322
0323 enum gaudi2_tpc_id {
0324     TPC_ID_DCORE0_TPC0,
0325     TPC_ID_DCORE0_TPC1,
0326     TPC_ID_DCORE0_TPC2,
0327     TPC_ID_DCORE0_TPC3,
0328     TPC_ID_DCORE0_TPC4,
0329     TPC_ID_DCORE0_TPC5,
0330     TPC_ID_DCORE1_TPC0,
0331     TPC_ID_DCORE1_TPC1,
0332     TPC_ID_DCORE1_TPC2,
0333     TPC_ID_DCORE1_TPC3,
0334     TPC_ID_DCORE1_TPC4,
0335     TPC_ID_DCORE1_TPC5,
0336     TPC_ID_DCORE2_TPC0,
0337     TPC_ID_DCORE2_TPC1,
0338     TPC_ID_DCORE2_TPC2,
0339     TPC_ID_DCORE2_TPC3,
0340     TPC_ID_DCORE2_TPC4,
0341     TPC_ID_DCORE2_TPC5,
0342     TPC_ID_DCORE3_TPC0,
0343     TPC_ID_DCORE3_TPC1,
0344     TPC_ID_DCORE3_TPC2,
0345     TPC_ID_DCORE3_TPC3,
0346     TPC_ID_DCORE3_TPC4,
0347     TPC_ID_DCORE3_TPC5,
0348     /* the PCI TPC is placed last (mapped liked HW) */
0349     TPC_ID_DCORE0_TPC6,
0350     TPC_ID_SIZE,
0351 };
0352
0353 enum gaudi2_dec_id {
0354     DEC_ID_DCORE0_DEC0,
0355     DEC_ID_DCORE0_DEC1,
0356     DEC_ID_DCORE1_DEC0,
0357     DEC_ID_DCORE1_DEC1,
0358     DEC_ID_DCORE2_DEC0,
0359     DEC_ID_DCORE2_DEC1,
0360     DEC_ID_DCORE3_DEC0,
0361     DEC_ID_DCORE3_DEC1,
0362     DEC_ID_PCIE_VDEC0,
0363     DEC_ID_PCIE_VDEC1,
0364     DEC_ID_SIZE,
0365 };
0366
0367 enum gaudi2_hbm_id {
0368     HBM_ID0,
0369     HBM_ID1,
0370     HBM_ID2,
0371     HBM_ID3,
0372     HBM_ID4,
0373     HBM_ID5,
0374     HBM_ID_SIZE,
0375 };
0376
0377 /* specific EDMA enumeration */
0378 enum gaudi2_edma_id {
0379     EDMA_ID_DCORE0_INSTANCE0,
0380     EDMA_ID_DCORE0_INSTANCE1,
0381     EDMA_ID_DCORE1_INSTANCE0,
0382     EDMA_ID_DCORE1_INSTANCE1,
0383     EDMA_ID_DCORE2_INSTANCE0,
0384     EDMA_ID_DCORE2_INSTANCE1,
0385     EDMA_ID_DCORE3_INSTANCE0,
0386     EDMA_ID_DCORE3_INSTANCE1,
0387     EDMA_ID_SIZE,
0388 };
0389
0390 /* User interrupt count is aligned with HW CQ count.
0391  * We have 64 CQ's per dcore, CQ0 in dcore 0 is reserved for legacy mode
0392  */
0393 #define GAUDI2_NUM_USER_INTERRUPTS 255
0394
0395 enum gaudi2_irq_num {
0396     GAUDI2_IRQ_NUM_EVENT_QUEUE = GAUDI2_EVENT_QUEUE_MSIX_IDX,
0397     GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM,
0398     GAUDI2_IRQ_NUM_DCORE0_DEC0_ABNRM,
0399     GAUDI2_IRQ_NUM_DCORE0_DEC1_NRM,
0400     GAUDI2_IRQ_NUM_DCORE0_DEC1_ABNRM,
0401     GAUDI2_IRQ_NUM_DCORE1_DEC0_NRM,
0402     GAUDI2_IRQ_NUM_DCORE1_DEC0_ABNRM,
0403     GAUDI2_IRQ_NUM_DCORE1_DEC1_NRM,
0404     GAUDI2_IRQ_NUM_DCORE1_DEC1_ABNRM,
0405     GAUDI2_IRQ_NUM_DCORE2_DEC0_NRM,
0406     GAUDI2_IRQ_NUM_DCORE2_DEC0_ABNRM,
0407     GAUDI2_IRQ_NUM_DCORE2_DEC1_NRM,
0408     GAUDI2_IRQ_NUM_DCORE2_DEC1_ABNRM,
0409     GAUDI2_IRQ_NUM_DCORE3_DEC0_NRM,
0410     GAUDI2_IRQ_NUM_DCORE3_DEC0_ABNRM,
0411     GAUDI2_IRQ_NUM_DCORE3_DEC1_NRM,
0412     GAUDI2_IRQ_NUM_DCORE3_DEC1_ABNRM,
0413     GAUDI2_IRQ_NUM_SHARED_DEC0_NRM,
0414     GAUDI2_IRQ_NUM_SHARED_DEC0_ABNRM,
0415     GAUDI2_IRQ_NUM_SHARED_DEC1_NRM,
0416     GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM,
0417     GAUDI2_IRQ_NUM_COMPLETION,
0418     GAUDI2_IRQ_NUM_NIC_PORT_FIRST,
0419     GAUDI2_IRQ_NUM_NIC_PORT_LAST = (GAUDI2_IRQ_NUM_NIC_PORT_FIRST + NIC_NUMBER_OF_PORTS - 1),
0420     GAUDI2_IRQ_NUM_RESERVED_FIRST,
0421     GAUDI2_IRQ_NUM_RESERVED_LAST = (GAUDI2_MSIX_ENTRIES - GAUDI2_NUM_USER_INTERRUPTS - 1),
0422     GAUDI2_IRQ_NUM_USER_FIRST,
0423     GAUDI2_IRQ_NUM_USER_LAST = (GAUDI2_IRQ_NUM_USER_FIRST + GAUDI2_NUM_USER_INTERRUPTS - 1),
0424     GAUDI2_IRQ_NUM_LAST = (GAUDI2_MSIX_ENTRIES - 1)
0425 };
0426
0427 static_assert(GAUDI2_IRQ_NUM_USER_FIRST > GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM);
0428
0429 /**
0430  * struct dup_block_ctx - context to initialize unit instances across multiple
0431  *                        blocks where block can be either a dcore of duplicated
0432  *                        common module. this code relies on constant offsets
0433  *                        of blocks and unit instances in a block.
0434  * @instance_cfg_fn: instance specific configuration function.
0435  * @data: private configuration data.
0436  * @base: base address of the first instance in the first block.
0437  * @block_off: subsequent blocks address spacing.
0438  * @instance_off: subsequent block's instances address spacing.
0439  * @enabled_mask: mask of enabled instances (1- enabled, 0- disabled).
0440  * @blocks: number of blocks.
0441  * @instances: unit instances per block.
0442  */
0443 struct dup_block_ctx {
0444     void (*instance_cfg_fn)(struct hl_device *hdev, u64 base, void *data);
0445     void *data;
0446     u64 base;
0447     u64 block_off;
0448     u64 instance_off;
0449     u64 enabled_mask;
0450     unsigned int blocks;
0451     unsigned int instances;
0452 };
0453
0454 /**
0455  * struct gaudi2_device - ASIC specific manage structure.
0456  * @cpucp_info_get: get information on device from CPU-CP
0457  * @mapped_blocks: array that holds the base address and size of all blocks
0458  *                 the user can map.
0459  * @lfsr_rand_seeds: array of MME ACC random seeds to set.
0460  * @hw_queues_lock: protects the H/W queues from concurrent access.
0461  * @kdma_lock: protects the KDMA engine from concurrent access.
0462  * @scratchpad_kernel_address: general purpose PAGE_SIZE contiguous memory,
0463  *                             this memory region should be write-only.
0464  *                             currently used for HBW QMAN writes which is
0465  *                             redundant.
0466  * @scratchpad_bus_address: scratchpad bus address
0467  * @virt_msix_db_cpu_addr: host memory page for the virtual MSI-X doorbell.
0468  * @virt_msix_db_dma_addr: bus address of the page for the virtual MSI-X doorbell.
0469  * @dram_bar_cur_addr: current address of DRAM PCI bar.
0470  * @hw_cap_initialized: This field contains a bit per H/W engine. When that
0471  *                      engine is initialized, that bit is set by the driver to
0472  *                      signal we can use this engine in later code paths.
0473  *                      Each bit is cleared upon reset of its corresponding H/W
0474  *                      engine.
0475  * @active_hw_arc: This field contains a bit per ARC of an H/W engine with
0476  *                 exception of TPC and NIC engines. Once an engine arc is
0477  *                 initialized, its respective bit is set. Driver can uniquely
0478  *                 identify each initialized ARC and use this information in
0479  *                 later code paths. Each respective bit is cleared upon reset
0480  *                 of its corresponding ARC of the H/W engine.
0481  * @dec_hw_cap_initialized: This field contains a bit per decoder H/W engine.
0482  *                      When that engine is initialized, that bit is set by
0483  *                      the driver to signal we can use this engine in later
0484  *                      code paths.
0485  *                      Each bit is cleared upon reset of its corresponding H/W
0486  *                      engine.
0487  * @tpc_hw_cap_initialized: This field contains a bit per TPC H/W engine.
0488  *                      When that engine is initialized, that bit is set by
0489  *                      the driver to signal we can use this engine in later
0490  *                      code paths.
0491  *                      Each bit is cleared upon reset of its corresponding H/W
0492  *                      engine.
0493  * @active_tpc_arc: This field contains a bit per ARC of the TPC engines.
0494  *                  Once an engine arc is initialized, its respective bit is
0495  *                  set. Each respective bit is cleared upon reset of its
0496  *                  corresponding ARC of the TPC engine.
0497  * @nic_hw_cap_initialized: This field contains a bit per nic H/W engine.
0498  * @active_nic_arc: This field contains a bit per ARC of the NIC engines.
0499  *                  Once an engine arc is initialized, its respective bit is
0500  *                  set. Each respective bit is cleared upon reset of its
0501  *                  corresponding ARC of the NIC engine.
0502  * @hw_events: array that holds all H/W events that are defined valid.
0503  * @events_stat: array that holds histogram of all received events.
0504  * @events_stat_aggregate: same as events_stat but doesn't get cleared on reset.
0505  * @num_of_valid_hw_events: used to hold the number of valid H/W events.
0506  * @nic_ports: array that holds all NIC ports manage structures.
0507  * @nic_macros: array that holds all NIC macro manage structures.
0508  * @core_info: core info to be used by the Ethernet driver.
0509  * @aux_ops: functions for core <-> aux drivers communication.
0510  * @flush_db_fifo: flag to force flush DB FIFO after a write.
0511  * @hbm_cfg: HBM subsystem settings
0512  * @hw_queues_lock_mutex: used by simulator instead of hw_queues_lock.
0513  * @kdma_lock_mutex: used by simulator instead of kdma_lock.
0514  * @use_deprecated_event_mappings: use old event mappings which are about to be
0515  *                                 deprecated
0516  */
0517 struct gaudi2_device {
0518     int (*cpucp_info_get)(struct hl_device *hdev);
0519
0520     struct user_mapped_block    mapped_blocks[NUM_USER_MAPPED_BLOCKS];
0521     int             lfsr_rand_seeds[MME_NUM_OF_LFSR_SEEDS];
0522
0523     spinlock_t          hw_queues_lock;
0524     spinlock_t          kdma_lock;
0525
0526     void                *scratchpad_kernel_address;
0527     dma_addr_t          scratchpad_bus_address;
0528
0529     void                *virt_msix_db_cpu_addr;
0530     dma_addr_t          virt_msix_db_dma_addr;
0531
0532     u64             dram_bar_cur_addr;
0533     u64             hw_cap_initialized;
0534     u64             active_hw_arc;
0535     u64             dec_hw_cap_initialized;
0536     u64             tpc_hw_cap_initialized;
0537     u64             active_tpc_arc;
0538     u64             nic_hw_cap_initialized;
0539     u64             active_nic_arc;
0540     u32             hw_events[GAUDI2_EVENT_SIZE];
0541     u32             events_stat[GAUDI2_EVENT_SIZE];
0542     u32             events_stat_aggregate[GAUDI2_EVENT_SIZE];
0543     u32             num_of_valid_hw_events;
0544 };
0545
0546 extern const u32 gaudi2_dma_core_blocks_bases[DMA_CORE_ID_SIZE];
0547 extern const u32 gaudi2_qm_blocks_bases[GAUDI2_QUEUE_ID_SIZE];
0548 extern const u32 gaudi2_mme_acc_blocks_bases[MME_ID_SIZE];
0549 extern const u32 gaudi2_mme_ctrl_lo_blocks_bases[MME_ID_SIZE];
0550 extern const u32 edma_stream_base[NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES];
0551 extern const u32 gaudi2_rot_blocks_bases[ROTATOR_ID_SIZE];
0552
0553 void gaudi2_iterate_tpcs(struct hl_device *hdev, struct iterate_module_ctx *ctx);
0554 int gaudi2_coresight_init(struct hl_device *hdev);
0555 int gaudi2_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data);
0556 void gaudi2_halt_coresight(struct hl_device *hdev, struct hl_ctx *ctx);
0557 void gaudi2_init_blocks(struct hl_device *hdev, struct dup_block_ctx *cfg_ctx);
0558 bool gaudi2_is_hmmu_enabled(struct hl_device *hdev, int dcore_id, int hmmu_id);
0559 void gaudi2_write_rr_to_all_lbw_rtrs(struct hl_device *hdev, u8 rr_type, u32 rr_index, u64 min_val,
0560                     u64 max_val);
0561 void gaudi2_pb_print_security_errors(struct hl_device *hdev, u32 block_addr, u32 cause,
0562                     u32 offended_addr);
0563 int gaudi2_init_security(struct hl_device *hdev);
0564 void gaudi2_ack_protection_bits_errors(struct hl_device *hdev);
0565
0566 #endif /* GAUDI2P_H_ */