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0008 #include "gaudiP.h"
0009 #include "../include/gaudi/gaudi_coresight.h"
0010 #include "../include/gaudi/asic_reg/gaudi_regs.h"
0011 #include "../include/gaudi/gaudi_masks.h"
0012 #include "../include/gaudi/gaudi_reg_map.h"
0013
0014 #include <uapi/misc/habanalabs.h>
0015 #define SPMU_SECTION_SIZE MME0_ACC_SPMU_MAX_OFFSET
0016 #define SPMU_EVENT_TYPES_OFFSET 0x400
0017 #define SPMU_MAX_COUNTERS 6
0018
0019 static u64 debug_stm_regs[GAUDI_STM_LAST + 1] = {
0020 [GAUDI_STM_MME0_ACC] = mmMME0_ACC_STM_BASE,
0021 [GAUDI_STM_MME0_SBAB] = mmMME0_SBAB_STM_BASE,
0022 [GAUDI_STM_MME0_CTRL] = mmMME0_CTRL_STM_BASE,
0023 [GAUDI_STM_MME1_ACC] = mmMME1_ACC_STM_BASE,
0024 [GAUDI_STM_MME1_SBAB] = mmMME1_SBAB_STM_BASE,
0025 [GAUDI_STM_MME1_CTRL] = mmMME1_CTRL_STM_BASE,
0026 [GAUDI_STM_MME2_ACC] = mmMME2_ACC_STM_BASE,
0027 [GAUDI_STM_MME2_SBAB] = mmMME2_SBAB_STM_BASE,
0028 [GAUDI_STM_MME2_CTRL] = mmMME2_CTRL_STM_BASE,
0029 [GAUDI_STM_MME3_ACC] = mmMME3_ACC_STM_BASE,
0030 [GAUDI_STM_MME3_SBAB] = mmMME3_SBAB_STM_BASE,
0031 [GAUDI_STM_MME3_CTRL] = mmMME3_CTRL_STM_BASE,
0032 [GAUDI_STM_DMA_IF_W_S] = mmDMA_IF_W_S_STM_BASE,
0033 [GAUDI_STM_DMA_IF_E_S] = mmDMA_IF_E_S_STM_BASE,
0034 [GAUDI_STM_DMA_IF_W_N] = mmDMA_IF_W_N_STM_BASE,
0035 [GAUDI_STM_DMA_IF_E_N] = mmDMA_IF_E_N_STM_BASE,
0036 [GAUDI_STM_CPU] = mmCPU_STM_BASE,
0037 [GAUDI_STM_DMA_CH_0_CS] = mmDMA_CH_0_CS_STM_BASE,
0038 [GAUDI_STM_DMA_CH_1_CS] = mmDMA_CH_1_CS_STM_BASE,
0039 [GAUDI_STM_DMA_CH_2_CS] = mmDMA_CH_2_CS_STM_BASE,
0040 [GAUDI_STM_DMA_CH_3_CS] = mmDMA_CH_3_CS_STM_BASE,
0041 [GAUDI_STM_DMA_CH_4_CS] = mmDMA_CH_4_CS_STM_BASE,
0042 [GAUDI_STM_DMA_CH_5_CS] = mmDMA_CH_5_CS_STM_BASE,
0043 [GAUDI_STM_DMA_CH_6_CS] = mmDMA_CH_6_CS_STM_BASE,
0044 [GAUDI_STM_DMA_CH_7_CS] = mmDMA_CH_7_CS_STM_BASE,
0045 [GAUDI_STM_PCIE] = mmPCIE_STM_BASE,
0046 [GAUDI_STM_MMU_CS] = mmMMU_CS_STM_BASE,
0047 [GAUDI_STM_PSOC] = mmPSOC_STM_BASE,
0048 [GAUDI_STM_NIC0_0] = mmSTM_0_NIC0_DBG_BASE,
0049 [GAUDI_STM_NIC0_1] = mmSTM_1_NIC0_DBG_BASE,
0050 [GAUDI_STM_NIC1_0] = mmSTM_0_NIC1_DBG_BASE,
0051 [GAUDI_STM_NIC1_1] = mmSTM_1_NIC1_DBG_BASE,
0052 [GAUDI_STM_NIC2_0] = mmSTM_0_NIC2_DBG_BASE,
0053 [GAUDI_STM_NIC2_1] = mmSTM_1_NIC2_DBG_BASE,
0054 [GAUDI_STM_NIC3_0] = mmSTM_0_NIC3_DBG_BASE,
0055 [GAUDI_STM_NIC3_1] = mmSTM_1_NIC3_DBG_BASE,
0056 [GAUDI_STM_NIC4_0] = mmSTM_0_NIC4_DBG_BASE,
0057 [GAUDI_STM_NIC4_1] = mmSTM_1_NIC4_DBG_BASE,
0058 [GAUDI_STM_TPC0_EML] = mmTPC0_EML_STM_BASE,
0059 [GAUDI_STM_TPC1_EML] = mmTPC1_EML_STM_BASE,
0060 [GAUDI_STM_TPC2_EML] = mmTPC2_EML_STM_BASE,
0061 [GAUDI_STM_TPC3_EML] = mmTPC3_EML_STM_BASE,
0062 [GAUDI_STM_TPC4_EML] = mmTPC4_EML_STM_BASE,
0063 [GAUDI_STM_TPC5_EML] = mmTPC5_EML_STM_BASE,
0064 [GAUDI_STM_TPC6_EML] = mmTPC6_EML_STM_BASE,
0065 [GAUDI_STM_TPC7_EML] = mmTPC7_EML_STM_BASE
0066 };
0067
0068 static u64 debug_etf_regs[GAUDI_ETF_LAST + 1] = {
0069 [GAUDI_ETF_MME0_ACC] = mmMME0_ACC_ETF_BASE,
0070 [GAUDI_ETF_MME0_SBAB] = mmMME0_SBAB_ETF_BASE,
0071 [GAUDI_ETF_MME0_CTRL] = mmMME0_CTRL_ETF_BASE,
0072 [GAUDI_ETF_MME1_ACC] = mmMME1_ACC_ETF_BASE,
0073 [GAUDI_ETF_MME1_SBAB] = mmMME1_SBAB_ETF_BASE,
0074 [GAUDI_ETF_MME1_CTRL] = mmMME1_CTRL_ETF_BASE,
0075 [GAUDI_ETF_MME2_ACC] = mmMME2_MME2_ACC_ETF_BASE,
0076 [GAUDI_ETF_MME2_SBAB] = mmMME2_SBAB_ETF_BASE,
0077 [GAUDI_ETF_MME2_CTRL] = mmMME2_CTRL_ETF_BASE,
0078 [GAUDI_ETF_MME3_ACC] = mmMME3_ACC_ETF_BASE,
0079 [GAUDI_ETF_MME3_SBAB] = mmMME3_SBAB_ETF_BASE,
0080 [GAUDI_ETF_MME3_CTRL] = mmMME3_CTRL_ETF_BASE,
0081 [GAUDI_ETF_DMA_IF_W_S] = mmDMA_IF_W_S_ETF_BASE,
0082 [GAUDI_ETF_DMA_IF_E_S] = mmDMA_IF_E_S_ETF_BASE,
0083 [GAUDI_ETF_DMA_IF_W_N] = mmDMA_IF_W_N_ETF_BASE,
0084 [GAUDI_ETF_DMA_IF_E_N] = mmDMA_IF_E_N_ETF_BASE,
0085 [GAUDI_ETF_CPU_0] = mmCPU_ETF_0_BASE,
0086 [GAUDI_ETF_CPU_1] = mmCPU_ETF_1_BASE,
0087 [GAUDI_ETF_CPU_TRACE] = mmCPU_ETF_TRACE_BASE,
0088 [GAUDI_ETF_DMA_CH_0_CS] = mmDMA_CH_0_CS_ETF_BASE,
0089 [GAUDI_ETF_DMA_CH_1_CS] = mmDMA_CH_1_CS_ETF_BASE,
0090 [GAUDI_ETF_DMA_CH_2_CS] = mmDMA_CH_2_CS_ETF_BASE,
0091 [GAUDI_ETF_DMA_CH_3_CS] = mmDMA_CH_3_CS_ETF_BASE,
0092 [GAUDI_ETF_DMA_CH_4_CS] = mmDMA_CH_4_CS_ETF_BASE,
0093 [GAUDI_ETF_DMA_CH_5_CS] = mmDMA_CH_5_CS_ETF_BASE,
0094 [GAUDI_ETF_DMA_CH_6_CS] = mmDMA_CH_6_CS_ETF_BASE,
0095 [GAUDI_ETF_DMA_CH_7_CS] = mmDMA_CH_7_CS_ETF_BASE,
0096 [GAUDI_ETF_PCIE] = mmPCIE_ETF_BASE,
0097 [GAUDI_ETF_MMU_CS] = mmMMU_CS_ETF_BASE,
0098 [GAUDI_ETF_PSOC] = mmPSOC_ETF_BASE,
0099 [GAUDI_ETF_NIC0_0] = mmETF_0_NIC0_DBG_BASE,
0100 [GAUDI_ETF_NIC0_1] = mmETF_1_NIC0_DBG_BASE,
0101 [GAUDI_ETF_NIC1_0] = mmETF_0_NIC1_DBG_BASE,
0102 [GAUDI_ETF_NIC1_1] = mmETF_1_NIC1_DBG_BASE,
0103 [GAUDI_ETF_NIC2_0] = mmETF_0_NIC2_DBG_BASE,
0104 [GAUDI_ETF_NIC2_1] = mmETF_1_NIC2_DBG_BASE,
0105 [GAUDI_ETF_NIC3_0] = mmETF_0_NIC3_DBG_BASE,
0106 [GAUDI_ETF_NIC3_1] = mmETF_1_NIC3_DBG_BASE,
0107 [GAUDI_ETF_NIC4_0] = mmETF_0_NIC4_DBG_BASE,
0108 [GAUDI_ETF_NIC4_1] = mmETF_1_NIC4_DBG_BASE,
0109 [GAUDI_ETF_TPC0_EML] = mmTPC0_EML_ETF_BASE,
0110 [GAUDI_ETF_TPC1_EML] = mmTPC1_EML_ETF_BASE,
0111 [GAUDI_ETF_TPC2_EML] = mmTPC2_EML_ETF_BASE,
0112 [GAUDI_ETF_TPC3_EML] = mmTPC3_EML_ETF_BASE,
0113 [GAUDI_ETF_TPC4_EML] = mmTPC4_EML_ETF_BASE,
0114 [GAUDI_ETF_TPC5_EML] = mmTPC5_EML_ETF_BASE,
0115 [GAUDI_ETF_TPC6_EML] = mmTPC6_EML_ETF_BASE,
0116 [GAUDI_ETF_TPC7_EML] = mmTPC7_EML_ETF_BASE
0117 };
0118
0119 static u64 debug_funnel_regs[GAUDI_FUNNEL_LAST + 1] = {
0120 [GAUDI_FUNNEL_MME0_ACC] = mmMME0_ACC_FUNNEL_BASE,
0121 [GAUDI_FUNNEL_MME1_ACC] = mmMME1_ACC_FUNNEL_BASE,
0122 [GAUDI_FUNNEL_MME2_ACC] = mmMME2_ACC_FUNNEL_BASE,
0123 [GAUDI_FUNNEL_MME3_ACC] = mmMME3_ACC_FUNNEL_BASE,
0124 [GAUDI_FUNNEL_SRAM_Y0_X0] = mmSRAM_Y0_X0_FUNNEL_BASE,
0125 [GAUDI_FUNNEL_SRAM_Y0_X1] = mmSRAM_Y0_X1_FUNNEL_BASE,
0126 [GAUDI_FUNNEL_SRAM_Y0_X2] = mmSRAM_Y0_X2_FUNNEL_BASE,
0127 [GAUDI_FUNNEL_SRAM_Y0_X3] = mmSRAM_Y0_X3_FUNNEL_BASE,
0128 [GAUDI_FUNNEL_SRAM_Y0_X4] = mmSRAM_Y0_X4_FUNNEL_BASE,
0129 [GAUDI_FUNNEL_SRAM_Y0_X5] = mmSRAM_Y0_X5_FUNNEL_BASE,
0130 [GAUDI_FUNNEL_SRAM_Y0_X6] = mmSRAM_Y0_X6_FUNNEL_BASE,
0131 [GAUDI_FUNNEL_SRAM_Y0_X7] = mmSRAM_Y0_X7_FUNNEL_BASE,
0132 [GAUDI_FUNNEL_SRAM_Y1_X0] = mmSRAM_Y1_X0_FUNNEL_BASE,
0133 [GAUDI_FUNNEL_SRAM_Y1_X1] = mmSRAM_Y1_X1_FUNNEL_BASE,
0134 [GAUDI_FUNNEL_SRAM_Y1_X2] = mmSRAM_Y1_X2_FUNNEL_BASE,
0135 [GAUDI_FUNNEL_SRAM_Y1_X3] = mmSRAM_Y1_X3_FUNNEL_BASE,
0136 [GAUDI_FUNNEL_SRAM_Y1_X4] = mmSRAM_Y1_X4_FUNNEL_BASE,
0137 [GAUDI_FUNNEL_SRAM_Y1_X5] = mmSRAM_Y1_X5_FUNNEL_BASE,
0138 [GAUDI_FUNNEL_SRAM_Y1_X6] = mmSRAM_Y1_X6_FUNNEL_BASE,
0139 [GAUDI_FUNNEL_SRAM_Y1_X7] = mmSRAM_Y1_X7_FUNNEL_BASE,
0140 [GAUDI_FUNNEL_SRAM_Y2_X0] = mmSRAM_Y2_X0_FUNNEL_BASE,
0141 [GAUDI_FUNNEL_SRAM_Y2_X1] = mmSRAM_Y2_X1_FUNNEL_BASE,
0142 [GAUDI_FUNNEL_SRAM_Y2_X2] = mmSRAM_Y2_X2_FUNNEL_BASE,
0143 [GAUDI_FUNNEL_SRAM_Y2_X3] = mmSRAM_Y2_X3_FUNNEL_BASE,
0144 [GAUDI_FUNNEL_SRAM_Y2_X4] = mmSRAM_Y2_X4_FUNNEL_BASE,
0145 [GAUDI_FUNNEL_SRAM_Y2_X5] = mmSRAM_Y2_X5_FUNNEL_BASE,
0146 [GAUDI_FUNNEL_SRAM_Y2_X6] = mmSRAM_Y2_X6_FUNNEL_BASE,
0147 [GAUDI_FUNNEL_SRAM_Y2_X7] = mmSRAM_Y2_X7_FUNNEL_BASE,
0148 [GAUDI_FUNNEL_SRAM_Y3_X0] = mmSRAM_Y3_X0_FUNNEL_BASE,
0149 [GAUDI_FUNNEL_SRAM_Y3_X1] = mmSRAM_Y3_X1_FUNNEL_BASE,
0150 [GAUDI_FUNNEL_SRAM_Y3_X2] = mmSRAM_Y3_X2_FUNNEL_BASE,
0151 [GAUDI_FUNNEL_SRAM_Y3_X4] = mmSRAM_Y3_X4_FUNNEL_BASE,
0152 [GAUDI_FUNNEL_SRAM_Y3_X3] = mmSRAM_Y3_X3_FUNNEL_BASE,
0153 [GAUDI_FUNNEL_SRAM_Y3_X5] = mmSRAM_Y3_X5_FUNNEL_BASE,
0154 [GAUDI_FUNNEL_SRAM_Y3_X6] = mmSRAM_Y3_X6_FUNNEL_BASE,
0155 [GAUDI_FUNNEL_SRAM_Y3_X7] = mmSRAM_Y3_X7_FUNNEL_BASE,
0156 [GAUDI_FUNNEL_SIF_0] = mmSIF_FUNNEL_0_BASE,
0157 [GAUDI_FUNNEL_SIF_1] = mmSIF_FUNNEL_1_BASE,
0158 [GAUDI_FUNNEL_SIF_2] = mmSIF_FUNNEL_2_BASE,
0159 [GAUDI_FUNNEL_SIF_3] = mmSIF_FUNNEL_3_BASE,
0160 [GAUDI_FUNNEL_SIF_4] = mmSIF_FUNNEL_4_BASE,
0161 [GAUDI_FUNNEL_SIF_5] = mmSIF_FUNNEL_5_BASE,
0162 [GAUDI_FUNNEL_SIF_6] = mmSIF_FUNNEL_6_BASE,
0163 [GAUDI_FUNNEL_SIF_7] = mmSIF_FUNNEL_7_BASE,
0164 [GAUDI_FUNNEL_NIF_0] = mmNIF_FUNNEL_0_BASE,
0165 [GAUDI_FUNNEL_NIF_1] = mmNIF_FUNNEL_1_BASE,
0166 [GAUDI_FUNNEL_NIF_2] = mmNIF_FUNNEL_2_BASE,
0167 [GAUDI_FUNNEL_NIF_3] = mmNIF_FUNNEL_3_BASE,
0168 [GAUDI_FUNNEL_NIF_4] = mmNIF_FUNNEL_4_BASE,
0169 [GAUDI_FUNNEL_NIF_5] = mmNIF_FUNNEL_5_BASE,
0170 [GAUDI_FUNNEL_NIF_6] = mmNIF_FUNNEL_6_BASE,
0171 [GAUDI_FUNNEL_NIF_7] = mmNIF_FUNNEL_7_BASE,
0172 [GAUDI_FUNNEL_DMA_IF_W_S] = mmDMA_IF_W_S_FUNNEL_BASE,
0173 [GAUDI_FUNNEL_DMA_IF_E_S] = mmDMA_IF_E_S_FUNNEL_BASE,
0174 [GAUDI_FUNNEL_DMA_IF_W_N] = mmDMA_IF_W_N_FUNNEL_BASE,
0175 [GAUDI_FUNNEL_DMA_IF_E_N] = mmDMA_IF_E_N_FUNNEL_BASE,
0176 [GAUDI_FUNNEL_CPU] = mmCPU_FUNNEL_BASE,
0177 [GAUDI_FUNNEL_NIC_TPC_W_S] = mmNIC_TPC_FUNNEL_W_S_BASE,
0178 [GAUDI_FUNNEL_NIC_TPC_E_S] = mmNIC_TPC_FUNNEL_E_S_BASE,
0179 [GAUDI_FUNNEL_NIC_TPC_W_N] = mmNIC_TPC_FUNNEL_W_N_BASE,
0180 [GAUDI_FUNNEL_NIC_TPC_E_N] = mmNIC_TPC_FUNNEL_E_N_BASE,
0181 [GAUDI_FUNNEL_PCIE] = mmPCIE_FUNNEL_BASE,
0182 [GAUDI_FUNNEL_PSOC] = mmPSOC_FUNNEL_BASE,
0183 [GAUDI_FUNNEL_NIC0] = mmFUNNEL_NIC0_DBG_BASE,
0184 [GAUDI_FUNNEL_NIC1] = mmFUNNEL_NIC1_DBG_BASE,
0185 [GAUDI_FUNNEL_NIC2] = mmFUNNEL_NIC2_DBG_BASE,
0186 [GAUDI_FUNNEL_NIC3] = mmFUNNEL_NIC3_DBG_BASE,
0187 [GAUDI_FUNNEL_NIC4] = mmFUNNEL_NIC4_DBG_BASE,
0188 [GAUDI_FUNNEL_TPC0_EML] = mmTPC0_EML_FUNNEL_BASE,
0189 [GAUDI_FUNNEL_TPC1_EML] = mmTPC1_EML_FUNNEL_BASE,
0190 [GAUDI_FUNNEL_TPC2_EML] = mmTPC2_EML_FUNNEL_BASE,
0191 [GAUDI_FUNNEL_TPC3_EML] = mmTPC3_EML_FUNNEL_BASE,
0192 [GAUDI_FUNNEL_TPC4_EML] = mmTPC4_EML_FUNNEL_BASE,
0193 [GAUDI_FUNNEL_TPC5_EML] = mmTPC5_EML_FUNNEL_BASE,
0194 [GAUDI_FUNNEL_TPC6_EML] = mmTPC6_EML_FUNNEL_BASE,
0195 [GAUDI_FUNNEL_TPC7_EML] = mmTPC7_EML_FUNNEL_BASE
0196 };
0197
0198 static u64 debug_bmon_regs[GAUDI_BMON_LAST + 1] = {
0199 [GAUDI_BMON_MME0_ACC_0] = mmMME0_ACC_BMON0_BASE,
0200 [GAUDI_BMON_MME0_SBAB_0] = mmMME0_SBAB_BMON0_BASE,
0201 [GAUDI_BMON_MME0_SBAB_1] = mmMME0_SBAB_BMON1_BASE,
0202 [GAUDI_BMON_MME0_CTRL_0] = mmMME0_CTRL_BMON0_BASE,
0203 [GAUDI_BMON_MME0_CTRL_1] = mmMME0_CTRL_BMON1_BASE,
0204 [GAUDI_BMON_MME1_ACC_0] = mmMME1_ACC_BMON0_BASE,
0205 [GAUDI_BMON_MME1_SBAB_0] = mmMME1_SBAB_BMON0_BASE,
0206 [GAUDI_BMON_MME1_SBAB_1] = mmMME1_SBAB_BMON1_BASE,
0207 [GAUDI_BMON_MME1_CTRL_0] = mmMME1_CTRL_BMON0_BASE,
0208 [GAUDI_BMON_MME1_CTRL_1] = mmMME1_CTRL_BMON1_BASE,
0209 [GAUDI_BMON_MME2_ACC_0] = mmMME2_ACC_BMON0_BASE,
0210 [GAUDI_BMON_MME2_SBAB_0] = mmMME2_SBAB_BMON0_BASE,
0211 [GAUDI_BMON_MME2_SBAB_1] = mmMME2_SBAB_BMON1_BASE,
0212 [GAUDI_BMON_MME2_CTRL_0] = mmMME2_CTRL_BMON0_BASE,
0213 [GAUDI_BMON_MME2_CTRL_1] = mmMME2_CTRL_BMON1_BASE,
0214 [GAUDI_BMON_MME3_ACC_0] = mmMME3_ACC_BMON0_BASE,
0215 [GAUDI_BMON_MME3_SBAB_0] = mmMME3_SBAB_BMON0_BASE,
0216 [GAUDI_BMON_MME3_SBAB_1] = mmMME3_SBAB_BMON1_BASE,
0217 [GAUDI_BMON_MME3_CTRL_0] = mmMME3_CTRL_BMON0_BASE,
0218 [GAUDI_BMON_MME3_CTRL_1] = mmMME3_CTRL_BMON1_BASE,
0219 [GAUDI_BMON_DMA_IF_W_S_SOB_WR] = mmDMA_IF_W_S_SOB_WR_BMON_BASE,
0220 [GAUDI_BMON_DMA_IF_W_S_0_WR] = mmDMA_IF_W_S_HBM0_WR_BMON_BASE,
0221 [GAUDI_BMON_DMA_IF_W_S_0_RD] = mmDMA_IF_W_S_HBM0_RD_BMON_BASE,
0222 [GAUDI_BMON_DMA_IF_W_S_1_WR] = mmDMA_IF_W_S_HBM1_WR_BMON_BASE,
0223 [GAUDI_BMON_DMA_IF_W_S_1_RD] = mmDMA_IF_W_S_HBM1_RD_BMON_BASE,
0224 [GAUDI_BMON_DMA_IF_E_S_SOB_WR] = mmDMA_IF_E_S_SOB_WR_BMON_BASE,
0225 [GAUDI_BMON_DMA_IF_E_S_0_WR] = mmDMA_IF_E_S_HBM0_WR_BMON_BASE,
0226 [GAUDI_BMON_DMA_IF_E_S_0_RD] = mmDMA_IF_E_S_HBM0_RD_BMON_BASE,
0227 [GAUDI_BMON_DMA_IF_E_S_1_WR] = mmDMA_IF_E_S_HBM1_WR_BMON_BASE,
0228 [GAUDI_BMON_DMA_IF_E_S_1_RD] = mmDMA_IF_E_S_HBM1_RD_BMON_BASE,
0229 [GAUDI_BMON_DMA_IF_W_N_SOB_WR] = mmDMA_IF_W_N_SOB_WR_BMON_BASE,
0230 [GAUDI_BMON_DMA_IF_W_N_HBM0_WR] = mmDMA_IF_W_N_HBM0_WR_BMON_BASE,
0231 [GAUDI_BMON_DMA_IF_W_N_HBM0_RD] = mmDMA_IF_W_N_HBM0_RD_BMON_BASE,
0232 [GAUDI_BMON_DMA_IF_W_N_HBM1_WR] = mmDMA_IF_W_N_HBM1_WR_BMON_BASE,
0233 [GAUDI_BMON_DMA_IF_W_N_HBM1_RD] = mmDMA_IF_W_N_HBM1_RD_BMON_BASE,
0234 [GAUDI_BMON_DMA_IF_E_N_SOB_WR] = mmDMA_IF_E_N_SOB_WR_BMON_BASE,
0235 [GAUDI_BMON_DMA_IF_E_N_HBM0_WR] = mmDMA_IF_E_N_HBM0_WR_BMON_BASE,
0236 [GAUDI_BMON_DMA_IF_E_N_HBM0_RD] = mmDMA_IF_E_N_HBM0_RD_BMON_BASE,
0237 [GAUDI_BMON_DMA_IF_E_N_HBM1_WR] = mmDMA_IF_E_N_HBM1_WR_BMON_BASE,
0238 [GAUDI_BMON_DMA_IF_E_N_HBM1_RD] = mmDMA_IF_E_N_HBM1_RD_BMON_BASE,
0239 [GAUDI_BMON_CPU_WR] = mmCPU_WR_BMON_BASE,
0240 [GAUDI_BMON_CPU_RD] = mmCPU_RD_BMON_BASE,
0241 [GAUDI_BMON_DMA_CH_0_0] = mmDMA_CH_0_BMON_0_BASE,
0242 [GAUDI_BMON_DMA_CH_0_1] = mmDMA_CH_0_BMON_1_BASE,
0243 [GAUDI_BMON_DMA_CH_1_0] = mmDMA_CH_1_BMON_0_BASE,
0244 [GAUDI_BMON_DMA_CH_1_1] = mmDMA_CH_1_BMON_1_BASE,
0245 [GAUDI_BMON_DMA_CH_2_0] = mmDMA_CH_2_BMON_0_BASE,
0246 [GAUDI_BMON_DMA_CH_2_1] = mmDMA_CH_2_BMON_1_BASE,
0247 [GAUDI_BMON_DMA_CH_3_0] = mmDMA_CH_3_BMON_0_BASE,
0248 [GAUDI_BMON_DMA_CH_3_1] = mmDMA_CH_3_BMON_1_BASE,
0249 [GAUDI_BMON_DMA_CH_4_0] = mmDMA_CH_4_BMON_0_BASE,
0250 [GAUDI_BMON_DMA_CH_4_1] = mmDMA_CH_4_BMON_1_BASE,
0251 [GAUDI_BMON_DMA_CH_5_0] = mmDMA_CH_5_BMON_0_BASE,
0252 [GAUDI_BMON_DMA_CH_5_1] = mmDMA_CH_5_BMON_1_BASE,
0253 [GAUDI_BMON_DMA_CH_6_0] = mmDMA_CH_6_BMON_0_BASE,
0254 [GAUDI_BMON_DMA_CH_6_1] = mmDMA_CH_6_BMON_1_BASE,
0255 [GAUDI_BMON_DMA_CH_7_0] = mmDMA_CH_7_BMON_0_BASE,
0256 [GAUDI_BMON_DMA_CH_7_1] = mmDMA_CH_7_BMON_1_BASE,
0257 [GAUDI_BMON_PCIE_MSTR_WR] = mmPCIE_BMON_MSTR_WR_BASE,
0258 [GAUDI_BMON_PCIE_MSTR_RD] = mmPCIE_BMON_MSTR_RD_BASE,
0259 [GAUDI_BMON_PCIE_SLV_WR] = mmPCIE_BMON_SLV_WR_BASE,
0260 [GAUDI_BMON_PCIE_SLV_RD] = mmPCIE_BMON_SLV_RD_BASE,
0261 [GAUDI_BMON_MMU_0] = mmMMU_BMON_0_BASE,
0262 [GAUDI_BMON_MMU_1] = mmMMU_BMON_1_BASE,
0263 [GAUDI_BMON_NIC0_0] = mmBMON0_NIC0_DBG_BASE,
0264 [GAUDI_BMON_NIC0_1] = mmBMON1_NIC0_DBG_BASE,
0265 [GAUDI_BMON_NIC0_2] = mmBMON2_NIC0_DBG_BASE,
0266 [GAUDI_BMON_NIC0_3] = mmBMON3_NIC0_DBG_BASE,
0267 [GAUDI_BMON_NIC0_4] = mmBMON4_NIC0_DBG_BASE,
0268 [GAUDI_BMON_NIC1_0] = mmBMON0_NIC1_DBG_BASE,
0269 [GAUDI_BMON_NIC1_1] = mmBMON1_NIC1_DBG_BASE,
0270 [GAUDI_BMON_NIC1_2] = mmBMON2_NIC1_DBG_BASE,
0271 [GAUDI_BMON_NIC1_3] = mmBMON3_NIC1_DBG_BASE,
0272 [GAUDI_BMON_NIC1_4] = mmBMON4_NIC1_DBG_BASE,
0273 [GAUDI_BMON_NIC2_0] = mmBMON0_NIC2_DBG_BASE,
0274 [GAUDI_BMON_NIC2_1] = mmBMON1_NIC2_DBG_BASE,
0275 [GAUDI_BMON_NIC2_2] = mmBMON2_NIC2_DBG_BASE,
0276 [GAUDI_BMON_NIC2_3] = mmBMON3_NIC2_DBG_BASE,
0277 [GAUDI_BMON_NIC2_4] = mmBMON4_NIC2_DBG_BASE,
0278 [GAUDI_BMON_NIC3_0] = mmBMON0_NIC3_DBG_BASE,
0279 [GAUDI_BMON_NIC3_1] = mmBMON1_NIC3_DBG_BASE,
0280 [GAUDI_BMON_NIC3_2] = mmBMON2_NIC3_DBG_BASE,
0281 [GAUDI_BMON_NIC3_3] = mmBMON3_NIC3_DBG_BASE,
0282 [GAUDI_BMON_NIC3_4] = mmBMON4_NIC3_DBG_BASE,
0283 [GAUDI_BMON_NIC4_0] = mmBMON0_NIC4_DBG_BASE,
0284 [GAUDI_BMON_NIC4_1] = mmBMON1_NIC4_DBG_BASE,
0285 [GAUDI_BMON_NIC4_2] = mmBMON2_NIC4_DBG_BASE,
0286 [GAUDI_BMON_NIC4_3] = mmBMON3_NIC4_DBG_BASE,
0287 [GAUDI_BMON_NIC4_4] = mmBMON4_NIC4_DBG_BASE,
0288 [GAUDI_BMON_TPC0_EML_0] = mmTPC0_EML_BUSMON_0_BASE,
0289 [GAUDI_BMON_TPC0_EML_1] = mmTPC0_EML_BUSMON_1_BASE,
0290 [GAUDI_BMON_TPC0_EML_2] = mmTPC0_EML_BUSMON_2_BASE,
0291 [GAUDI_BMON_TPC0_EML_3] = mmTPC0_EML_BUSMON_3_BASE,
0292 [GAUDI_BMON_TPC1_EML_0] = mmTPC1_EML_BUSMON_0_BASE,
0293 [GAUDI_BMON_TPC1_EML_1] = mmTPC1_EML_BUSMON_1_BASE,
0294 [GAUDI_BMON_TPC1_EML_2] = mmTPC1_EML_BUSMON_2_BASE,
0295 [GAUDI_BMON_TPC1_EML_3] = mmTPC1_EML_BUSMON_3_BASE,
0296 [GAUDI_BMON_TPC2_EML_0] = mmTPC2_EML_BUSMON_0_BASE,
0297 [GAUDI_BMON_TPC2_EML_1] = mmTPC2_EML_BUSMON_1_BASE,
0298 [GAUDI_BMON_TPC2_EML_2] = mmTPC2_EML_BUSMON_2_BASE,
0299 [GAUDI_BMON_TPC2_EML_3] = mmTPC2_EML_BUSMON_3_BASE,
0300 [GAUDI_BMON_TPC3_EML_0] = mmTPC3_EML_BUSMON_0_BASE,
0301 [GAUDI_BMON_TPC3_EML_1] = mmTPC3_EML_BUSMON_1_BASE,
0302 [GAUDI_BMON_TPC3_EML_2] = mmTPC3_EML_BUSMON_2_BASE,
0303 [GAUDI_BMON_TPC3_EML_3] = mmTPC3_EML_BUSMON_3_BASE,
0304 [GAUDI_BMON_TPC4_EML_0] = mmTPC4_EML_BUSMON_0_BASE,
0305 [GAUDI_BMON_TPC4_EML_1] = mmTPC4_EML_BUSMON_1_BASE,
0306 [GAUDI_BMON_TPC4_EML_2] = mmTPC4_EML_BUSMON_2_BASE,
0307 [GAUDI_BMON_TPC4_EML_3] = mmTPC4_EML_BUSMON_3_BASE,
0308 [GAUDI_BMON_TPC5_EML_0] = mmTPC5_EML_BUSMON_0_BASE,
0309 [GAUDI_BMON_TPC5_EML_1] = mmTPC5_EML_BUSMON_1_BASE,
0310 [GAUDI_BMON_TPC5_EML_2] = mmTPC5_EML_BUSMON_2_BASE,
0311 [GAUDI_BMON_TPC5_EML_3] = mmTPC5_EML_BUSMON_3_BASE,
0312 [GAUDI_BMON_TPC6_EML_0] = mmTPC6_EML_BUSMON_0_BASE,
0313 [GAUDI_BMON_TPC6_EML_1] = mmTPC6_EML_BUSMON_1_BASE,
0314 [GAUDI_BMON_TPC6_EML_2] = mmTPC6_EML_BUSMON_2_BASE,
0315 [GAUDI_BMON_TPC6_EML_3] = mmTPC6_EML_BUSMON_3_BASE,
0316 [GAUDI_BMON_TPC7_EML_0] = mmTPC7_EML_BUSMON_0_BASE,
0317 [GAUDI_BMON_TPC7_EML_1] = mmTPC7_EML_BUSMON_1_BASE,
0318 [GAUDI_BMON_TPC7_EML_2] = mmTPC7_EML_BUSMON_2_BASE,
0319 [GAUDI_BMON_TPC7_EML_3] = mmTPC7_EML_BUSMON_3_BASE
0320 };
0321
0322 static u64 debug_spmu_regs[GAUDI_SPMU_LAST + 1] = {
0323 [GAUDI_SPMU_MME0_ACC] = mmMME0_ACC_SPMU_BASE,
0324 [GAUDI_SPMU_MME0_SBAB] = mmMME0_SBAB_SPMU_BASE,
0325 [GAUDI_SPMU_MME0_CTRL] = mmMME0_CTRL_SPMU_BASE,
0326 [GAUDI_SPMU_MME1_ACC] = mmMME1_ACC_SPMU_BASE,
0327 [GAUDI_SPMU_MME1_SBAB] = mmMME1_SBAB_SPMU_BASE,
0328 [GAUDI_SPMU_MME1_CTRL] = mmMME1_CTRL_SPMU_BASE,
0329 [GAUDI_SPMU_MME2_MME2_ACC] = mmMME2_ACC_SPMU_BASE,
0330 [GAUDI_SPMU_MME2_SBAB] = mmMME2_SBAB_SPMU_BASE,
0331 [GAUDI_SPMU_MME2_CTRL] = mmMME2_CTRL_SPMU_BASE,
0332 [GAUDI_SPMU_MME3_ACC] = mmMME3_ACC_SPMU_BASE,
0333 [GAUDI_SPMU_MME3_SBAB] = mmMME3_SBAB_SPMU_BASE,
0334 [GAUDI_SPMU_MME3_CTRL] = mmMME3_CTRL_SPMU_BASE,
0335 [GAUDI_SPMU_DMA_CH_0_CS] = mmDMA_CH_0_CS_SPMU_BASE,
0336 [GAUDI_SPMU_DMA_CH_1_CS] = mmDMA_CH_1_CS_SPMU_BASE,
0337 [GAUDI_SPMU_DMA_CH_2_CS] = mmDMA_CH_2_CS_SPMU_BASE,
0338 [GAUDI_SPMU_DMA_CH_3_CS] = mmDMA_CH_3_CS_SPMU_BASE,
0339 [GAUDI_SPMU_DMA_CH_4_CS] = mmDMA_CH_4_CS_SPMU_BASE,
0340 [GAUDI_SPMU_DMA_CH_5_CS] = mmDMA_CH_5_CS_SPMU_BASE,
0341 [GAUDI_SPMU_DMA_CH_6_CS] = mmDMA_CH_6_CS_SPMU_BASE,
0342 [GAUDI_SPMU_DMA_CH_7_CS] = mmDMA_CH_7_CS_SPMU_BASE,
0343 [GAUDI_SPMU_PCIE] = mmPCIE_SPMU_BASE,
0344 [GAUDI_SPMU_MMU_CS] = mmMMU_CS_SPMU_BASE,
0345 [GAUDI_SPMU_NIC0_0] = mmSPMU_0_NIC0_DBG_BASE,
0346 [GAUDI_SPMU_NIC0_1] = mmSPMU_1_NIC0_DBG_BASE,
0347 [GAUDI_SPMU_NIC1_0] = mmSPMU_0_NIC1_DBG_BASE,
0348 [GAUDI_SPMU_NIC1_1] = mmSPMU_1_NIC1_DBG_BASE,
0349 [GAUDI_SPMU_NIC2_0] = mmSPMU_0_NIC2_DBG_BASE,
0350 [GAUDI_SPMU_NIC2_1] = mmSPMU_1_NIC2_DBG_BASE,
0351 [GAUDI_SPMU_NIC3_0] = mmSPMU_0_NIC3_DBG_BASE,
0352 [GAUDI_SPMU_NIC3_1] = mmSPMU_1_NIC3_DBG_BASE,
0353 [GAUDI_SPMU_NIC4_0] = mmSPMU_0_NIC4_DBG_BASE,
0354 [GAUDI_SPMU_NIC4_1] = mmSPMU_1_NIC4_DBG_BASE,
0355 [GAUDI_SPMU_TPC0_EML] = mmTPC0_EML_SPMU_BASE,
0356 [GAUDI_SPMU_TPC1_EML] = mmTPC1_EML_SPMU_BASE,
0357 [GAUDI_SPMU_TPC2_EML] = mmTPC2_EML_SPMU_BASE,
0358 [GAUDI_SPMU_TPC3_EML] = mmTPC3_EML_SPMU_BASE,
0359 [GAUDI_SPMU_TPC4_EML] = mmTPC4_EML_SPMU_BASE,
0360 [GAUDI_SPMU_TPC5_EML] = mmTPC5_EML_SPMU_BASE,
0361 [GAUDI_SPMU_TPC6_EML] = mmTPC6_EML_SPMU_BASE,
0362 [GAUDI_SPMU_TPC7_EML] = mmTPC7_EML_SPMU_BASE
0363 };
0364
0365 static int gaudi_coresight_timeout(struct hl_device *hdev, u64 addr,
0366 int position, bool up)
0367 {
0368 int rc;
0369 u32 val;
0370
0371 rc = hl_poll_timeout(
0372 hdev,
0373 addr,
0374 val,
0375 up ? val & BIT(position) : !(val & BIT(position)),
0376 1000,
0377 CORESIGHT_TIMEOUT_USEC);
0378
0379 if (rc) {
0380 dev_err(hdev->dev,
0381 "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n",
0382 addr, position, up);
0383 return -EFAULT;
0384 }
0385
0386 return 0;
0387 }
0388
0389 static int gaudi_config_stm(struct hl_device *hdev,
0390 struct hl_debug_params *params)
0391 {
0392 struct hl_debug_params_stm *input;
0393 u64 base_reg;
0394 u32 frequency;
0395 int rc;
0396
0397 if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) {
0398 dev_err(hdev->dev, "Invalid register index in STM\n");
0399 return -EINVAL;
0400 }
0401
0402 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE;
0403
0404 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
0405
0406 if (params->enable) {
0407 input = params->input;
0408
0409 if (!input)
0410 return -EINVAL;
0411
0412 WREG32(base_reg + 0xE80, 0x80004);
0413 WREG32(base_reg + 0xD64, 7);
0414 WREG32(base_reg + 0xD60, 0);
0415 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask));
0416 WREG32(base_reg + 0xD60, 1);
0417 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask));
0418 WREG32(base_reg + 0xE70, 0x10);
0419 WREG32(base_reg + 0xE60, 0);
0420 WREG32(base_reg + 0xE00, lower_32_bits(input->sp_mask));
0421 WREG32(base_reg + 0xEF4, input->id);
0422 WREG32(base_reg + 0xDF4, 0x80);
0423 frequency = hdev->asic_prop.psoc_timestamp_frequency;
0424 if (frequency == 0)
0425 frequency = input->frequency;
0426 WREG32(base_reg + 0xE8C, frequency);
0427 WREG32(base_reg + 0xE90, 0x1F00);
0428
0429
0430 if ((CFG_BASE + base_reg) >= mmDMA_CH_0_CS_STM_BASE &&
0431 (CFG_BASE + base_reg) <= mmDMA_CH_7_CS_STM_BASE) {
0432
0433 WREG32(base_reg + 0xE68, 0xffff8005);
0434 WREG32(base_reg + 0xE6C, 0x0);
0435 }
0436
0437 WREG32(base_reg + 0xE80, 0x23 | (input->id << 16));
0438 } else {
0439 WREG32(base_reg + 0xE80, 4);
0440 WREG32(base_reg + 0xD64, 0);
0441 WREG32(base_reg + 0xD60, 1);
0442 WREG32(base_reg + 0xD00, 0);
0443 WREG32(base_reg + 0xD20, 0);
0444 WREG32(base_reg + 0xD60, 0);
0445 WREG32(base_reg + 0xE20, 0);
0446 WREG32(base_reg + 0xE00, 0);
0447 WREG32(base_reg + 0xDF4, 0x80);
0448 WREG32(base_reg + 0xE70, 0);
0449 WREG32(base_reg + 0xE60, 0);
0450 WREG32(base_reg + 0xE64, 0);
0451 WREG32(base_reg + 0xE8C, 0);
0452
0453 rc = gaudi_coresight_timeout(hdev, base_reg + 0xE80, 23, false);
0454 if (rc) {
0455 dev_err(hdev->dev,
0456 "Failed to disable STM on timeout, error %d\n",
0457 rc);
0458 return rc;
0459 }
0460
0461 WREG32(base_reg + 0xE80, 4);
0462 }
0463
0464 return 0;
0465 }
0466
0467 static int gaudi_config_etf(struct hl_device *hdev,
0468 struct hl_debug_params *params)
0469 {
0470 struct hl_debug_params_etf *input;
0471 u64 base_reg;
0472 u32 val;
0473 int rc;
0474
0475 if (params->reg_idx >= ARRAY_SIZE(debug_etf_regs)) {
0476 dev_err(hdev->dev, "Invalid register index in ETF\n");
0477 return -EINVAL;
0478 }
0479
0480 base_reg = debug_etf_regs[params->reg_idx] - CFG_BASE;
0481
0482 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
0483
0484 val = RREG32(base_reg + 0x304);
0485 val |= 0x1000;
0486 WREG32(base_reg + 0x304, val);
0487 val |= 0x40;
0488 WREG32(base_reg + 0x304, val);
0489
0490 rc = gaudi_coresight_timeout(hdev, base_reg + 0x304, 6, false);
0491 if (rc) {
0492 dev_err(hdev->dev,
0493 "Failed to %s ETF on timeout, error %d\n",
0494 params->enable ? "enable" : "disable", rc);
0495 return rc;
0496 }
0497
0498 rc = gaudi_coresight_timeout(hdev, base_reg + 0xC, 2, true);
0499 if (rc) {
0500 dev_err(hdev->dev,
0501 "Failed to %s ETF on timeout, error %d\n",
0502 params->enable ? "enable" : "disable", rc);
0503 return rc;
0504 }
0505
0506 WREG32(base_reg + 0x20, 0);
0507
0508 if (params->enable) {
0509 input = params->input;
0510
0511 if (!input)
0512 return -EINVAL;
0513
0514 WREG32(base_reg + 0x34, 0x3FFC);
0515 WREG32(base_reg + 0x28, input->sink_mode);
0516 WREG32(base_reg + 0x304, 0x4001);
0517 WREG32(base_reg + 0x308, 0xA);
0518 WREG32(base_reg + 0x20, 1);
0519 } else {
0520 WREG32(base_reg + 0x34, 0);
0521 WREG32(base_reg + 0x28, 0);
0522 WREG32(base_reg + 0x304, 0);
0523 }
0524
0525 return 0;
0526 }
0527
0528 static bool gaudi_etr_validate_address(struct hl_device *hdev, u64 addr,
0529 u64 size, bool *is_host)
0530 {
0531 struct asic_fixed_properties *prop = &hdev->asic_prop;
0532 struct gaudi_device *gaudi = hdev->asic_specific;
0533
0534
0535 if (addr >> 50) {
0536 dev_err(hdev->dev,
0537 "ETR buffer address shouldn't exceed 50 bits\n");
0538 return false;
0539 }
0540
0541 if (addr > (addr + size)) {
0542 dev_err(hdev->dev,
0543 "ETR buffer size %llu overflow\n", size);
0544 return false;
0545 }
0546
0547
0548 if ((gaudi->hw_cap_initialized & HW_CAP_MMU) &&
0549 hl_mem_area_inside_range(addr, size,
0550 prop->pmmu.start_addr,
0551 prop->pmmu.end_addr)) {
0552 *is_host = true;
0553 return true;
0554 }
0555
0556 if (hl_mem_area_inside_range(addr, size,
0557 prop->dram_user_base_address,
0558 prop->dram_end_address))
0559 return true;
0560
0561 if (hl_mem_area_inside_range(addr, size,
0562 prop->sram_user_base_address,
0563 prop->sram_end_address))
0564 return true;
0565
0566 if (!(gaudi->hw_cap_initialized & HW_CAP_MMU))
0567 dev_err(hdev->dev, "ETR buffer should be in SRAM/DRAM\n");
0568
0569 return false;
0570 }
0571
0572 static int gaudi_config_etr(struct hl_device *hdev,
0573 struct hl_debug_params *params)
0574 {
0575 struct hl_debug_params_etr *input;
0576 u64 msb;
0577 u32 val;
0578 int rc;
0579
0580 WREG32(mmPSOC_ETR_LAR, CORESIGHT_UNLOCK);
0581
0582 val = RREG32(mmPSOC_ETR_FFCR);
0583 val |= 0x1000;
0584 WREG32(mmPSOC_ETR_FFCR, val);
0585 val |= 0x40;
0586 WREG32(mmPSOC_ETR_FFCR, val);
0587
0588 rc = gaudi_coresight_timeout(hdev, mmPSOC_ETR_FFCR, 6, false);
0589 if (rc) {
0590 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",
0591 params->enable ? "enable" : "disable", rc);
0592 return rc;
0593 }
0594
0595 rc = gaudi_coresight_timeout(hdev, mmPSOC_ETR_STS, 2, true);
0596 if (rc) {
0597 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",
0598 params->enable ? "enable" : "disable", rc);
0599 return rc;
0600 }
0601
0602 WREG32(mmPSOC_ETR_CTL, 0);
0603
0604 if (params->enable) {
0605 bool is_host = false;
0606
0607 input = params->input;
0608
0609 if (!input)
0610 return -EINVAL;
0611
0612 if (input->buffer_size == 0) {
0613 dev_err(hdev->dev,
0614 "ETR buffer size should be bigger than 0\n");
0615 return -EINVAL;
0616 }
0617
0618 if (!gaudi_etr_validate_address(hdev,
0619 input->buffer_address, input->buffer_size,
0620 &is_host)) {
0621 dev_err(hdev->dev, "ETR buffer address is invalid\n");
0622 return -EINVAL;
0623 }
0624
0625 msb = upper_32_bits(input->buffer_address) >> 8;
0626 msb &= PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK;
0627 WREG32(mmPSOC_GLOBAL_CONF_TRACE_ADDR, msb);
0628
0629 WREG32(mmPSOC_ETR_BUFWM, 0x3FFC);
0630 WREG32(mmPSOC_ETR_RSZ, input->buffer_size);
0631 WREG32(mmPSOC_ETR_MODE, input->sink_mode);
0632 if (!hdev->asic_prop.fw_security_enabled) {
0633
0634 val = FIELD_PREP(
0635 PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK, 0);
0636
0637 val |= FIELD_PREP(
0638 PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK, 1);
0639
0640
0641
0642
0643 val |= FIELD_PREP(PSOC_ETR_AXICTL_WRBURSTLEN_MASK,
0644 is_host ? 0 : 7);
0645 WREG32(mmPSOC_ETR_AXICTL, val);
0646 }
0647 WREG32(mmPSOC_ETR_DBALO,
0648 lower_32_bits(input->buffer_address));
0649 WREG32(mmPSOC_ETR_DBAHI,
0650 upper_32_bits(input->buffer_address));
0651 WREG32(mmPSOC_ETR_FFCR, 3);
0652 WREG32(mmPSOC_ETR_PSCR, 0xA);
0653 WREG32(mmPSOC_ETR_CTL, 1);
0654 } else {
0655 WREG32(mmPSOC_ETR_BUFWM, 0);
0656 WREG32(mmPSOC_ETR_RSZ, 0x400);
0657 WREG32(mmPSOC_ETR_DBALO, 0);
0658 WREG32(mmPSOC_ETR_DBAHI, 0);
0659 WREG32(mmPSOC_ETR_PSCR, 0);
0660 WREG32(mmPSOC_ETR_MODE, 0);
0661 WREG32(mmPSOC_ETR_FFCR, 0);
0662
0663 if (params->output_size >= sizeof(u64)) {
0664 u32 rwp, rwphi;
0665
0666
0667
0668
0669
0670
0671
0672
0673 rwp = RREG32(mmPSOC_ETR_RWP);
0674 rwphi = RREG32(mmPSOC_ETR_RWPHI) & 0xff;
0675 msb = RREG32(mmPSOC_GLOBAL_CONF_TRACE_ADDR) &
0676 PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK;
0677 *(u64 *) params->output = ((u64) msb << 40) |
0678 ((u64) rwphi << 32) | rwp;
0679 }
0680 }
0681
0682 return 0;
0683 }
0684
0685 static int gaudi_config_funnel(struct hl_device *hdev,
0686 struct hl_debug_params *params)
0687 {
0688 u64 base_reg;
0689
0690 if (params->reg_idx >= ARRAY_SIZE(debug_funnel_regs)) {
0691 dev_err(hdev->dev, "Invalid register index in FUNNEL\n");
0692 return -EINVAL;
0693 }
0694
0695 base_reg = debug_funnel_regs[params->reg_idx] - CFG_BASE;
0696
0697 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
0698
0699 WREG32(base_reg, params->enable ? 0x33F : 0);
0700
0701 return 0;
0702 }
0703
0704 static int gaudi_config_bmon(struct hl_device *hdev,
0705 struct hl_debug_params *params)
0706 {
0707 struct hl_debug_params_bmon *input;
0708 u64 base_reg;
0709
0710 if (params->reg_idx >= ARRAY_SIZE(debug_bmon_regs)) {
0711 dev_err(hdev->dev, "Invalid register index in BMON\n");
0712 return -EINVAL;
0713 }
0714
0715 base_reg = debug_bmon_regs[params->reg_idx] - CFG_BASE;
0716
0717 WREG32(base_reg + 0x104, 1);
0718
0719 if (params->enable) {
0720 input = params->input;
0721
0722 if (!input)
0723 return -EINVAL;
0724
0725 WREG32(base_reg + 0x200, lower_32_bits(input->start_addr0));
0726 WREG32(base_reg + 0x204, upper_32_bits(input->start_addr0));
0727 WREG32(base_reg + 0x208, lower_32_bits(input->addr_mask0));
0728 WREG32(base_reg + 0x20C, upper_32_bits(input->addr_mask0));
0729 WREG32(base_reg + 0x240, lower_32_bits(input->start_addr1));
0730 WREG32(base_reg + 0x244, upper_32_bits(input->start_addr1));
0731 WREG32(base_reg + 0x248, lower_32_bits(input->addr_mask1));
0732 WREG32(base_reg + 0x24C, upper_32_bits(input->addr_mask1));
0733 WREG32(base_reg + 0x224, 0);
0734 WREG32(base_reg + 0x234, 0);
0735 WREG32(base_reg + 0x30C, input->bw_win);
0736 WREG32(base_reg + 0x308, input->win_capture);
0737 WREG32(base_reg + 0x700, 0xA000B00 | (input->id << 12));
0738 WREG32(base_reg + 0x708, 0xA000A00 | (input->id << 12));
0739 WREG32(base_reg + 0x70C, 0xA000C00 | (input->id << 12));
0740 WREG32(base_reg + 0x100, 0x11);
0741 WREG32(base_reg + 0x304, 0x1);
0742 } else {
0743 WREG32(base_reg + 0x200, 0);
0744 WREG32(base_reg + 0x204, 0);
0745 WREG32(base_reg + 0x208, 0xFFFFFFFF);
0746 WREG32(base_reg + 0x20C, 0xFFFFFFFF);
0747 WREG32(base_reg + 0x240, 0);
0748 WREG32(base_reg + 0x244, 0);
0749 WREG32(base_reg + 0x248, 0xFFFFFFFF);
0750 WREG32(base_reg + 0x24C, 0xFFFFFFFF);
0751 WREG32(base_reg + 0x224, 0xFFFFFFFF);
0752 WREG32(base_reg + 0x234, 0x1070F);
0753 WREG32(base_reg + 0x30C, 0);
0754 WREG32(base_reg + 0x308, 0xFFFF);
0755 WREG32(base_reg + 0x700, 0xA000B00);
0756 WREG32(base_reg + 0x708, 0xA000A00);
0757 WREG32(base_reg + 0x70C, 0xA000C00);
0758 WREG32(base_reg + 0x100, 1);
0759 WREG32(base_reg + 0x304, 0);
0760 WREG32(base_reg + 0x104, 0);
0761 }
0762
0763 return 0;
0764 }
0765
0766 static int gaudi_config_spmu(struct hl_device *hdev,
0767 struct hl_debug_params *params)
0768 {
0769 u64 base_reg;
0770 struct hl_debug_params_spmu *input = params->input;
0771 u64 *output;
0772 u32 output_arr_len;
0773 u32 events_num;
0774 u32 overflow_idx;
0775 u32 cycle_cnt_idx;
0776 int i;
0777
0778 if (params->reg_idx >= ARRAY_SIZE(debug_spmu_regs)) {
0779 dev_err(hdev->dev, "Invalid register index in SPMU\n");
0780 return -EINVAL;
0781 }
0782
0783 base_reg = debug_spmu_regs[params->reg_idx] - CFG_BASE;
0784
0785 if (params->enable) {
0786 input = params->input;
0787
0788 if (!input)
0789 return -EINVAL;
0790
0791 if (input->event_types_num < 3) {
0792 dev_err(hdev->dev,
0793 "not enough event types values for SPMU enable\n");
0794 return -EINVAL;
0795 }
0796
0797 if (input->event_types_num > SPMU_MAX_COUNTERS) {
0798 dev_err(hdev->dev,
0799 "too many event types values for SPMU enable\n");
0800 return -EINVAL;
0801 }
0802
0803 WREG32(base_reg + 0xE04, 0x41013046);
0804 WREG32(base_reg + 0xE04, 0x41013040);
0805
0806 for (i = 0 ; i < input->event_types_num ; i++)
0807 WREG32(base_reg + SPMU_EVENT_TYPES_OFFSET + i * 4,
0808 input->event_types[i]);
0809
0810 WREG32(base_reg + 0xE04, 0x41013041);
0811 WREG32(base_reg + 0xC00, 0x8000003F);
0812 } else {
0813 output = params->output;
0814 output_arr_len = params->output_size / 8;
0815 events_num = output_arr_len - 2;
0816 overflow_idx = output_arr_len - 2;
0817 cycle_cnt_idx = output_arr_len - 1;
0818
0819 if (!output)
0820 return -EINVAL;
0821
0822 if (output_arr_len < 3) {
0823 dev_err(hdev->dev,
0824 "not enough values for SPMU disable\n");
0825 return -EINVAL;
0826 }
0827
0828 if (events_num > SPMU_MAX_COUNTERS) {
0829 dev_err(hdev->dev,
0830 "too many events values for SPMU disable\n");
0831 return -EINVAL;
0832 }
0833
0834 WREG32(base_reg + 0xE04, 0x41013040);
0835
0836 for (i = 0 ; i < events_num ; i++)
0837 output[i] = RREG32(base_reg + i * 8);
0838
0839 output[overflow_idx] = RREG32(base_reg + 0xCC0);
0840
0841 output[cycle_cnt_idx] = RREG32(base_reg + 0xFC);
0842 output[cycle_cnt_idx] <<= 32;
0843 output[cycle_cnt_idx] |= RREG32(base_reg + 0xF8);
0844
0845 WREG32(base_reg + 0xCC0, 0);
0846 }
0847
0848 return 0;
0849 }
0850
0851 int gaudi_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data)
0852 {
0853 struct hl_debug_params *params = data;
0854 int rc = 0;
0855
0856 switch (params->op) {
0857 case HL_DEBUG_OP_STM:
0858 rc = gaudi_config_stm(hdev, params);
0859 break;
0860 case HL_DEBUG_OP_ETF:
0861 rc = gaudi_config_etf(hdev, params);
0862 break;
0863 case HL_DEBUG_OP_ETR:
0864 rc = gaudi_config_etr(hdev, params);
0865 break;
0866 case HL_DEBUG_OP_FUNNEL:
0867 rc = gaudi_config_funnel(hdev, params);
0868 break;
0869 case HL_DEBUG_OP_BMON:
0870 rc = gaudi_config_bmon(hdev, params);
0871 break;
0872 case HL_DEBUG_OP_SPMU:
0873 rc = gaudi_config_spmu(hdev, params);
0874 break;
0875 case HL_DEBUG_OP_TIMESTAMP:
0876
0877 break;
0878
0879 default:
0880 dev_err(hdev->dev, "Unknown coresight id %d\n", params->op);
0881 return -EINVAL;
0882 }
0883
0884
0885 RREG32(mmHW_STATE);
0886
0887 return rc;
0888 }
0889
0890 void gaudi_halt_coresight(struct hl_device *hdev, struct hl_ctx *ctx)
0891 {
0892 struct hl_debug_params params = {};
0893 int i, rc;
0894
0895 for (i = GAUDI_ETF_FIRST ; i <= GAUDI_ETF_LAST ; i++) {
0896 params.reg_idx = i;
0897 rc = gaudi_config_etf(hdev, ¶ms);
0898 if (rc)
0899 dev_err(hdev->dev, "halt ETF failed, %d/%d\n", rc, i);
0900 }
0901
0902 rc = gaudi_config_etr(hdev, ¶ms);
0903 if (rc)
0904 dev_err(hdev->dev, "halt ETR failed, %d\n", rc);
0905 }
