misc/genwqe/card_ddcb.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 #ifndef __CARD_DDCB_H__
0003 #define __CARD_DDCB_H__
0004
0005 /**
0006  * IBM Accelerator Family 'GenWQE'
0007  *
0008  * (C) Copyright IBM Corp. 2013
0009  *
0010  * Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
0011  * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
0012  * Author: Michael Jung <mijung@gmx.net>
0013  * Author: Michael Ruettger <michael@ibmra.de>
0014  */
0015
0016 #include <linux/types.h>
0017 #include <asm/byteorder.h>
0018
0019 #include "genwqe_driver.h"
0020 #include "card_base.h"
0021
0022 /**
0023  * struct ddcb - Device Driver Control Block DDCB
0024  * @hsi:        Hardware software interlock
0025  * @shi:        Software hardware interlock. Hsi and shi are used to interlock
0026  *              software and hardware activities. We are using a compare and
0027  *              swap operation to ensure that there are no races when
0028  *              activating new DDCBs on the queue, or when we need to
0029  *              purge a DDCB from a running queue.
0030  * @acfunc:     Accelerator function addresses a unit within the chip
0031  * @cmd:        Command to work on
0032  * @cmdopts_16: Options for the command
0033  * @asiv:       Input data
0034  * @asv:        Output data
0035  *
0036  * The DDCB data format is big endian. Multiple consequtive DDBCs form
0037  * a DDCB queue.
0038  */
0039 #define ASIV_LENGTH     104 /* Old specification without ATS field */
0040 #define ASIV_LENGTH_ATS     96  /* New specification with ATS field */
0041 #define ASV_LENGTH      64
0042
0043 struct ddcb {
0044     union {
0045         __be32 icrc_hsi_shi_32; /* iCRC, Hardware/SW interlock */
0046         struct {
0047             __be16  icrc_16;
0048             u8  hsi;
0049             u8  shi;
0050         };
0051     };
0052     u8  pre;        /* Preamble */
0053     u8  xdir;       /* Execution Directives */
0054     __be16 seqnum_16;   /* Sequence Number */
0055
0056     u8  acfunc;     /* Accelerator Function.. */
0057     u8  cmd;        /* Command. */
0058     __be16 cmdopts_16;  /* Command Options */
0059     u8  sur;        /* Status Update Rate */
0060     u8  psp;        /* Protection Section Pointer */
0061     __be16 rsvd_0e_16;  /* Reserved invariant */
0062
0063     __be64 fwiv_64;     /* Firmware Invariant. */
0064
0065     union {
0066         struct {
0067             __be64 ats_64;  /* Address Translation Spec */
0068             u8     asiv[ASIV_LENGTH_ATS]; /* New ASIV */
0069         } n;
0070         u8  __asiv[ASIV_LENGTH];    /* obsolete */
0071     };
0072     u8     asv[ASV_LENGTH]; /* Appl Spec Variant */
0073
0074     __be16 rsvd_c0_16;  /* Reserved Variant */
0075     __be16 vcrc_16;     /* Variant CRC */
0076     __be32 rsvd_32;     /* Reserved unprotected */
0077
0078     __be64 deque_ts_64; /* Deque Time Stamp. */
0079
0080     __be16 retc_16;     /* Return Code */
0081     __be16 attn_16;     /* Attention/Extended Error Codes */
0082     __be32 progress_32; /* Progress indicator. */
0083
0084     __be64 cmplt_ts_64; /* Completion Time Stamp. */
0085
0086     /* The following layout matches the new service layer format */
0087     __be32 ibdc_32;     /* Inbound Data Count  (* 256) */
0088     __be32 obdc_32;     /* Outbound Data Count (* 256) */
0089
0090     __be64 rsvd_SLH_64; /* Reserved for hardware */
0091     union {         /* private data for driver */
0092         u8  priv[8];
0093         __be64  priv_64;
0094     };
0095     __be64 disp_ts_64;  /* Dispatch TimeStamp */
0096 } __attribute__((__packed__));
0097
0098 /* CRC polynomials for DDCB */
0099 #define CRC16_POLYNOMIAL    0x1021
0100
0101 /*
0102  * SHI: Software to Hardware Interlock
0103  *   This 1 byte field is written by software to interlock the
0104  *   movement of one queue entry to another with the hardware in the
0105  *   chip.
0106  */
0107 #define DDCB_SHI_INTR       0x04 /* Bit 2 */
0108 #define DDCB_SHI_PURGE      0x02 /* Bit 1 */
0109 #define DDCB_SHI_NEXT       0x01 /* Bit 0 */
0110
0111 /*
0112  * HSI: Hardware to Software interlock
0113  * This 1 byte field is written by hardware to interlock the movement
0114  * of one queue entry to another with the software in the chip.
0115  */
0116 #define DDCB_HSI_COMPLETED  0x40 /* Bit 6 */
0117 #define DDCB_HSI_FETCHED    0x04 /* Bit 2 */
0118
0119 /*
0120  * Accessing HSI/SHI is done 32-bit wide
0121  *   Normally 16-bit access would work too, but on some platforms the
0122  *   16 compare and swap operation is not supported. Therefore
0123  *   switching to 32-bit such that those platforms will work too.
0124  *
0125  *                                         iCRC HSI/SHI
0126  */
0127 #define DDCB_INTR_BE32      cpu_to_be32(0x00000004)
0128 #define DDCB_PURGE_BE32     cpu_to_be32(0x00000002)
0129 #define DDCB_NEXT_BE32      cpu_to_be32(0x00000001)
0130 #define DDCB_COMPLETED_BE32 cpu_to_be32(0x00004000)
0131 #define DDCB_FETCHED_BE32   cpu_to_be32(0x00000400)
0132
0133 /* Definitions of DDCB presets */
0134 #define DDCB_PRESET_PRE     0x80
0135 #define ICRC_LENGTH(n)      ((n) + 8 + 8 + 8)  /* used ASIV + hdr fields */
0136 #define VCRC_LENGTH(n)      ((n))          /* used ASV */
0137
0138 /*
0139  * Genwqe Scatter Gather list
0140  *   Each element has up to 8 entries.
0141  *   The chaining element is element 0 cause of prefetching needs.
0142  */
0143
0144 /*
0145  * 0b0110 Chained descriptor. The descriptor is describing the next
0146  * descriptor list.
0147  */
0148 #define SG_CHAINED      (0x6)
0149
0150 /*
0151  * 0b0010 First entry of a descriptor list. Start from a Buffer-Empty
0152  * condition.
0153  */
0154 #define SG_DATA         (0x2)
0155
0156 /*
0157  * 0b0000 Early terminator. This is the last entry on the list
0158  * irregardless of the length indicated.
0159  */
0160 #define SG_END_LIST     (0x0)
0161
0162 /**
0163  * struct sglist - Scatter gather list
0164  * @target_addr:       Either a dma addr of memory to work on or a
0165  *                     dma addr or a subsequent sglist block.
0166  * @len:               Length of the data block.
0167  * @flags:             See above.
0168  *
0169  * Depending on the command the GenWQE card can use a scatter gather
0170  * list to describe the memory it works on. Always 8 sg_entry's form
0171  * a block.
0172  */
0173 struct sg_entry {
0174     __be64 target_addr;
0175     __be32 len;
0176     __be32 flags;
0177 };
0178
0179 #endif /* __CARD_DDCB_H__ */