misc/genwqe/card_base.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 #ifndef __CARD_BASE_H__
0003 #define __CARD_BASE_H__
0004
0005 /**
0006  * IBM Accelerator Family 'GenWQE'
0007  *
0008  * (C) Copyright IBM Corp. 2013
0009  *
0010  * Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
0011  * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
0012  * Author: Michael Jung <mijung@gmx.net>
0013  * Author: Michael Ruettger <michael@ibmra.de>
0014  */
0015
0016 /*
0017  * Interfaces within the GenWQE module. Defines genwqe_card and
0018  * ddcb_queue as well as ddcb_requ.
0019  */
0020
0021 #include <linux/kernel.h>
0022 #include <linux/types.h>
0023 #include <linux/cdev.h>
0024 #include <linux/stringify.h>
0025 #include <linux/pci.h>
0026 #include <linux/semaphore.h>
0027 #include <linux/uaccess.h>
0028 #include <linux/io.h>
0029 #include <linux/debugfs.h>
0030 #include <linux/slab.h>
0031
0032 #include <linux/genwqe/genwqe_card.h>
0033 #include "genwqe_driver.h"
0034
0035 #define GENWQE_MSI_IRQS         4  /* Just one supported, no MSIx */
0036
0037 #define GENWQE_MAX_VFS          15 /* maximum 15 VFs are possible */
0038 #define GENWQE_MAX_FUNCS        16 /* 1 PF and 15 VFs */
0039 #define GENWQE_CARD_NO_MAX      (16 * GENWQE_MAX_FUNCS)
0040
0041 /* Compile parameters, some of them appear in debugfs for later adjustment */
0042 #define GENWQE_DDCB_MAX         32 /* DDCBs on the work-queue */
0043 #define GENWQE_POLLING_ENABLED      0  /* in case of irqs not working */
0044 #define GENWQE_DDCB_SOFTWARE_TIMEOUT    10 /* timeout per DDCB in seconds */
0045 #define GENWQE_KILL_TIMEOUT     8  /* time until process gets killed */
0046 #define GENWQE_VF_JOBTIMEOUT_MSEC   250  /* 250 msec */
0047 #define GENWQE_PF_JOBTIMEOUT_MSEC   8000 /* 8 sec should be ok */
0048 #define GENWQE_HEALTH_CHECK_INTERVAL    4 /* <= 0: disabled */
0049
0050 /* Sysfs attribute groups used when we create the genwqe device */
0051 extern const struct attribute_group *genwqe_attribute_groups[];
0052
0053 /*
0054  * Config space for Genwqe5 A7:
0055  * 00:[14 10 4b 04]40 00 10 00[00 00 00 12]00 00 00 00
0056  * 10: 0c 00 00 f0 07 3c 00 00 00 00 00 00 00 00 00 00
0057  * 20: 00 00 00 00 00 00 00 00 00 00 00 00[14 10 4b 04]
0058  * 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 00 00 00
0059  */
0060 #define PCI_DEVICE_GENWQE       0x044b /* Genwqe DeviceID */
0061
0062 #define PCI_SUBSYSTEM_ID_GENWQE5    0x035f /* Genwqe A5 Subsystem-ID */
0063 #define PCI_SUBSYSTEM_ID_GENWQE5_NEW    0x044b /* Genwqe A5 Subsystem-ID */
0064 #define PCI_CLASSCODE_GENWQE5       0x1200 /* UNKNOWN */
0065
0066 #define PCI_SUBVENDOR_ID_IBM_SRIOV  0x0000
0067 #define PCI_SUBSYSTEM_ID_GENWQE5_SRIOV  0x0000 /* Genwqe A5 Subsystem-ID */
0068 #define PCI_CLASSCODE_GENWQE5_SRIOV 0x1200 /* UNKNOWN */
0069
0070 #define GENWQE_SLU_ARCH_REQ     2 /* Required SLU architecture level */
0071
0072 /**
0073  * struct genwqe_reg - Genwqe data dump functionality
0074  */
0075 struct genwqe_reg {
0076     u32 addr;
0077     u32 idx;
0078     u64 val;
0079 };
0080
0081 /*
0082  * enum genwqe_dbg_type - Specify chip unit to dump/debug
0083  */
0084 enum genwqe_dbg_type {
0085     GENWQE_DBG_UNIT0 = 0,  /* captured before prev errs cleared */
0086     GENWQE_DBG_UNIT1 = 1,
0087     GENWQE_DBG_UNIT2 = 2,
0088     GENWQE_DBG_UNIT3 = 3,
0089     GENWQE_DBG_UNIT4 = 4,
0090     GENWQE_DBG_UNIT5 = 5,
0091     GENWQE_DBG_UNIT6 = 6,
0092     GENWQE_DBG_UNIT7 = 7,
0093     GENWQE_DBG_REGS  = 8,
0094     GENWQE_DBG_DMA   = 9,
0095     GENWQE_DBG_UNITS = 10, /* max number of possible debug units  */
0096 };
0097
0098 /* Software error injection to simulate card failures */
0099 #define GENWQE_INJECT_HARDWARE_FAILURE  0x00000001 /* injects -1 reg reads */
0100 #define GENWQE_INJECT_BUS_RESET_FAILURE 0x00000002 /* pci_bus_reset fail */
0101 #define GENWQE_INJECT_GFIR_FATAL    0x00000004 /* GFIR = 0x0000ffff */
0102 #define GENWQE_INJECT_GFIR_INFO     0x00000008 /* GFIR = 0xffff0000 */
0103
0104 /*
0105  * Genwqe card description and management data.
0106  *
0107  * Error-handling in case of card malfunction
0108  * ------------------------------------------
0109  *
0110  * If the card is detected to be defective the outside environment
0111  * will cause the PCI layer to call deinit (the cleanup function for
0112  * probe). This is the same effect like doing a unbind/bind operation
0113  * on the card.
0114  *
0115  * The genwqe card driver implements a health checking thread which
0116  * verifies the card function. If this detects a problem the cards
0117  * device is being shutdown and restarted again, along with a reset of
0118  * the card and queue.
0119  *
0120  * All functions accessing the card device return either -EIO or -ENODEV
0121  * code to indicate the malfunction to the user. The user has to close
0122  * the file descriptor and open a new one, once the card becomes
0123  * available again.
0124  *
0125  * If the open file descriptor is setup to receive SIGIO, the signal is
0126  * genereated for the application which has to provide a handler to
0127  * react on it. If the application does not close the open
0128  * file descriptor a SIGKILL is send to enforce freeing the cards
0129  * resources.
0130  *
0131  * I did not find a different way to prevent kernel problems due to
0132  * reference counters for the cards character devices getting out of
0133  * sync. The character device deallocation does not block, even if
0134  * there is still an open file descriptor pending. If this pending
0135  * descriptor is closed, the data structures used by the character
0136  * device is reinstantiated, which will lead to the reference counter
0137  * dropping below the allowed values.
0138  *
0139  * Card recovery
0140  * -------------
0141  *
0142  * To test the internal driver recovery the following command can be used:
0143  *   sudo sh -c 'echo 0xfffff > /sys/class/genwqe/genwqe0_card/err_inject'
0144  */
0145
0146
0147 /**
0148  * struct dma_mapping_type - Mapping type definition
0149  *
0150  * To avoid memcpying data arround we use user memory directly. To do
0151  * this we need to pin/swap-in the memory and request a DMA address
0152  * for it.
0153  */
0154 enum dma_mapping_type {
0155     GENWQE_MAPPING_RAW = 0,     /* contignous memory buffer */
0156     GENWQE_MAPPING_SGL_TEMP,    /* sglist dynamically used */
0157     GENWQE_MAPPING_SGL_PINNED,  /* sglist used with pinning */
0158 };
0159
0160 /**
0161  * struct dma_mapping - Information about memory mappings done by the driver
0162  */
0163 struct dma_mapping {
0164     enum dma_mapping_type type;
0165
0166     void *u_vaddr;          /* user-space vaddr/non-aligned */
0167     void *k_vaddr;          /* kernel-space vaddr/non-aligned */
0168     dma_addr_t dma_addr;        /* physical DMA address */
0169
0170     struct page **page_list;    /* list of pages used by user buff */
0171     dma_addr_t *dma_list;       /* list of dma addresses per page */
0172     unsigned int nr_pages;      /* number of pages */
0173     unsigned int size;      /* size in bytes */
0174
0175     struct list_head card_list; /* list of usr_maps for card */
0176     struct list_head pin_list;  /* list of pinned memory for dev */
0177     int write;          /* writable map? useful in unmapping */
0178 };
0179
0180 static inline void genwqe_mapping_init(struct dma_mapping *m,
0181                        enum dma_mapping_type type)
0182 {
0183     memset(m, 0, sizeof(*m));
0184     m->type = type;
0185     m->write = 1; /* Assume the maps we create are R/W */
0186 }
0187
0188 /**
0189  * struct ddcb_queue - DDCB queue data
0190  * @ddcb_max:          Number of DDCBs on the queue
0191  * @ddcb_next:         Next free DDCB
0192  * @ddcb_act:          Next DDCB supposed to finish
0193  * @ddcb_seq:          Sequence number of last DDCB
0194  * @ddcbs_in_flight:   Currently enqueued DDCBs
0195  * @ddcbs_completed:   Number of already completed DDCBs
0196  * @return_on_busy:    Number of -EBUSY returns on full queue
0197  * @wait_on_busy:      Number of waits on full queue
0198  * @ddcb_daddr:        DMA address of first DDCB in the queue
0199  * @ddcb_vaddr:        Kernel virtual address of first DDCB in the queue
0200  * @ddcb_req:          Associated requests (one per DDCB)
0201  * @ddcb_waitqs:       Associated wait queues (one per DDCB)
0202  * @ddcb_lock:         Lock to protect queuing operations
0203  * @ddcb_waitq:        Wait on next DDCB finishing
0204  */
0205
0206 struct ddcb_queue {
0207     int ddcb_max;           /* amount of DDCBs  */
0208     int ddcb_next;          /* next available DDCB num */
0209     int ddcb_act;           /* DDCB to be processed */
0210     u16 ddcb_seq;           /* slc seq num */
0211     unsigned int ddcbs_in_flight;   /* number of ddcbs in processing */
0212     unsigned int ddcbs_completed;
0213     unsigned int ddcbs_max_in_flight;
0214     unsigned int return_on_busy;    /* how many times -EBUSY? */
0215     unsigned int wait_on_busy;
0216
0217     dma_addr_t ddcb_daddr;      /* DMA address */
0218     struct ddcb *ddcb_vaddr;    /* kernel virtual addr for DDCBs */
0219     struct ddcb_requ **ddcb_req;    /* ddcb processing parameter */
0220     wait_queue_head_t *ddcb_waitqs; /* waitqueue per ddcb */
0221
0222     spinlock_t ddcb_lock;       /* exclusive access to queue */
0223     wait_queue_head_t busy_waitq;   /* wait for ddcb processing */
0224
0225     /* registers or the respective queue to be used */
0226     u32 IO_QUEUE_CONFIG;
0227     u32 IO_QUEUE_STATUS;
0228     u32 IO_QUEUE_SEGMENT;
0229     u32 IO_QUEUE_INITSQN;
0230     u32 IO_QUEUE_WRAP;
0231     u32 IO_QUEUE_OFFSET;
0232     u32 IO_QUEUE_WTIME;
0233     u32 IO_QUEUE_ERRCNTS;
0234     u32 IO_QUEUE_LRW;
0235 };
0236
0237 /*
0238  * GFIR, SLU_UNITCFG, APP_UNITCFG
0239  *   8 Units with FIR/FEC + 64 * 2ndary FIRS/FEC.
0240  */
0241 #define GENWQE_FFDC_REGS    (3 + (8 * (2 + 2 * 64)))
0242
0243 struct genwqe_ffdc {
0244     unsigned int entries;
0245     struct genwqe_reg *regs;
0246 };
0247
0248 /**
0249  * struct genwqe_dev - GenWQE device information
0250  * @card_state:       Card operation state, see above
0251  * @ffdc:             First Failure Data Capture buffers for each unit
0252  * @card_thread:      Working thread to operate the DDCB queue
0253  * @card_waitq:       Wait queue used in card_thread
0254  * @queue:            DDCB queue
0255  * @health_thread:    Card monitoring thread (only for PFs)
0256  * @health_waitq:     Wait queue used in health_thread
0257  * @pci_dev:          Associated PCI device (function)
0258  * @mmio:             Base address of 64-bit register space
0259  * @mmio_len:         Length of register area
0260  * @file_lock:        Lock to protect access to file_list
0261  * @file_list:        List of all processes with open GenWQE file descriptors
0262  *
0263  * This struct contains all information needed to communicate with a
0264  * GenWQE card. It is initialized when a GenWQE device is found and
0265  * destroyed when it goes away. It holds data to maintain the queue as
0266  * well as data needed to feed the user interfaces.
0267  */
0268 struct genwqe_dev {
0269     enum genwqe_card_state card_state;
0270     spinlock_t print_lock;
0271
0272     int card_idx;           /* card index 0..CARD_NO_MAX-1 */
0273     u64 flags;          /* general flags */
0274
0275     /* FFDC data gathering */
0276     struct genwqe_ffdc ffdc[GENWQE_DBG_UNITS];
0277
0278     /* DDCB workqueue */
0279     struct task_struct *card_thread;
0280     wait_queue_head_t queue_waitq;
0281     struct ddcb_queue queue;    /* genwqe DDCB queue */
0282     unsigned int irqs_processed;
0283
0284     /* Card health checking thread */
0285     struct task_struct *health_thread;
0286     wait_queue_head_t health_waitq;
0287
0288     int use_platform_recovery;  /* use platform recovery mechanisms */
0289
0290     /* char device */
0291     dev_t  devnum_genwqe;       /* major/minor num card */
0292     struct class *class_genwqe; /* reference to class object */
0293     struct device *dev;     /* for device creation */
0294     struct cdev cdev_genwqe;    /* char device for card */
0295
0296     struct dentry *debugfs_root;    /* debugfs card root directory */
0297     struct dentry *debugfs_genwqe;  /* debugfs driver root directory */
0298
0299     /* pci resources */
0300     struct pci_dev *pci_dev;    /* PCI device */
0301     void __iomem *mmio;     /* BAR-0 MMIO start */
0302     unsigned long mmio_len;
0303     int num_vfs;
0304     u32 vf_jobtimeout_msec[GENWQE_MAX_VFS];
0305     int is_privileged;      /* access to all regs possible */
0306
0307     /* config regs which we need often */
0308     u64 slu_unitcfg;
0309     u64 app_unitcfg;
0310     u64 softreset;
0311     u64 err_inject;
0312     u64 last_gfir;
0313     char app_name[5];
0314
0315     spinlock_t file_lock;       /* lock for open files */
0316     struct list_head file_list; /* list of open files */
0317
0318     /* debugfs parameters */
0319     int ddcb_software_timeout;  /* wait until DDCB times out */
0320     int skip_recovery;      /* circumvention if recovery fails */
0321     int kill_timeout;       /* wait after sending SIGKILL */
0322 };
0323
0324 /**
0325  * enum genwqe_requ_state - State of a DDCB execution request
0326  */
0327 enum genwqe_requ_state {
0328     GENWQE_REQU_NEW      = 0,
0329     GENWQE_REQU_ENQUEUED = 1,
0330     GENWQE_REQU_TAPPED   = 2,
0331     GENWQE_REQU_FINISHED = 3,
0332     GENWQE_REQU_STATE_MAX,
0333 };
0334
0335 /**
0336  * struct genwqe_sgl - Scatter gather list describing user-space memory
0337  * @sgl:            scatter gather list needs to be 128 byte aligned
0338  * @sgl_dma_addr:   dma address of sgl
0339  * @sgl_size:       size of area used for sgl
0340  * @user_addr:      user-space address of memory area
0341  * @user_size:      size of user-space memory area
0342  * @page:           buffer for partial pages if needed
0343  * @page_dma_addr:  dma address partial pages
0344  * @write:          should we write it back to userspace?
0345  */
0346 struct genwqe_sgl {
0347     dma_addr_t sgl_dma_addr;
0348     struct sg_entry *sgl;
0349     size_t sgl_size;    /* size of sgl */
0350
0351     void __user *user_addr; /* user-space base-address */
0352     size_t user_size;       /* size of memory area */
0353
0354     int write;
0355
0356     unsigned long nr_pages;
0357     unsigned long fpage_offs;
0358     size_t fpage_size;
0359     size_t lpage_size;
0360
0361     void *fpage;
0362     dma_addr_t fpage_dma_addr;
0363
0364     void *lpage;
0365     dma_addr_t lpage_dma_addr;
0366 };
0367
0368 int genwqe_alloc_sync_sgl(struct genwqe_dev *cd, struct genwqe_sgl *sgl,
0369               void __user *user_addr, size_t user_size, int write);
0370
0371 int genwqe_setup_sgl(struct genwqe_dev *cd, struct genwqe_sgl *sgl,
0372              dma_addr_t *dma_list);
0373
0374 int genwqe_free_sync_sgl(struct genwqe_dev *cd, struct genwqe_sgl *sgl);
0375
0376 /**
0377  * struct ddcb_requ - Kernel internal representation of the DDCB request
0378  * @cmd:          User space representation of the DDCB execution request
0379  */
0380 struct ddcb_requ {
0381     /* kernel specific content */
0382     enum genwqe_requ_state req_state; /* request status */
0383     int num;              /* ddcb_no for this request */
0384     struct ddcb_queue *queue;     /* associated queue */
0385
0386     struct dma_mapping  dma_mappings[DDCB_FIXUPS];
0387     struct genwqe_sgl sgls[DDCB_FIXUPS];
0388
0389     /* kernel/user shared content */
0390     struct genwqe_ddcb_cmd cmd; /* ddcb_no for this request */
0391     struct genwqe_debug_data debug_data;
0392 };
0393
0394 /**
0395  * struct genwqe_file - Information for open GenWQE devices
0396  */
0397 struct genwqe_file {
0398     struct genwqe_dev *cd;
0399     struct genwqe_driver *client;
0400     struct file *filp;
0401
0402     struct fasync_struct *async_queue;
0403     struct pid *opener;
0404     struct list_head list;      /* entry in list of open files */
0405
0406     spinlock_t map_lock;        /* lock for dma_mappings */
0407     struct list_head map_list;  /* list of dma_mappings */
0408
0409     spinlock_t pin_lock;        /* lock for pinned memory */
0410     struct list_head pin_list;  /* list of pinned memory */
0411 };
0412
0413 int  genwqe_setup_service_layer(struct genwqe_dev *cd); /* for PF only */
0414 int  genwqe_finish_queue(struct genwqe_dev *cd);
0415 int  genwqe_release_service_layer(struct genwqe_dev *cd);
0416
0417 /**
0418  * genwqe_get_slu_id() - Read Service Layer Unit Id
0419  * Return: 0x00: Development code
0420  *         0x01: SLC1 (old)
0421  *         0x02: SLC2 (sept2012)
0422  *         0x03: SLC2 (feb2013, generic driver)
0423  */
0424 static inline int genwqe_get_slu_id(struct genwqe_dev *cd)
0425 {
0426     return (int)((cd->slu_unitcfg >> 32) & 0xff);
0427 }
0428
0429 int  genwqe_ddcbs_in_flight(struct genwqe_dev *cd);
0430
0431 u8   genwqe_card_type(struct genwqe_dev *cd);
0432 int  genwqe_card_reset(struct genwqe_dev *cd);
0433 int  genwqe_set_interrupt_capability(struct genwqe_dev *cd, int count);
0434 void genwqe_reset_interrupt_capability(struct genwqe_dev *cd);
0435
0436 int  genwqe_device_create(struct genwqe_dev *cd);
0437 int  genwqe_device_remove(struct genwqe_dev *cd);
0438
0439 /* debugfs */
0440 void genwqe_init_debugfs(struct genwqe_dev *cd);
0441 void genqwe_exit_debugfs(struct genwqe_dev *cd);
0442
0443 int  genwqe_read_softreset(struct genwqe_dev *cd);
0444
0445 /* Hardware Circumventions */
0446 int  genwqe_recovery_on_fatal_gfir_required(struct genwqe_dev *cd);
0447 int  genwqe_flash_readback_fails(struct genwqe_dev *cd);
0448
0449 /**
0450  * genwqe_write_vreg() - Write register in VF window
0451  * @cd:    genwqe device
0452  * @reg:   register address
0453  * @val:   value to write
0454  * @func:  0: PF, 1: VF0, ..., 15: VF14
0455  */
0456 int genwqe_write_vreg(struct genwqe_dev *cd, u32 reg, u64 val, int func);
0457
0458 /**
0459  * genwqe_read_vreg() - Read register in VF window
0460  * @cd:    genwqe device
0461  * @reg:   register address
0462  * @func:  0: PF, 1: VF0, ..., 15: VF14
0463  *
0464  * Return: content of the register
0465  */
0466 u64 genwqe_read_vreg(struct genwqe_dev *cd, u32 reg, int func);
0467
0468 /* FFDC Buffer Management */
0469 int  genwqe_ffdc_buff_size(struct genwqe_dev *cd, int unit_id);
0470 int  genwqe_ffdc_buff_read(struct genwqe_dev *cd, int unit_id,
0471                struct genwqe_reg *regs, unsigned int max_regs);
0472 int  genwqe_read_ffdc_regs(struct genwqe_dev *cd, struct genwqe_reg *regs,
0473                unsigned int max_regs, int all);
0474 int  genwqe_ffdc_dump_dma(struct genwqe_dev *cd,
0475               struct genwqe_reg *regs, unsigned int max_regs);
0476
0477 int  genwqe_init_debug_data(struct genwqe_dev *cd,
0478                 struct genwqe_debug_data *d);
0479
0480 void genwqe_init_crc32(void);
0481 int  genwqe_read_app_id(struct genwqe_dev *cd, char *app_name, int len);
0482
0483 /* Memory allocation/deallocation; dma address handling */
0484 int  genwqe_user_vmap(struct genwqe_dev *cd, struct dma_mapping *m,
0485               void *uaddr, unsigned long size);
0486
0487 int  genwqe_user_vunmap(struct genwqe_dev *cd, struct dma_mapping *m);
0488
0489 static inline bool dma_mapping_used(struct dma_mapping *m)
0490 {
0491     if (!m)
0492         return false;
0493     return m->size != 0;
0494 }
0495
0496 /**
0497  * __genwqe_execute_ddcb() - Execute DDCB request with addr translation
0498  *
0499  * This function will do the address translation changes to the DDCBs
0500  * according to the definitions required by the ATS field. It looks up
0501  * the memory allocation buffer or does vmap/vunmap for the respective
0502  * user-space buffers, inclusive page pinning and scatter gather list
0503  * buildup and teardown.
0504  */
0505 int  __genwqe_execute_ddcb(struct genwqe_dev *cd,
0506                struct genwqe_ddcb_cmd *cmd, unsigned int f_flags);
0507
0508 /**
0509  * __genwqe_execute_raw_ddcb() - Execute DDCB request without addr translation
0510  *
0511  * This version will not do address translation or any modification of
0512  * the DDCB data. It is used e.g. for the MoveFlash DDCB which is
0513  * entirely prepared by the driver itself. That means the appropriate
0514  * DMA addresses are already in the DDCB and do not need any
0515  * modification.
0516  */
0517 int  __genwqe_execute_raw_ddcb(struct genwqe_dev *cd,
0518                    struct genwqe_ddcb_cmd *cmd,
0519                    unsigned int f_flags);
0520 int  __genwqe_enqueue_ddcb(struct genwqe_dev *cd,
0521                struct ddcb_requ *req,
0522                unsigned int f_flags);
0523
0524 int  __genwqe_wait_ddcb(struct genwqe_dev *cd, struct ddcb_requ *req);
0525 int  __genwqe_purge_ddcb(struct genwqe_dev *cd, struct ddcb_requ *req);
0526
0527 /* register access */
0528 int __genwqe_writeq(struct genwqe_dev *cd, u64 byte_offs, u64 val);
0529 u64 __genwqe_readq(struct genwqe_dev *cd, u64 byte_offs);
0530 int __genwqe_writel(struct genwqe_dev *cd, u64 byte_offs, u32 val);
0531 u32 __genwqe_readl(struct genwqe_dev *cd, u64 byte_offs);
0532
0533 void *__genwqe_alloc_consistent(struct genwqe_dev *cd, size_t size,
0534                  dma_addr_t *dma_handle);
0535 void __genwqe_free_consistent(struct genwqe_dev *cd, size_t size,
0536                   void *vaddr, dma_addr_t dma_handle);
0537
0538 /* Base clock frequency in MHz */
0539 int  genwqe_base_clock_frequency(struct genwqe_dev *cd);
0540
0541 /* Before FFDC is captured the traps should be stopped. */
0542 void genwqe_stop_traps(struct genwqe_dev *cd);
0543 void genwqe_start_traps(struct genwqe_dev *cd);
0544
0545 /* Hardware circumvention */
0546 bool genwqe_need_err_masking(struct genwqe_dev *cd);
0547
0548 /**
0549  * genwqe_is_privileged() - Determine operation mode for PCI function
0550  *
0551  * On Intel with SRIOV support we see:
0552  *   PF: is_physfn = 1 is_virtfn = 0
0553  *   VF: is_physfn = 0 is_virtfn = 1
0554  *
0555  * On Systems with no SRIOV support _and_ virtualized systems we get:
0556  *       is_physfn = 0 is_virtfn = 0
0557  *
0558  * Other vendors have individual pci device ids to distinguish between
0559  * virtual function drivers and physical function drivers. GenWQE
0560  * unfortunately has just on pci device id for both, VFs and PF.
0561  *
0562  * The following code is used to distinguish if the card is running in
0563  * privileged mode, either as true PF or in a virtualized system with
0564  * full register access e.g. currently on PowerPC.
0565  *
0566  * if (pci_dev->is_virtfn)
0567  *          cd->is_privileged = 0;
0568  *  else
0569  *          cd->is_privileged = (__genwqe_readq(cd, IO_SLU_BITSTREAM)
0570  *               != IO_ILLEGAL_VALUE);
0571  */
0572 static inline int genwqe_is_privileged(struct genwqe_dev *cd)
0573 {
0574     return cd->is_privileged;
0575 }
0576
0577 #endif  /* __CARD_BASE_H__ */