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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *   Copyright (C) 2016 T-Platforms. All Rights Reserved.
0004  *
0005  * IDT PCIe-switch NTB Linux driver
0006  *
0007  * Contact Information:
0008  * Serge Semin <fancer.lancer@gmail.com>, <Sergey.Semin@t-platforms.ru>
0009  */
0010 /*
0011  *           NOTE of the IDT 89HPESx SMBus-slave interface driver
0012  *    This driver primarily is developed to have an access to EEPROM device of
0013  * IDT PCIe-switches. IDT provides a simple SMBus interface to perform IO-
0014  * operations from/to EEPROM, which is located at private (so called Master)
0015  * SMBus of switches. Using that interface this the driver creates a simple
0016  * binary sysfs-file in the device directory:
0017  * /sys/bus/i2c/devices/<bus>-<devaddr>/eeprom
0018  * In case if read-only flag is specified in the dts-node of device desription,
0019  * User-space applications won't be able to write to the EEPROM sysfs-node.
0020  *    Additionally IDT 89HPESx SMBus interface has an ability to write/read
0021  * data of device CSRs. This driver exposes debugf-file to perform simple IO
0022  * operations using that ability for just basic debug purpose. Particularly
0023  * next file is created in the specific debugfs-directory:
0024  * /sys/kernel/debug/idt_csr/
0025  * Format of the debugfs-node is:
0026  * $ cat /sys/kernel/debug/idt_csr/<bus>-<devaddr>/<devname>;
0027  * <CSR address>:<CSR value>
0028  * So reading the content of the file gives current CSR address and it value.
0029  * If User-space application wishes to change current CSR address,
0030  * it can just write a proper value to the sysfs-file:
0031  * $ echo "<CSR address>" > /sys/kernel/debug/idt_csr/<bus>-<devaddr>/<devname>
0032  * If it wants to change the CSR value as well, the format of the write
0033  * operation is:
0034  * $ echo "<CSR address>:<CSR value>" > \
0035  *        /sys/kernel/debug/idt_csr/<bus>-<devaddr>/<devname>;
0036  * CSR address and value can be any of hexadecimal, decimal or octal format.
0037  */
0038 
0039 #include <linux/kernel.h>
0040 #include <linux/init.h>
0041 #include <linux/module.h>
0042 #include <linux/types.h>
0043 #include <linux/sizes.h>
0044 #include <linux/slab.h>
0045 #include <linux/mutex.h>
0046 #include <linux/sysfs.h>
0047 #include <linux/debugfs.h>
0048 #include <linux/mod_devicetable.h>
0049 #include <linux/property.h>
0050 #include <linux/i2c.h>
0051 #include <linux/pci_ids.h>
0052 #include <linux/delay.h>
0053 
0054 #define IDT_NAME        "89hpesx"
0055 #define IDT_89HPESX_DESC    "IDT 89HPESx SMBus-slave interface driver"
0056 #define IDT_89HPESX_VER     "1.0"
0057 
0058 MODULE_DESCRIPTION(IDT_89HPESX_DESC);
0059 MODULE_VERSION(IDT_89HPESX_VER);
0060 MODULE_LICENSE("GPL v2");
0061 MODULE_AUTHOR("T-platforms");
0062 
0063 /*
0064  * csr_dbgdir - CSR read/write operations Debugfs directory
0065  */
0066 static struct dentry *csr_dbgdir;
0067 
0068 /*
0069  * struct idt_89hpesx_dev - IDT 89HPESx device data structure
0070  * @eesize: Size of EEPROM in bytes (calculated from "idt,eecompatible")
0071  * @eero:   EEPROM Read-only flag
0072  * @eeaddr: EEPROM custom address
0073  *
0074  * @inieecmd:   Initial cmd value for EEPROM read/write operations
0075  * @inicsrcmd:  Initial cmd value for CSR read/write operations
0076  * @iniccode:   Initialial command code value for IO-operations
0077  *
0078  * @csr:    CSR address to perform read operation
0079  *
0080  * @smb_write:  SMBus write method
0081  * @smb_read:   SMBus read method
0082  * @smb_mtx:    SMBus mutex
0083  *
0084  * @client: i2c client used to perform IO operations
0085  *
0086  * @ee_file:    EEPROM read/write sysfs-file
0087  */
0088 struct idt_smb_seq;
0089 struct idt_89hpesx_dev {
0090     u32 eesize;
0091     bool eero;
0092     u8 eeaddr;
0093 
0094     u8 inieecmd;
0095     u8 inicsrcmd;
0096     u8 iniccode;
0097 
0098     u16 csr;
0099 
0100     int (*smb_write)(struct idt_89hpesx_dev *, const struct idt_smb_seq *);
0101     int (*smb_read)(struct idt_89hpesx_dev *, struct idt_smb_seq *);
0102     struct mutex smb_mtx;
0103 
0104     struct i2c_client *client;
0105 
0106     struct bin_attribute *ee_file;
0107     struct dentry *csr_dir;
0108 };
0109 
0110 /*
0111  * struct idt_smb_seq - sequence of data to be read/written from/to IDT 89HPESx
0112  * @ccode:  SMBus command code
0113  * @bytecnt:    Byte count of operation
0114  * @data:   Data to by written
0115  */
0116 struct idt_smb_seq {
0117     u8 ccode;
0118     u8 bytecnt;
0119     u8 *data;
0120 };
0121 
0122 /*
0123  * struct idt_eeprom_seq - sequence of data to be read/written from/to EEPROM
0124  * @cmd:    Transaction CMD
0125  * @eeaddr: EEPROM custom address
0126  * @memaddr:    Internal memory address of EEPROM
0127  * @data:   Data to be written at the memory address
0128  */
0129 struct idt_eeprom_seq {
0130     u8 cmd;
0131     u8 eeaddr;
0132     u16 memaddr;
0133     u8 data;
0134 } __packed;
0135 
0136 /*
0137  * struct idt_csr_seq - sequence of data to be read/written from/to CSR
0138  * @cmd:    Transaction CMD
0139  * @csraddr:    Internal IDT device CSR address
0140  * @data:   Data to be read/written from/to the CSR address
0141  */
0142 struct idt_csr_seq {
0143     u8 cmd;
0144     u16 csraddr;
0145     u32 data;
0146 } __packed;
0147 
0148 /*
0149  * SMBus command code macros
0150  * @CCODE_END:      Indicates the end of transaction
0151  * @CCODE_START:    Indicates the start of transaction
0152  * @CCODE_CSR:      CSR read/write transaction
0153  * @CCODE_EEPROM:   EEPROM read/write transaction
0154  * @CCODE_BYTE:     Supplied data has BYTE length
0155  * @CCODE_WORD:     Supplied data has WORD length
0156  * @CCODE_BLOCK:    Supplied data has variable length passed in bytecnt
0157  *          byte right following CCODE byte
0158  */
0159 #define CCODE_END   ((u8)0x01)
0160 #define CCODE_START ((u8)0x02)
0161 #define CCODE_CSR   ((u8)0x00)
0162 #define CCODE_EEPROM    ((u8)0x04)
0163 #define CCODE_BYTE  ((u8)0x00)
0164 #define CCODE_WORD  ((u8)0x20)
0165 #define CCODE_BLOCK ((u8)0x40)
0166 #define CCODE_PEC   ((u8)0x80)
0167 
0168 /*
0169  * EEPROM command macros
0170  * @EEPROM_OP_WRITE:    EEPROM write operation
0171  * @EEPROM_OP_READ: EEPROM read operation
0172  * @EEPROM_USA:     Use specified address of EEPROM
0173  * @EEPROM_NAERR:   EEPROM device is not ready to respond
0174  * @EEPROM_LAERR:   EEPROM arbitration loss error
0175  * @EEPROM_MSS:     EEPROM misplace start & stop bits error
0176  * @EEPROM_WR_CNT:  Bytes count to perform write operation
0177  * @EEPROM_WRRD_CNT:    Bytes count to write before reading
0178  * @EEPROM_RD_CNT:  Bytes count to perform read operation
0179  * @EEPROM_DEF_SIZE:    Fall back size of EEPROM
0180  * @EEPROM_DEF_ADDR:    Defatul EEPROM address
0181  * @EEPROM_TOUT:    Timeout before retry read operation if eeprom is busy
0182  */
0183 #define EEPROM_OP_WRITE ((u8)0x00)
0184 #define EEPROM_OP_READ  ((u8)0x01)
0185 #define EEPROM_USA  ((u8)0x02)
0186 #define EEPROM_NAERR    ((u8)0x08)
0187 #define EEPROM_LAERR    ((u8)0x10)
0188 #define EEPROM_MSS  ((u8)0x20)
0189 #define EEPROM_WR_CNT   ((u8)5)
0190 #define EEPROM_WRRD_CNT ((u8)4)
0191 #define EEPROM_RD_CNT   ((u8)5)
0192 #define EEPROM_DEF_SIZE ((u16)4096)
0193 #define EEPROM_DEF_ADDR ((u8)0x50)
0194 #define EEPROM_TOUT (100)
0195 
0196 /*
0197  * CSR command macros
0198  * @CSR_DWE:        Enable all four bytes of the operation
0199  * @CSR_OP_WRITE:   CSR write operation
0200  * @CSR_OP_READ:    CSR read operation
0201  * @CSR_RERR:       Read operation error
0202  * @CSR_WERR:       Write operation error
0203  * @CSR_WR_CNT:     Bytes count to perform write operation
0204  * @CSR_WRRD_CNT:   Bytes count to write before reading
0205  * @CSR_RD_CNT:     Bytes count to perform read operation
0206  * @CSR_MAX:        Maximum CSR address
0207  * @CSR_DEF:        Default CSR address
0208  * @CSR_REAL_ADDR:  CSR real unshifted address
0209  */
0210 #define CSR_DWE         ((u8)0x0F)
0211 #define CSR_OP_WRITE        ((u8)0x00)
0212 #define CSR_OP_READ     ((u8)0x10)
0213 #define CSR_RERR        ((u8)0x40)
0214 #define CSR_WERR        ((u8)0x80)
0215 #define CSR_WR_CNT      ((u8)7)
0216 #define CSR_WRRD_CNT        ((u8)3)
0217 #define CSR_RD_CNT      ((u8)7)
0218 #define CSR_MAX         ((u32)0x3FFFF)
0219 #define CSR_DEF         ((u16)0x0000)
0220 #define CSR_REAL_ADDR(val)  ((unsigned int)val << 2)
0221 
0222 /*
0223  * IDT 89HPESx basic register
0224  * @IDT_VIDDID_CSR: PCIe VID and DID of IDT 89HPESx
0225  * @IDT_VID_MASK:   Mask of VID
0226  */
0227 #define IDT_VIDDID_CSR  ((u32)0x0000)
0228 #define IDT_VID_MASK    ((u32)0xFFFF)
0229 
0230 /*
0231  * IDT 89HPESx can send NACK when new command is sent before previous one
0232  * fininshed execution. In this case driver retries operation
0233  * certain times.
0234  * @RETRY_CNT:      Number of retries before giving up and fail
0235  * @idt_smb_safe:   Generate a retry loop on corresponding SMBus method
0236  */
0237 #define RETRY_CNT (128)
0238 #define idt_smb_safe(ops, args...) ({ \
0239     int __retry = RETRY_CNT; \
0240     s32 __sts; \
0241     do { \
0242         __sts = i2c_smbus_ ## ops ## _data(args); \
0243     } while (__retry-- && __sts < 0); \
0244     __sts; \
0245 })
0246 
0247 /*===========================================================================
0248  *                         i2c bus level IO-operations
0249  *===========================================================================
0250  */
0251 
0252 /*
0253  * idt_smb_write_byte() - SMBus write method when I2C_SMBUS_BYTE_DATA operation
0254  *                        is only available
0255  * @pdev:   Pointer to the driver data
0256  * @seq:    Sequence of data to be written
0257  */
0258 static int idt_smb_write_byte(struct idt_89hpesx_dev *pdev,
0259                   const struct idt_smb_seq *seq)
0260 {
0261     s32 sts;
0262     u8 ccode;
0263     int idx;
0264 
0265     /* Loop over the supplied data sending byte one-by-one */
0266     for (idx = 0; idx < seq->bytecnt; idx++) {
0267         /* Collect the command code byte */
0268         ccode = seq->ccode | CCODE_BYTE;
0269         if (idx == 0)
0270             ccode |= CCODE_START;
0271         if (idx == seq->bytecnt - 1)
0272             ccode |= CCODE_END;
0273 
0274         /* Send data to the device */
0275         sts = idt_smb_safe(write_byte, pdev->client, ccode,
0276             seq->data[idx]);
0277         if (sts != 0)
0278             return (int)sts;
0279     }
0280 
0281     return 0;
0282 }
0283 
0284 /*
0285  * idt_smb_read_byte() - SMBus read method when I2C_SMBUS_BYTE_DATA operation
0286  *                        is only available
0287  * @pdev:   Pointer to the driver data
0288  * @seq:    Buffer to read data to
0289  */
0290 static int idt_smb_read_byte(struct idt_89hpesx_dev *pdev,
0291                  struct idt_smb_seq *seq)
0292 {
0293     s32 sts;
0294     u8 ccode;
0295     int idx;
0296 
0297     /* Loop over the supplied buffer receiving byte one-by-one */
0298     for (idx = 0; idx < seq->bytecnt; idx++) {
0299         /* Collect the command code byte */
0300         ccode = seq->ccode | CCODE_BYTE;
0301         if (idx == 0)
0302             ccode |= CCODE_START;
0303         if (idx == seq->bytecnt - 1)
0304             ccode |= CCODE_END;
0305 
0306         /* Read data from the device */
0307         sts = idt_smb_safe(read_byte, pdev->client, ccode);
0308         if (sts < 0)
0309             return (int)sts;
0310 
0311         seq->data[idx] = (u8)sts;
0312     }
0313 
0314     return 0;
0315 }
0316 
0317 /*
0318  * idt_smb_write_word() - SMBus write method when I2C_SMBUS_BYTE_DATA and
0319  *                        I2C_FUNC_SMBUS_WORD_DATA operations are available
0320  * @pdev:   Pointer to the driver data
0321  * @seq:    Sequence of data to be written
0322  */
0323 static int idt_smb_write_word(struct idt_89hpesx_dev *pdev,
0324                   const struct idt_smb_seq *seq)
0325 {
0326     s32 sts;
0327     u8 ccode;
0328     int idx, evencnt;
0329 
0330     /* Calculate the even count of data to send */
0331     evencnt = seq->bytecnt - (seq->bytecnt % 2);
0332 
0333     /* Loop over the supplied data sending two bytes at a time */
0334     for (idx = 0; idx < evencnt; idx += 2) {
0335         /* Collect the command code byte */
0336         ccode = seq->ccode | CCODE_WORD;
0337         if (idx == 0)
0338             ccode |= CCODE_START;
0339         if (idx == evencnt - 2)
0340             ccode |= CCODE_END;
0341 
0342         /* Send word data to the device */
0343         sts = idt_smb_safe(write_word, pdev->client, ccode,
0344             *(u16 *)&seq->data[idx]);
0345         if (sts != 0)
0346             return (int)sts;
0347     }
0348 
0349     /* If there is odd number of bytes then send just one last byte */
0350     if (seq->bytecnt != evencnt) {
0351         /* Collect the command code byte */
0352         ccode = seq->ccode | CCODE_BYTE | CCODE_END;
0353         if (idx == 0)
0354             ccode |= CCODE_START;
0355 
0356         /* Send byte data to the device */
0357         sts = idt_smb_safe(write_byte, pdev->client, ccode,
0358             seq->data[idx]);
0359         if (sts != 0)
0360             return (int)sts;
0361     }
0362 
0363     return 0;
0364 }
0365 
0366 /*
0367  * idt_smb_read_word() - SMBus read method when I2C_SMBUS_BYTE_DATA and
0368  *                       I2C_FUNC_SMBUS_WORD_DATA operations are available
0369  * @pdev:   Pointer to the driver data
0370  * @seq:    Buffer to read data to
0371  */
0372 static int idt_smb_read_word(struct idt_89hpesx_dev *pdev,
0373                  struct idt_smb_seq *seq)
0374 {
0375     s32 sts;
0376     u8 ccode;
0377     int idx, evencnt;
0378 
0379     /* Calculate the even count of data to send */
0380     evencnt = seq->bytecnt - (seq->bytecnt % 2);
0381 
0382     /* Loop over the supplied data reading two bytes at a time */
0383     for (idx = 0; idx < evencnt; idx += 2) {
0384         /* Collect the command code byte */
0385         ccode = seq->ccode | CCODE_WORD;
0386         if (idx == 0)
0387             ccode |= CCODE_START;
0388         if (idx == evencnt - 2)
0389             ccode |= CCODE_END;
0390 
0391         /* Read word data from the device */
0392         sts = idt_smb_safe(read_word, pdev->client, ccode);
0393         if (sts < 0)
0394             return (int)sts;
0395 
0396         *(u16 *)&seq->data[idx] = (u16)sts;
0397     }
0398 
0399     /* If there is odd number of bytes then receive just one last byte */
0400     if (seq->bytecnt != evencnt) {
0401         /* Collect the command code byte */
0402         ccode = seq->ccode | CCODE_BYTE | CCODE_END;
0403         if (idx == 0)
0404             ccode |= CCODE_START;
0405 
0406         /* Read last data byte from the device */
0407         sts = idt_smb_safe(read_byte, pdev->client, ccode);
0408         if (sts < 0)
0409             return (int)sts;
0410 
0411         seq->data[idx] = (u8)sts;
0412     }
0413 
0414     return 0;
0415 }
0416 
0417 /*
0418  * idt_smb_write_block() - SMBus write method when I2C_SMBUS_BLOCK_DATA
0419  *                         operation is available
0420  * @pdev:   Pointer to the driver data
0421  * @seq:    Sequence of data to be written
0422  */
0423 static int idt_smb_write_block(struct idt_89hpesx_dev *pdev,
0424                    const struct idt_smb_seq *seq)
0425 {
0426     u8 ccode;
0427 
0428     /* Return error if too much data passed to send */
0429     if (seq->bytecnt > I2C_SMBUS_BLOCK_MAX)
0430         return -EINVAL;
0431 
0432     /* Collect the command code byte */
0433     ccode = seq->ccode | CCODE_BLOCK | CCODE_START | CCODE_END;
0434 
0435     /* Send block of data to the device */
0436     return idt_smb_safe(write_block, pdev->client, ccode, seq->bytecnt,
0437         seq->data);
0438 }
0439 
0440 /*
0441  * idt_smb_read_block() - SMBus read method when I2C_SMBUS_BLOCK_DATA
0442  *                        operation is available
0443  * @pdev:   Pointer to the driver data
0444  * @seq:    Buffer to read data to
0445  */
0446 static int idt_smb_read_block(struct idt_89hpesx_dev *pdev,
0447                   struct idt_smb_seq *seq)
0448 {
0449     s32 sts;
0450     u8 ccode;
0451 
0452     /* Return error if too much data passed to send */
0453     if (seq->bytecnt > I2C_SMBUS_BLOCK_MAX)
0454         return -EINVAL;
0455 
0456     /* Collect the command code byte */
0457     ccode = seq->ccode | CCODE_BLOCK | CCODE_START | CCODE_END;
0458 
0459     /* Read block of data from the device */
0460     sts = idt_smb_safe(read_block, pdev->client, ccode, seq->data);
0461     if (sts != seq->bytecnt)
0462         return (sts < 0 ? sts : -ENODATA);
0463 
0464     return 0;
0465 }
0466 
0467 /*
0468  * idt_smb_write_i2c_block() - SMBus write method when I2C_SMBUS_I2C_BLOCK_DATA
0469  *                             operation is available
0470  * @pdev:   Pointer to the driver data
0471  * @seq:    Sequence of data to be written
0472  *
0473  * NOTE It's usual SMBus write block operation, except the actual data length is
0474  * sent as first byte of data
0475  */
0476 static int idt_smb_write_i2c_block(struct idt_89hpesx_dev *pdev,
0477                    const struct idt_smb_seq *seq)
0478 {
0479     u8 ccode, buf[I2C_SMBUS_BLOCK_MAX + 1];
0480 
0481     /* Return error if too much data passed to send */
0482     if (seq->bytecnt > I2C_SMBUS_BLOCK_MAX)
0483         return -EINVAL;
0484 
0485     /* Collect the data to send. Length byte must be added prior the data */
0486     buf[0] = seq->bytecnt;
0487     memcpy(&buf[1], seq->data, seq->bytecnt);
0488 
0489     /* Collect the command code byte */
0490     ccode = seq->ccode | CCODE_BLOCK | CCODE_START | CCODE_END;
0491 
0492     /* Send length and block of data to the device */
0493     return idt_smb_safe(write_i2c_block, pdev->client, ccode,
0494         seq->bytecnt + 1, buf);
0495 }
0496 
0497 /*
0498  * idt_smb_read_i2c_block() - SMBus read method when I2C_SMBUS_I2C_BLOCK_DATA
0499  *                            operation is available
0500  * @pdev:   Pointer to the driver data
0501  * @seq:    Buffer to read data to
0502  *
0503  * NOTE It's usual SMBus read block operation, except the actual data length is
0504  * retrieved as first byte of data
0505  */
0506 static int idt_smb_read_i2c_block(struct idt_89hpesx_dev *pdev,
0507                   struct idt_smb_seq *seq)
0508 {
0509     u8 ccode, buf[I2C_SMBUS_BLOCK_MAX + 1];
0510     s32 sts;
0511 
0512     /* Return error if too much data passed to send */
0513     if (seq->bytecnt > I2C_SMBUS_BLOCK_MAX)
0514         return -EINVAL;
0515 
0516     /* Collect the command code byte */
0517     ccode = seq->ccode | CCODE_BLOCK | CCODE_START | CCODE_END;
0518 
0519     /* Read length and block of data from the device */
0520     sts = idt_smb_safe(read_i2c_block, pdev->client, ccode,
0521         seq->bytecnt + 1, buf);
0522     if (sts != seq->bytecnt + 1)
0523         return (sts < 0 ? sts : -ENODATA);
0524     if (buf[0] != seq->bytecnt)
0525         return -ENODATA;
0526 
0527     /* Copy retrieved data to the output data buffer */
0528     memcpy(seq->data, &buf[1], seq->bytecnt);
0529 
0530     return 0;
0531 }
0532 
0533 /*===========================================================================
0534  *                          EEPROM IO-operations
0535  *===========================================================================
0536  */
0537 
0538 /*
0539  * idt_eeprom_read_byte() - read just one byte from EEPROM
0540  * @pdev:   Pointer to the driver data
0541  * @memaddr:    Start EEPROM memory address
0542  * @data:   Data to be written to EEPROM
0543  */
0544 static int idt_eeprom_read_byte(struct idt_89hpesx_dev *pdev, u16 memaddr,
0545                 u8 *data)
0546 {
0547     struct device *dev = &pdev->client->dev;
0548     struct idt_eeprom_seq eeseq;
0549     struct idt_smb_seq smbseq;
0550     int ret, retry;
0551 
0552     /* Initialize SMBus sequence fields */
0553     smbseq.ccode = pdev->iniccode | CCODE_EEPROM;
0554     smbseq.data = (u8 *)&eeseq;
0555 
0556     /*
0557      * Sometimes EEPROM may respond with NACK if it's busy with previous
0558      * operation, so we need to perform a few attempts of read cycle
0559      */
0560     retry = RETRY_CNT;
0561     do {
0562         /* Send EEPROM memory address to read data from */
0563         smbseq.bytecnt = EEPROM_WRRD_CNT;
0564         eeseq.cmd = pdev->inieecmd | EEPROM_OP_READ;
0565         eeseq.eeaddr = pdev->eeaddr;
0566         eeseq.memaddr = cpu_to_le16(memaddr);
0567         ret = pdev->smb_write(pdev, &smbseq);
0568         if (ret != 0) {
0569             dev_err(dev, "Failed to init eeprom addr 0x%02x",
0570                 memaddr);
0571             break;
0572         }
0573 
0574         /* Perform read operation */
0575         smbseq.bytecnt = EEPROM_RD_CNT;
0576         ret = pdev->smb_read(pdev, &smbseq);
0577         if (ret != 0) {
0578             dev_err(dev, "Failed to read eeprom data 0x%02x",
0579                 memaddr);
0580             break;
0581         }
0582 
0583         /* Restart read operation if the device is busy */
0584         if (retry && (eeseq.cmd & EEPROM_NAERR)) {
0585             dev_dbg(dev, "EEPROM busy, retry reading after %d ms",
0586                 EEPROM_TOUT);
0587             msleep(EEPROM_TOUT);
0588             continue;
0589         }
0590 
0591         /* Check whether IDT successfully read data from EEPROM */
0592         if (eeseq.cmd & (EEPROM_NAERR | EEPROM_LAERR | EEPROM_MSS)) {
0593             dev_err(dev,
0594                 "Communication with eeprom failed, cmd 0x%hhx",
0595                 eeseq.cmd);
0596             ret = -EREMOTEIO;
0597             break;
0598         }
0599 
0600         /* Save retrieved data and exit the loop */
0601         *data = eeseq.data;
0602         break;
0603     } while (retry--);
0604 
0605     /* Return the status of operation */
0606     return ret;
0607 }
0608 
0609 /*
0610  * idt_eeprom_write() - EEPROM write operation
0611  * @pdev:   Pointer to the driver data
0612  * @memaddr:    Start EEPROM memory address
0613  * @len:    Length of data to be written
0614  * @data:   Data to be written to EEPROM
0615  */
0616 static int idt_eeprom_write(struct idt_89hpesx_dev *pdev, u16 memaddr, u16 len,
0617                 const u8 *data)
0618 {
0619     struct device *dev = &pdev->client->dev;
0620     struct idt_eeprom_seq eeseq;
0621     struct idt_smb_seq smbseq;
0622     int ret;
0623     u16 idx;
0624 
0625     /* Initialize SMBus sequence fields */
0626     smbseq.ccode = pdev->iniccode | CCODE_EEPROM;
0627     smbseq.data = (u8 *)&eeseq;
0628 
0629     /* Send data byte-by-byte, checking if it is successfully written */
0630     for (idx = 0; idx < len; idx++, memaddr++) {
0631         /* Lock IDT SMBus device */
0632         mutex_lock(&pdev->smb_mtx);
0633 
0634         /* Perform write operation */
0635         smbseq.bytecnt = EEPROM_WR_CNT;
0636         eeseq.cmd = pdev->inieecmd | EEPROM_OP_WRITE;
0637         eeseq.eeaddr = pdev->eeaddr;
0638         eeseq.memaddr = cpu_to_le16(memaddr);
0639         eeseq.data = data[idx];
0640         ret = pdev->smb_write(pdev, &smbseq);
0641         if (ret != 0) {
0642             dev_err(dev,
0643                 "Failed to write 0x%04hx:0x%02hhx to eeprom",
0644                 memaddr, data[idx]);
0645             goto err_mutex_unlock;
0646         }
0647 
0648         /*
0649          * Check whether the data is successfully written by reading
0650          * from the same EEPROM memory address.
0651          */
0652         eeseq.data = ~data[idx];
0653         ret = idt_eeprom_read_byte(pdev, memaddr, &eeseq.data);
0654         if (ret != 0)
0655             goto err_mutex_unlock;
0656 
0657         /* Check whether the read byte is the same as written one */
0658         if (eeseq.data != data[idx]) {
0659             dev_err(dev, "Values don't match 0x%02hhx != 0x%02hhx",
0660                 eeseq.data, data[idx]);
0661             ret = -EREMOTEIO;
0662             goto err_mutex_unlock;
0663         }
0664 
0665         /* Unlock IDT SMBus device */
0666 err_mutex_unlock:
0667         mutex_unlock(&pdev->smb_mtx);
0668         if (ret != 0)
0669             return ret;
0670     }
0671 
0672     return 0;
0673 }
0674 
0675 /*
0676  * idt_eeprom_read() - EEPROM read operation
0677  * @pdev:   Pointer to the driver data
0678  * @memaddr:    Start EEPROM memory address
0679  * @len:    Length of data to read
0680  * @buf:    Buffer to read data to
0681  */
0682 static int idt_eeprom_read(struct idt_89hpesx_dev *pdev, u16 memaddr, u16 len,
0683                u8 *buf)
0684 {
0685     int ret;
0686     u16 idx;
0687 
0688     /* Read data byte-by-byte, retrying if it wasn't successful */
0689     for (idx = 0; idx < len; idx++, memaddr++) {
0690         /* Lock IDT SMBus device */
0691         mutex_lock(&pdev->smb_mtx);
0692 
0693         /* Just read the byte to the buffer */
0694         ret = idt_eeprom_read_byte(pdev, memaddr, &buf[idx]);
0695 
0696         /* Unlock IDT SMBus device */
0697         mutex_unlock(&pdev->smb_mtx);
0698 
0699         /* Return error if read operation failed */
0700         if (ret != 0)
0701             return ret;
0702     }
0703 
0704     return 0;
0705 }
0706 
0707 /*===========================================================================
0708  *                          CSR IO-operations
0709  *===========================================================================
0710  */
0711 
0712 /*
0713  * idt_csr_write() - CSR write operation
0714  * @pdev:   Pointer to the driver data
0715  * @csraddr:    CSR address (with no two LS bits)
0716  * @data:   Data to be written to CSR
0717  */
0718 static int idt_csr_write(struct idt_89hpesx_dev *pdev, u16 csraddr,
0719              const u32 data)
0720 {
0721     struct device *dev = &pdev->client->dev;
0722     struct idt_csr_seq csrseq;
0723     struct idt_smb_seq smbseq;
0724     int ret;
0725 
0726     /* Initialize SMBus sequence fields */
0727     smbseq.ccode = pdev->iniccode | CCODE_CSR;
0728     smbseq.data = (u8 *)&csrseq;
0729 
0730     /* Lock IDT SMBus device */
0731     mutex_lock(&pdev->smb_mtx);
0732 
0733     /* Perform write operation */
0734     smbseq.bytecnt = CSR_WR_CNT;
0735     csrseq.cmd = pdev->inicsrcmd | CSR_OP_WRITE;
0736     csrseq.csraddr = cpu_to_le16(csraddr);
0737     csrseq.data = cpu_to_le32(data);
0738     ret = pdev->smb_write(pdev, &smbseq);
0739     if (ret != 0) {
0740         dev_err(dev, "Failed to write 0x%04x: 0x%04x to csr",
0741             CSR_REAL_ADDR(csraddr), data);
0742         goto err_mutex_unlock;
0743     }
0744 
0745     /* Send CSR address to read data from */
0746     smbseq.bytecnt = CSR_WRRD_CNT;
0747     csrseq.cmd = pdev->inicsrcmd | CSR_OP_READ;
0748     ret = pdev->smb_write(pdev, &smbseq);
0749     if (ret != 0) {
0750         dev_err(dev, "Failed to init csr address 0x%04x",
0751             CSR_REAL_ADDR(csraddr));
0752         goto err_mutex_unlock;
0753     }
0754 
0755     /* Perform read operation */
0756     smbseq.bytecnt = CSR_RD_CNT;
0757     ret = pdev->smb_read(pdev, &smbseq);
0758     if (ret != 0) {
0759         dev_err(dev, "Failed to read csr 0x%04x",
0760             CSR_REAL_ADDR(csraddr));
0761         goto err_mutex_unlock;
0762     }
0763 
0764     /* Check whether IDT successfully retrieved CSR data */
0765     if (csrseq.cmd & (CSR_RERR | CSR_WERR)) {
0766         dev_err(dev, "IDT failed to perform CSR r/w");
0767         ret = -EREMOTEIO;
0768         goto err_mutex_unlock;
0769     }
0770 
0771     /* Unlock IDT SMBus device */
0772 err_mutex_unlock:
0773     mutex_unlock(&pdev->smb_mtx);
0774 
0775     return ret;
0776 }
0777 
0778 /*
0779  * idt_csr_read() - CSR read operation
0780  * @pdev:   Pointer to the driver data
0781  * @csraddr:    CSR address (with no two LS bits)
0782  * @data:   Data to be written to CSR
0783  */
0784 static int idt_csr_read(struct idt_89hpesx_dev *pdev, u16 csraddr, u32 *data)
0785 {
0786     struct device *dev = &pdev->client->dev;
0787     struct idt_csr_seq csrseq;
0788     struct idt_smb_seq smbseq;
0789     int ret;
0790 
0791     /* Initialize SMBus sequence fields */
0792     smbseq.ccode = pdev->iniccode | CCODE_CSR;
0793     smbseq.data = (u8 *)&csrseq;
0794 
0795     /* Lock IDT SMBus device */
0796     mutex_lock(&pdev->smb_mtx);
0797 
0798     /* Send CSR register address before reading it */
0799     smbseq.bytecnt = CSR_WRRD_CNT;
0800     csrseq.cmd = pdev->inicsrcmd | CSR_OP_READ;
0801     csrseq.csraddr = cpu_to_le16(csraddr);
0802     ret = pdev->smb_write(pdev, &smbseq);
0803     if (ret != 0) {
0804         dev_err(dev, "Failed to init csr address 0x%04x",
0805             CSR_REAL_ADDR(csraddr));
0806         goto err_mutex_unlock;
0807     }
0808 
0809     /* Perform read operation */
0810     smbseq.bytecnt = CSR_RD_CNT;
0811     ret = pdev->smb_read(pdev, &smbseq);
0812     if (ret != 0) {
0813         dev_err(dev, "Failed to read csr 0x%04x",
0814             CSR_REAL_ADDR(csraddr));
0815         goto err_mutex_unlock;
0816     }
0817 
0818     /* Check whether IDT successfully retrieved CSR data */
0819     if (csrseq.cmd & (CSR_RERR | CSR_WERR)) {
0820         dev_err(dev, "IDT failed to perform CSR r/w");
0821         ret = -EREMOTEIO;
0822         goto err_mutex_unlock;
0823     }
0824 
0825     /* Save data retrieved from IDT */
0826     *data = le32_to_cpu(csrseq.data);
0827 
0828     /* Unlock IDT SMBus device */
0829 err_mutex_unlock:
0830     mutex_unlock(&pdev->smb_mtx);
0831 
0832     return ret;
0833 }
0834 
0835 /*===========================================================================
0836  *                          Sysfs/debugfs-nodes IO-operations
0837  *===========================================================================
0838  */
0839 
0840 /*
0841  * eeprom_write() - EEPROM sysfs-node write callback
0842  * @filep:  Pointer to the file system node
0843  * @kobj:   Pointer to the kernel object related to the sysfs-node
0844  * @attr:   Attributes of the file
0845  * @buf:    Buffer to write data to
0846  * @off:    Offset at which data should be written to
0847  * @count:  Number of bytes to write
0848  */
0849 static ssize_t eeprom_write(struct file *filp, struct kobject *kobj,
0850                 struct bin_attribute *attr,
0851                 char *buf, loff_t off, size_t count)
0852 {
0853     struct idt_89hpesx_dev *pdev;
0854     int ret;
0855 
0856     /* Retrieve driver data */
0857     pdev = dev_get_drvdata(kobj_to_dev(kobj));
0858 
0859     /* Perform EEPROM write operation */
0860     ret = idt_eeprom_write(pdev, (u16)off, (u16)count, (u8 *)buf);
0861     return (ret != 0 ? ret : count);
0862 }
0863 
0864 /*
0865  * eeprom_read() - EEPROM sysfs-node read callback
0866  * @filep:  Pointer to the file system node
0867  * @kobj:   Pointer to the kernel object related to the sysfs-node
0868  * @attr:   Attributes of the file
0869  * @buf:    Buffer to write data to
0870  * @off:    Offset at which data should be written to
0871  * @count:  Number of bytes to write
0872  */
0873 static ssize_t eeprom_read(struct file *filp, struct kobject *kobj,
0874                struct bin_attribute *attr,
0875                char *buf, loff_t off, size_t count)
0876 {
0877     struct idt_89hpesx_dev *pdev;
0878     int ret;
0879 
0880     /* Retrieve driver data */
0881     pdev = dev_get_drvdata(kobj_to_dev(kobj));
0882 
0883     /* Perform EEPROM read operation */
0884     ret = idt_eeprom_read(pdev, (u16)off, (u16)count, (u8 *)buf);
0885     return (ret != 0 ? ret : count);
0886 }
0887 
0888 /*
0889  * idt_dbgfs_csr_write() - CSR debugfs-node write callback
0890  * @filep:  Pointer to the file system file descriptor
0891  * @buf:    Buffer to read data from
0892  * @count:  Size of the buffer
0893  * @offp:   Offset within the file
0894  *
0895  * It accepts either "0x<reg addr>:0x<value>" for saving register address
0896  * and writing value to specified DWORD register or "0x<reg addr>" for
0897  * just saving register address in order to perform next read operation.
0898  *
0899  * WARNING No spaces are allowed. Incoming string must be strictly formated as:
0900  * "<reg addr>:<value>". Register address must be aligned within 4 bytes
0901  * (one DWORD).
0902  */
0903 static ssize_t idt_dbgfs_csr_write(struct file *filep, const char __user *ubuf,
0904                    size_t count, loff_t *offp)
0905 {
0906     struct idt_89hpesx_dev *pdev = filep->private_data;
0907     char *colon_ch, *csraddr_str, *csrval_str;
0908     int ret, csraddr_len;
0909     u32 csraddr, csrval;
0910     char *buf;
0911 
0912     if (*offp)
0913         return 0;
0914 
0915     /* Copy data from User-space */
0916     buf = kmalloc(count + 1, GFP_KERNEL);
0917     if (!buf)
0918         return -ENOMEM;
0919 
0920     if (copy_from_user(buf, ubuf, count)) {
0921         ret = -EFAULT;
0922         goto free_buf;
0923     }
0924     buf[count] = 0;
0925 
0926     /* Find position of colon in the buffer */
0927     colon_ch = strnchr(buf, count, ':');
0928 
0929     /*
0930      * If there is colon passed then new CSR value should be parsed as
0931      * well, so allocate buffer for CSR address substring.
0932      * If no colon is found, then string must have just one number with
0933      * no new CSR value
0934      */
0935     if (colon_ch != NULL) {
0936         csraddr_len = colon_ch - buf;
0937         csraddr_str =
0938             kmalloc(csraddr_len + 1, GFP_KERNEL);
0939         if (csraddr_str == NULL) {
0940             ret = -ENOMEM;
0941             goto free_buf;
0942         }
0943         /* Copy the register address to the substring buffer */
0944         strncpy(csraddr_str, buf, csraddr_len);
0945         csraddr_str[csraddr_len] = '\0';
0946         /* Register value must follow the colon */
0947         csrval_str = colon_ch + 1;
0948     } else /* if (str_colon == NULL) */ {
0949         csraddr_str = (char *)buf; /* Just to shut warning up */
0950         csraddr_len = strnlen(csraddr_str, count);
0951         csrval_str = NULL;
0952     }
0953 
0954     /* Convert CSR address to u32 value */
0955     ret = kstrtou32(csraddr_str, 0, &csraddr);
0956     if (ret != 0)
0957         goto free_csraddr_str;
0958 
0959     /* Check whether passed register address is valid */
0960     if (csraddr > CSR_MAX || !IS_ALIGNED(csraddr, SZ_4)) {
0961         ret = -EINVAL;
0962         goto free_csraddr_str;
0963     }
0964 
0965     /* Shift register address to the right so to have u16 address */
0966     pdev->csr = (csraddr >> 2);
0967 
0968     /* Parse new CSR value and send it to IDT, if colon has been found */
0969     if (colon_ch != NULL) {
0970         ret = kstrtou32(csrval_str, 0, &csrval);
0971         if (ret != 0)
0972             goto free_csraddr_str;
0973 
0974         ret = idt_csr_write(pdev, pdev->csr, csrval);
0975         if (ret != 0)
0976             goto free_csraddr_str;
0977     }
0978 
0979     /* Free memory only if colon has been found */
0980 free_csraddr_str:
0981     if (colon_ch != NULL)
0982         kfree(csraddr_str);
0983 
0984     /* Free buffer allocated for data retrieved from User-space */
0985 free_buf:
0986     kfree(buf);
0987 
0988     return (ret != 0 ? ret : count);
0989 }
0990 
0991 /*
0992  * idt_dbgfs_csr_read() - CSR debugfs-node read callback
0993  * @filep:  Pointer to the file system file descriptor
0994  * @buf:    Buffer to write data to
0995  * @count:  Size of the buffer
0996  * @offp:   Offset within the file
0997  *
0998  * It just prints the pair "0x<reg addr>:0x<value>" to passed buffer.
0999  */
1000 #define CSRBUF_SIZE ((size_t)32)
1001 static ssize_t idt_dbgfs_csr_read(struct file *filep, char __user *ubuf,
1002                   size_t count, loff_t *offp)
1003 {
1004     struct idt_89hpesx_dev *pdev = filep->private_data;
1005     u32 csraddr, csrval;
1006     char buf[CSRBUF_SIZE];
1007     int ret, size;
1008 
1009     /* Perform CSR read operation */
1010     ret = idt_csr_read(pdev, pdev->csr, &csrval);
1011     if (ret != 0)
1012         return ret;
1013 
1014     /* Shift register address to the left so to have real address */
1015     csraddr = ((u32)pdev->csr << 2);
1016 
1017     /* Print the "0x<reg addr>:0x<value>" to buffer */
1018     size = snprintf(buf, CSRBUF_SIZE, "0x%05x:0x%08x\n",
1019         (unsigned int)csraddr, (unsigned int)csrval);
1020 
1021     /* Copy data to User-space */
1022     return simple_read_from_buffer(ubuf, count, offp, buf, size);
1023 }
1024 
1025 /*
1026  * eeprom_attribute - EEPROM sysfs-node attributes
1027  *
1028  * NOTE Size will be changed in compliance with OF node. EEPROM attribute will
1029  * be read-only as well if the corresponding flag is specified in OF node.
1030  */
1031 static BIN_ATTR_RW(eeprom, EEPROM_DEF_SIZE);
1032 
1033 /*
1034  * csr_dbgfs_ops - CSR debugfs-node read/write operations
1035  */
1036 static const struct file_operations csr_dbgfs_ops = {
1037     .owner = THIS_MODULE,
1038     .open = simple_open,
1039     .write = idt_dbgfs_csr_write,
1040     .read = idt_dbgfs_csr_read
1041 };
1042 
1043 /*===========================================================================
1044  *                       Driver init/deinit methods
1045  *===========================================================================
1046  */
1047 
1048 /*
1049  * idt_set_defval() - disable EEPROM access by default
1050  * @pdev:   Pointer to the driver data
1051  */
1052 static void idt_set_defval(struct idt_89hpesx_dev *pdev)
1053 {
1054     /* If OF info is missing then use next values */
1055     pdev->eesize = 0;
1056     pdev->eero = true;
1057     pdev->inieecmd = 0;
1058     pdev->eeaddr = 0;
1059 }
1060 
1061 static const struct i2c_device_id ee_ids[];
1062 
1063 /*
1064  * idt_ee_match_id() - check whether the node belongs to compatible EEPROMs
1065  */
1066 static const struct i2c_device_id *idt_ee_match_id(struct fwnode_handle *fwnode)
1067 {
1068     const struct i2c_device_id *id = ee_ids;
1069     const char *compatible, *p;
1070     char devname[I2C_NAME_SIZE];
1071     int ret;
1072 
1073     ret = fwnode_property_read_string(fwnode, "compatible", &compatible);
1074     if (ret)
1075         return NULL;
1076 
1077     p = strchr(compatible, ',');
1078     strlcpy(devname, p ? p + 1 : compatible, sizeof(devname));
1079     /* Search through the device name */
1080     while (id->name[0]) {
1081         if (strcmp(devname, id->name) == 0)
1082             return id;
1083         id++;
1084     }
1085     return NULL;
1086 }
1087 
1088 /*
1089  * idt_get_fw_data() - get IDT i2c-device parameters from device tree
1090  * @pdev:   Pointer to the driver data
1091  */
1092 static void idt_get_fw_data(struct idt_89hpesx_dev *pdev)
1093 {
1094     struct device *dev = &pdev->client->dev;
1095     struct fwnode_handle *fwnode;
1096     const struct i2c_device_id *ee_id = NULL;
1097     u32 eeprom_addr;
1098     int ret;
1099 
1100     device_for_each_child_node(dev, fwnode) {
1101         ee_id = idt_ee_match_id(fwnode);
1102         if (ee_id)
1103             break;
1104 
1105         dev_warn(dev, "Skip unsupported EEPROM device %pfw\n", fwnode);
1106     }
1107 
1108     /* If there is no fwnode EEPROM device, then set zero size */
1109     if (!ee_id) {
1110         dev_warn(dev, "No fwnode, EEPROM access disabled");
1111         idt_set_defval(pdev);
1112         return;
1113     }
1114 
1115     /* Retrieve EEPROM size */
1116     pdev->eesize = (u32)ee_id->driver_data;
1117 
1118     /* Get custom EEPROM address from 'reg' attribute */
1119     ret = fwnode_property_read_u32(fwnode, "reg", &eeprom_addr);
1120     if (ret || (eeprom_addr == 0)) {
1121         dev_warn(dev, "No EEPROM reg found, use default address 0x%x",
1122              EEPROM_DEF_ADDR);
1123         pdev->inieecmd = 0;
1124         pdev->eeaddr = EEPROM_DEF_ADDR << 1;
1125     } else {
1126         pdev->inieecmd = EEPROM_USA;
1127         pdev->eeaddr = eeprom_addr << 1;
1128     }
1129 
1130     /* Check EEPROM 'read-only' flag */
1131     if (fwnode_property_read_bool(fwnode, "read-only"))
1132         pdev->eero = true;
1133     else /* if (!fwnode_property_read_bool(node, "read-only")) */
1134         pdev->eero = false;
1135 
1136     fwnode_handle_put(fwnode);
1137     dev_info(dev, "EEPROM of %d bytes found by 0x%x",
1138         pdev->eesize, pdev->eeaddr);
1139 }
1140 
1141 /*
1142  * idt_create_pdev() - create and init data structure of the driver
1143  * @client: i2c client of IDT PCIe-switch device
1144  */
1145 static struct idt_89hpesx_dev *idt_create_pdev(struct i2c_client *client)
1146 {
1147     struct idt_89hpesx_dev *pdev;
1148 
1149     /* Allocate memory for driver data */
1150     pdev = devm_kmalloc(&client->dev, sizeof(struct idt_89hpesx_dev),
1151         GFP_KERNEL);
1152     if (pdev == NULL)
1153         return ERR_PTR(-ENOMEM);
1154 
1155     /* Initialize basic fields of the data */
1156     pdev->client = client;
1157     i2c_set_clientdata(client, pdev);
1158 
1159     /* Read firmware nodes information */
1160     idt_get_fw_data(pdev);
1161 
1162     /* Initialize basic CSR CMD field - use full DWORD-sized r/w ops */
1163     pdev->inicsrcmd = CSR_DWE;
1164     pdev->csr = CSR_DEF;
1165 
1166     /* Enable Packet Error Checking if it's supported by adapter */
1167     if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_PEC)) {
1168         pdev->iniccode = CCODE_PEC;
1169         client->flags |= I2C_CLIENT_PEC;
1170     } else /* PEC is unsupported */ {
1171         pdev->iniccode = 0;
1172     }
1173 
1174     return pdev;
1175 }
1176 
1177 /*
1178  * idt_free_pdev() - free data structure of the driver
1179  * @pdev:   Pointer to the driver data
1180  */
1181 static void idt_free_pdev(struct idt_89hpesx_dev *pdev)
1182 {
1183     /* Clear driver data from device private field */
1184     i2c_set_clientdata(pdev->client, NULL);
1185 }
1186 
1187 /*
1188  * idt_set_smbus_ops() - set supported SMBus operations
1189  * @pdev:   Pointer to the driver data
1190  * Return status of smbus check operations
1191  */
1192 static int idt_set_smbus_ops(struct idt_89hpesx_dev *pdev)
1193 {
1194     struct i2c_adapter *adapter = pdev->client->adapter;
1195     struct device *dev = &pdev->client->dev;
1196 
1197     /* Check i2c adapter read functionality */
1198     if (i2c_check_functionality(adapter,
1199                     I2C_FUNC_SMBUS_READ_BLOCK_DATA)) {
1200         pdev->smb_read = idt_smb_read_block;
1201         dev_dbg(dev, "SMBus block-read op chosen");
1202     } else if (i2c_check_functionality(adapter,
1203                        I2C_FUNC_SMBUS_READ_I2C_BLOCK)) {
1204         pdev->smb_read = idt_smb_read_i2c_block;
1205         dev_dbg(dev, "SMBus i2c-block-read op chosen");
1206     } else if (i2c_check_functionality(adapter,
1207                        I2C_FUNC_SMBUS_READ_WORD_DATA) &&
1208            i2c_check_functionality(adapter,
1209                        I2C_FUNC_SMBUS_READ_BYTE_DATA)) {
1210         pdev->smb_read = idt_smb_read_word;
1211         dev_warn(dev, "Use slow word/byte SMBus read ops");
1212     } else if (i2c_check_functionality(adapter,
1213                        I2C_FUNC_SMBUS_READ_BYTE_DATA)) {
1214         pdev->smb_read = idt_smb_read_byte;
1215         dev_warn(dev, "Use slow byte SMBus read op");
1216     } else /* no supported smbus read operations */ {
1217         dev_err(dev, "No supported SMBus read op");
1218         return -EPFNOSUPPORT;
1219     }
1220 
1221     /* Check i2c adapter write functionality */
1222     if (i2c_check_functionality(adapter,
1223                     I2C_FUNC_SMBUS_WRITE_BLOCK_DATA)) {
1224         pdev->smb_write = idt_smb_write_block;
1225         dev_dbg(dev, "SMBus block-write op chosen");
1226     } else if (i2c_check_functionality(adapter,
1227                        I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)) {
1228         pdev->smb_write = idt_smb_write_i2c_block;
1229         dev_dbg(dev, "SMBus i2c-block-write op chosen");
1230     } else if (i2c_check_functionality(adapter,
1231                        I2C_FUNC_SMBUS_WRITE_WORD_DATA) &&
1232            i2c_check_functionality(adapter,
1233                        I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) {
1234         pdev->smb_write = idt_smb_write_word;
1235         dev_warn(dev, "Use slow word/byte SMBus write op");
1236     } else if (i2c_check_functionality(adapter,
1237                        I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) {
1238         pdev->smb_write = idt_smb_write_byte;
1239         dev_warn(dev, "Use slow byte SMBus write op");
1240     } else /* no supported smbus write operations */ {
1241         dev_err(dev, "No supported SMBus write op");
1242         return -EPFNOSUPPORT;
1243     }
1244 
1245     /* Initialize IDT SMBus slave interface mutex */
1246     mutex_init(&pdev->smb_mtx);
1247 
1248     return 0;
1249 }
1250 
1251 /*
1252  * idt_check_dev() - check whether it's really IDT 89HPESx device
1253  * @pdev:   Pointer to the driver data
1254  * Return status of i2c adapter check operation
1255  */
1256 static int idt_check_dev(struct idt_89hpesx_dev *pdev)
1257 {
1258     struct device *dev = &pdev->client->dev;
1259     u32 viddid;
1260     int ret;
1261 
1262     /* Read VID and DID directly from IDT memory space */
1263     ret = idt_csr_read(pdev, IDT_VIDDID_CSR, &viddid);
1264     if (ret != 0) {
1265         dev_err(dev, "Failed to read VID/DID");
1266         return ret;
1267     }
1268 
1269     /* Check whether it's IDT device */
1270     if ((viddid & IDT_VID_MASK) != PCI_VENDOR_ID_IDT) {
1271         dev_err(dev, "Got unsupported VID/DID: 0x%08x", viddid);
1272         return -ENODEV;
1273     }
1274 
1275     dev_info(dev, "Found IDT 89HPES device VID:0x%04x, DID:0x%04x",
1276         (viddid & IDT_VID_MASK), (viddid >> 16));
1277 
1278     return 0;
1279 }
1280 
1281 /*
1282  * idt_create_sysfs_files() - create sysfs attribute files
1283  * @pdev:   Pointer to the driver data
1284  * Return status of operation
1285  */
1286 static int idt_create_sysfs_files(struct idt_89hpesx_dev *pdev)
1287 {
1288     struct device *dev = &pdev->client->dev;
1289     int ret;
1290 
1291     /* Don't do anything if EEPROM isn't accessible */
1292     if (pdev->eesize == 0) {
1293         dev_dbg(dev, "Skip creating sysfs-files");
1294         return 0;
1295     }
1296 
1297     /* Allocate memory for attribute file */
1298     pdev->ee_file = devm_kmalloc(dev, sizeof(*pdev->ee_file), GFP_KERNEL);
1299     if (!pdev->ee_file)
1300         return -ENOMEM;
1301 
1302     /* Copy the declared EEPROM attr structure to change some of fields */
1303     memcpy(pdev->ee_file, &bin_attr_eeprom, sizeof(*pdev->ee_file));
1304 
1305     /* In case of read-only EEPROM get rid of write ability */
1306     if (pdev->eero) {
1307         pdev->ee_file->attr.mode &= ~0200;
1308         pdev->ee_file->write = NULL;
1309     }
1310     /* Create EEPROM sysfs file */
1311     pdev->ee_file->size = pdev->eesize;
1312     ret = sysfs_create_bin_file(&dev->kobj, pdev->ee_file);
1313     if (ret != 0) {
1314         dev_err(dev, "Failed to create EEPROM sysfs-node");
1315         return ret;
1316     }
1317 
1318     return 0;
1319 }
1320 
1321 /*
1322  * idt_remove_sysfs_files() - remove sysfs attribute files
1323  * @pdev:   Pointer to the driver data
1324  */
1325 static void idt_remove_sysfs_files(struct idt_89hpesx_dev *pdev)
1326 {
1327     struct device *dev = &pdev->client->dev;
1328 
1329     /* Don't do anything if EEPROM wasn't accessible */
1330     if (pdev->eesize == 0)
1331         return;
1332 
1333     /* Remove EEPROM sysfs file */
1334     sysfs_remove_bin_file(&dev->kobj, pdev->ee_file);
1335 }
1336 
1337 /*
1338  * idt_create_dbgfs_files() - create debugfs files
1339  * @pdev:   Pointer to the driver data
1340  */
1341 #define CSRNAME_LEN ((size_t)32)
1342 static void idt_create_dbgfs_files(struct idt_89hpesx_dev *pdev)
1343 {
1344     struct i2c_client *cli = pdev->client;
1345     char fname[CSRNAME_LEN];
1346 
1347     /* Create Debugfs directory for CSR file */
1348     snprintf(fname, CSRNAME_LEN, "%d-%04hx", cli->adapter->nr, cli->addr);
1349     pdev->csr_dir = debugfs_create_dir(fname, csr_dbgdir);
1350 
1351     /* Create Debugfs file for CSR read/write operations */
1352     debugfs_create_file(cli->name, 0600, pdev->csr_dir, pdev,
1353                 &csr_dbgfs_ops);
1354 }
1355 
1356 /*
1357  * idt_remove_dbgfs_files() - remove debugfs files
1358  * @pdev:   Pointer to the driver data
1359  */
1360 static void idt_remove_dbgfs_files(struct idt_89hpesx_dev *pdev)
1361 {
1362     /* Remove CSR directory and it sysfs-node */
1363     debugfs_remove_recursive(pdev->csr_dir);
1364 }
1365 
1366 /*
1367  * idt_probe() - IDT 89HPESx driver probe() callback method
1368  */
1369 static int idt_probe(struct i2c_client *client, const struct i2c_device_id *id)
1370 {
1371     struct idt_89hpesx_dev *pdev;
1372     int ret;
1373 
1374     /* Create driver data */
1375     pdev = idt_create_pdev(client);
1376     if (IS_ERR(pdev))
1377         return PTR_ERR(pdev);
1378 
1379     /* Set SMBus operations */
1380     ret = idt_set_smbus_ops(pdev);
1381     if (ret != 0)
1382         goto err_free_pdev;
1383 
1384     /* Check whether it is truly IDT 89HPESx device */
1385     ret = idt_check_dev(pdev);
1386     if (ret != 0)
1387         goto err_free_pdev;
1388 
1389     /* Create sysfs files */
1390     ret = idt_create_sysfs_files(pdev);
1391     if (ret != 0)
1392         goto err_free_pdev;
1393 
1394     /* Create debugfs files */
1395     idt_create_dbgfs_files(pdev);
1396 
1397     return 0;
1398 
1399 err_free_pdev:
1400     idt_free_pdev(pdev);
1401 
1402     return ret;
1403 }
1404 
1405 /*
1406  * idt_remove() - IDT 89HPESx driver remove() callback method
1407  */
1408 static int idt_remove(struct i2c_client *client)
1409 {
1410     struct idt_89hpesx_dev *pdev = i2c_get_clientdata(client);
1411 
1412     /* Remove debugfs files first */
1413     idt_remove_dbgfs_files(pdev);
1414 
1415     /* Remove sysfs files */
1416     idt_remove_sysfs_files(pdev);
1417 
1418     /* Discard driver data structure */
1419     idt_free_pdev(pdev);
1420 
1421     return 0;
1422 }
1423 
1424 /*
1425  * ee_ids - array of supported EEPROMs
1426  */
1427 static const struct i2c_device_id ee_ids[] = {
1428     { "24c32",  4096},
1429     { "24c64",  8192},
1430     { "24c128", 16384},
1431     { "24c256", 32768},
1432     { "24c512", 65536},
1433     {}
1434 };
1435 MODULE_DEVICE_TABLE(i2c, ee_ids);
1436 
1437 /*
1438  * idt_ids - supported IDT 89HPESx devices
1439  */
1440 static const struct i2c_device_id idt_ids[] = {
1441     { "89hpes8nt2", 0 },
1442     { "89hpes12nt3", 0 },
1443 
1444     { "89hpes24nt6ag2", 0 },
1445     { "89hpes32nt8ag2", 0 },
1446     { "89hpes32nt8bg2", 0 },
1447     { "89hpes12nt12g2", 0 },
1448     { "89hpes16nt16g2", 0 },
1449     { "89hpes24nt24g2", 0 },
1450     { "89hpes32nt24ag2", 0 },
1451     { "89hpes32nt24bg2", 0 },
1452 
1453     { "89hpes12n3", 0 },
1454     { "89hpes12n3a", 0 },
1455     { "89hpes24n3", 0 },
1456     { "89hpes24n3a", 0 },
1457 
1458     { "89hpes32h8", 0 },
1459     { "89hpes32h8g2", 0 },
1460     { "89hpes48h12", 0 },
1461     { "89hpes48h12g2", 0 },
1462     { "89hpes48h12ag2", 0 },
1463     { "89hpes16h16", 0 },
1464     { "89hpes22h16", 0 },
1465     { "89hpes22h16g2", 0 },
1466     { "89hpes34h16", 0 },
1467     { "89hpes34h16g2", 0 },
1468     { "89hpes64h16", 0 },
1469     { "89hpes64h16g2", 0 },
1470     { "89hpes64h16ag2", 0 },
1471 
1472     /* { "89hpes3t3", 0 }, // No SMBus-slave iface */
1473     { "89hpes12t3g2", 0 },
1474     { "89hpes24t3g2", 0 },
1475     /* { "89hpes4t4", 0 }, // No SMBus-slave iface */
1476     { "89hpes16t4", 0 },
1477     { "89hpes4t4g2", 0 },
1478     { "89hpes10t4g2", 0 },
1479     { "89hpes16t4g2", 0 },
1480     { "89hpes16t4ag2", 0 },
1481     { "89hpes5t5", 0 },
1482     { "89hpes6t5", 0 },
1483     { "89hpes8t5", 0 },
1484     { "89hpes8t5a", 0 },
1485     { "89hpes24t6", 0 },
1486     { "89hpes6t6g2", 0 },
1487     { "89hpes24t6g2", 0 },
1488     { "89hpes16t7", 0 },
1489     { "89hpes32t8", 0 },
1490     { "89hpes32t8g2", 0 },
1491     { "89hpes48t12", 0 },
1492     { "89hpes48t12g2", 0 },
1493     { /* END OF LIST */ }
1494 };
1495 MODULE_DEVICE_TABLE(i2c, idt_ids);
1496 
1497 static const struct of_device_id idt_of_match[] = {
1498     { .compatible = "idt,89hpes8nt2", },
1499     { .compatible = "idt,89hpes12nt3", },
1500 
1501     { .compatible = "idt,89hpes24nt6ag2", },
1502     { .compatible = "idt,89hpes32nt8ag2", },
1503     { .compatible = "idt,89hpes32nt8bg2", },
1504     { .compatible = "idt,89hpes12nt12g2", },
1505     { .compatible = "idt,89hpes16nt16g2", },
1506     { .compatible = "idt,89hpes24nt24g2", },
1507     { .compatible = "idt,89hpes32nt24ag2", },
1508     { .compatible = "idt,89hpes32nt24bg2", },
1509 
1510     { .compatible = "idt,89hpes12n3", },
1511     { .compatible = "idt,89hpes12n3a", },
1512     { .compatible = "idt,89hpes24n3", },
1513     { .compatible = "idt,89hpes24n3a", },
1514 
1515     { .compatible = "idt,89hpes32h8", },
1516     { .compatible = "idt,89hpes32h8g2", },
1517     { .compatible = "idt,89hpes48h12", },
1518     { .compatible = "idt,89hpes48h12g2", },
1519     { .compatible = "idt,89hpes48h12ag2", },
1520     { .compatible = "idt,89hpes16h16", },
1521     { .compatible = "idt,89hpes22h16", },
1522     { .compatible = "idt,89hpes22h16g2", },
1523     { .compatible = "idt,89hpes34h16", },
1524     { .compatible = "idt,89hpes34h16g2", },
1525     { .compatible = "idt,89hpes64h16", },
1526     { .compatible = "idt,89hpes64h16g2", },
1527     { .compatible = "idt,89hpes64h16ag2", },
1528 
1529     { .compatible = "idt,89hpes12t3g2", },
1530     { .compatible = "idt,89hpes24t3g2", },
1531 
1532     { .compatible = "idt,89hpes16t4", },
1533     { .compatible = "idt,89hpes4t4g2", },
1534     { .compatible = "idt,89hpes10t4g2", },
1535     { .compatible = "idt,89hpes16t4g2", },
1536     { .compatible = "idt,89hpes16t4ag2", },
1537     { .compatible = "idt,89hpes5t5", },
1538     { .compatible = "idt,89hpes6t5", },
1539     { .compatible = "idt,89hpes8t5", },
1540     { .compatible = "idt,89hpes8t5a", },
1541     { .compatible = "idt,89hpes24t6", },
1542     { .compatible = "idt,89hpes6t6g2", },
1543     { .compatible = "idt,89hpes24t6g2", },
1544     { .compatible = "idt,89hpes16t7", },
1545     { .compatible = "idt,89hpes32t8", },
1546     { .compatible = "idt,89hpes32t8g2", },
1547     { .compatible = "idt,89hpes48t12", },
1548     { .compatible = "idt,89hpes48t12g2", },
1549     { },
1550 };
1551 MODULE_DEVICE_TABLE(of, idt_of_match);
1552 
1553 /*
1554  * idt_driver - IDT 89HPESx driver structure
1555  */
1556 static struct i2c_driver idt_driver = {
1557     .driver = {
1558         .name = IDT_NAME,
1559         .of_match_table = idt_of_match,
1560     },
1561     .probe = idt_probe,
1562     .remove = idt_remove,
1563     .id_table = idt_ids,
1564 };
1565 
1566 /*
1567  * idt_init() - IDT 89HPESx driver init() callback method
1568  */
1569 static int __init idt_init(void)
1570 {
1571     /* Create Debugfs directory first */
1572     if (debugfs_initialized())
1573         csr_dbgdir = debugfs_create_dir("idt_csr", NULL);
1574 
1575     /* Add new i2c-device driver */
1576     return i2c_add_driver(&idt_driver);
1577 }
1578 module_init(idt_init);
1579 
1580 /*
1581  * idt_exit() - IDT 89HPESx driver exit() callback method
1582  */
1583 static void __exit idt_exit(void)
1584 {
1585     /* Discard debugfs directory and all files if any */
1586     debugfs_remove_recursive(csr_dbgdir);
1587 
1588     /* Unregister i2c-device driver */
1589     i2c_del_driver(&idt_driver);
1590 }
1591 module_exit(idt_exit);
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