misc/eeprom/at25.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Driver for most of the SPI EEPROMs, such as Atmel AT25 models
0004  * and Cypress FRAMs FM25 models.
0005  *
0006  * Copyright (C) 2006 David Brownell
0007  */
0008
0009 #include <linux/bits.h>
0010 #include <linux/delay.h>
0011 #include <linux/device.h>
0012 #include <linux/kernel.h>
0013 #include <linux/module.h>
0014 #include <linux/property.h>
0015 #include <linux/sched.h>
0016 #include <linux/slab.h>
0017
0018 #include <linux/spi/eeprom.h>
0019 #include <linux/spi/spi.h>
0020
0021 #include <linux/nvmem-provider.h>
0022
0023 /*
0024  * NOTE: this is an *EEPROM* driver. The vagaries of product naming
0025  * mean that some AT25 products are EEPROMs, and others are FLASH.
0026  * Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver,
0027  * not this one!
0028  *
0029  * EEPROMs that can be used with this driver include, for example:
0030  *   AT25M02, AT25128B
0031  */
0032
0033 #define FM25_SN_LEN 8       /* serial number length */
0034 #define EE_MAXADDRLEN   3       /* 24 bit addresses, up to 2 MBytes */
0035
0036 struct at25_data {
0037     struct spi_eeprom   chip;
0038     struct spi_device   *spi;
0039     struct mutex        lock;
0040     unsigned        addrlen;
0041     struct nvmem_config nvmem_config;
0042     struct nvmem_device *nvmem;
0043     u8 sernum[FM25_SN_LEN];
0044     u8 command[EE_MAXADDRLEN + 1];
0045 };
0046
0047 #define AT25_WREN   0x06        /* latch the write enable */
0048 #define AT25_WRDI   0x04        /* reset the write enable */
0049 #define AT25_RDSR   0x05        /* read status register */
0050 #define AT25_WRSR   0x01        /* write status register */
0051 #define AT25_READ   0x03        /* read byte(s) */
0052 #define AT25_WRITE  0x02        /* write byte(s)/sector */
0053 #define FM25_SLEEP  0xb9        /* enter sleep mode */
0054 #define FM25_RDID   0x9f        /* read device ID */
0055 #define FM25_RDSN   0xc3        /* read S/N */
0056
0057 #define AT25_SR_nRDY    0x01        /* nRDY = write-in-progress */
0058 #define AT25_SR_WEN 0x02        /* write enable (latched) */
0059 #define AT25_SR_BP0 0x04        /* BP for software writeprotect */
0060 #define AT25_SR_BP1 0x08
0061 #define AT25_SR_WPEN    0x80        /* writeprotect enable */
0062
0063 #define AT25_INSTR_BIT3 0x08        /* additional address bit in instr */
0064
0065 #define FM25_ID_LEN 9       /* ID length */
0066
0067 /*
0068  * Specs often allow 5ms for a page write, sometimes 20ms;
0069  * it's important to recover from write timeouts.
0070  */
0071 #define EE_TIMEOUT  25
0072
0073 /*-------------------------------------------------------------------------*/
0074
0075 #define io_limit    PAGE_SIZE   /* bytes */
0076
0077 static int at25_ee_read(void *priv, unsigned int offset,
0078             void *val, size_t count)
0079 {
0080     struct at25_data *at25 = priv;
0081     char *buf = val;
0082     size_t max_chunk = spi_max_transfer_size(at25->spi);
0083     unsigned int msg_offset = offset;
0084     size_t bytes_left = count;
0085     size_t segment;
0086     u8          *cp;
0087     ssize_t         status;
0088     struct spi_transfer t[2];
0089     struct spi_message  m;
0090     u8          instr;
0091
0092     if (unlikely(offset >= at25->chip.byte_len))
0093         return -EINVAL;
0094     if ((offset + count) > at25->chip.byte_len)
0095         count = at25->chip.byte_len - offset;
0096     if (unlikely(!count))
0097         return -EINVAL;
0098
0099     do {
0100         segment = min(bytes_left, max_chunk);
0101         cp = at25->command;
0102
0103         instr = AT25_READ;
0104         if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
0105             if (msg_offset >= BIT(at25->addrlen * 8))
0106                 instr |= AT25_INSTR_BIT3;
0107
0108         mutex_lock(&at25->lock);
0109
0110         *cp++ = instr;
0111
0112         /* 8/16/24-bit address is written MSB first */
0113         switch (at25->addrlen) {
0114         default:    /* case 3 */
0115             *cp++ = msg_offset >> 16;
0116             fallthrough;
0117         case 2:
0118             *cp++ = msg_offset >> 8;
0119             fallthrough;
0120         case 1:
0121         case 0: /* can't happen: for better code generation */
0122             *cp++ = msg_offset >> 0;
0123         }
0124
0125         spi_message_init(&m);
0126         memset(t, 0, sizeof(t));
0127
0128         t[0].tx_buf = at25->command;
0129         t[0].len = at25->addrlen + 1;
0130         spi_message_add_tail(&t[0], &m);
0131
0132         t[1].rx_buf = buf;
0133         t[1].len = segment;
0134         spi_message_add_tail(&t[1], &m);
0135
0136         status = spi_sync(at25->spi, &m);
0137
0138         mutex_unlock(&at25->lock);
0139
0140         if (status)
0141             return status;
0142
0143         msg_offset += segment;
0144         buf += segment;
0145         bytes_left -= segment;
0146     } while (bytes_left > 0);
0147
0148     dev_dbg(&at25->spi->dev, "read %zu bytes at %d\n",
0149         count, offset);
0150     return 0;
0151 }
0152
0153 /* Read extra registers as ID or serial number */
0154 static int fm25_aux_read(struct at25_data *at25, u8 *buf, uint8_t command,
0155              int len)
0156 {
0157     int status;
0158     struct spi_transfer t[2];
0159     struct spi_message m;
0160
0161     spi_message_init(&m);
0162     memset(t, 0, sizeof(t));
0163
0164     t[0].tx_buf = at25->command;
0165     t[0].len = 1;
0166     spi_message_add_tail(&t[0], &m);
0167
0168     t[1].rx_buf = buf;
0169     t[1].len = len;
0170     spi_message_add_tail(&t[1], &m);
0171
0172     mutex_lock(&at25->lock);
0173
0174     at25->command[0] = command;
0175
0176     status = spi_sync(at25->spi, &m);
0177     dev_dbg(&at25->spi->dev, "read %d aux bytes --> %d\n", len, status);
0178
0179     mutex_unlock(&at25->lock);
0180     return status;
0181 }
0182
0183 static ssize_t sernum_show(struct device *dev, struct device_attribute *attr, char *buf)
0184 {
0185     struct at25_data *at25;
0186
0187     at25 = dev_get_drvdata(dev);
0188     return sysfs_emit(buf, "%*ph\n", (int)sizeof(at25->sernum), at25->sernum);
0189 }
0190 static DEVICE_ATTR_RO(sernum);
0191
0192 static struct attribute *sernum_attrs[] = {
0193     &dev_attr_sernum.attr,
0194     NULL,
0195 };
0196 ATTRIBUTE_GROUPS(sernum);
0197
0198 static int at25_ee_write(void *priv, unsigned int off, void *val, size_t count)
0199 {
0200     struct at25_data *at25 = priv;
0201     size_t maxsz = spi_max_transfer_size(at25->spi);
0202     const char *buf = val;
0203     int         status = 0;
0204     unsigned        buf_size;
0205     u8          *bounce;
0206
0207     if (unlikely(off >= at25->chip.byte_len))
0208         return -EFBIG;
0209     if ((off + count) > at25->chip.byte_len)
0210         count = at25->chip.byte_len - off;
0211     if (unlikely(!count))
0212         return -EINVAL;
0213
0214     /* Temp buffer starts with command and address */
0215     buf_size = at25->chip.page_size;
0216     if (buf_size > io_limit)
0217         buf_size = io_limit;
0218     bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL);
0219     if (!bounce)
0220         return -ENOMEM;
0221
0222     /*
0223      * For write, rollover is within the page ... so we write at
0224      * most one page, then manually roll over to the next page.
0225      */
0226     mutex_lock(&at25->lock);
0227     do {
0228         unsigned long   timeout, retries;
0229         unsigned    segment;
0230         unsigned    offset = off;
0231         u8      *cp = bounce;
0232         int     sr;
0233         u8      instr;
0234
0235         *cp = AT25_WREN;
0236         status = spi_write(at25->spi, cp, 1);
0237         if (status < 0) {
0238             dev_dbg(&at25->spi->dev, "WREN --> %d\n", status);
0239             break;
0240         }
0241
0242         instr = AT25_WRITE;
0243         if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
0244             if (offset >= BIT(at25->addrlen * 8))
0245                 instr |= AT25_INSTR_BIT3;
0246         *cp++ = instr;
0247
0248         /* 8/16/24-bit address is written MSB first */
0249         switch (at25->addrlen) {
0250         default:    /* case 3 */
0251             *cp++ = offset >> 16;
0252             fallthrough;
0253         case 2:
0254             *cp++ = offset >> 8;
0255             fallthrough;
0256         case 1:
0257         case 0: /* can't happen: for better code generation */
0258             *cp++ = offset >> 0;
0259         }
0260
0261         /* Write as much of a page as we can */
0262         segment = buf_size - (offset % buf_size);
0263         if (segment > count)
0264             segment = count;
0265         if (segment > maxsz)
0266             segment = maxsz;
0267         memcpy(cp, buf, segment);
0268         status = spi_write(at25->spi, bounce,
0269                 segment + at25->addrlen + 1);
0270         dev_dbg(&at25->spi->dev, "write %u bytes at %u --> %d\n",
0271             segment, offset, status);
0272         if (status < 0)
0273             break;
0274
0275         /*
0276          * REVISIT this should detect (or prevent) failed writes
0277          * to read-only sections of the EEPROM...
0278          */
0279
0280         /* Wait for non-busy status */
0281         timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT);
0282         retries = 0;
0283         do {
0284
0285             sr = spi_w8r8(at25->spi, AT25_RDSR);
0286             if (sr < 0 || (sr & AT25_SR_nRDY)) {
0287                 dev_dbg(&at25->spi->dev,
0288                     "rdsr --> %d (%02x)\n", sr, sr);
0289                 /* at HZ=100, this is sloooow */
0290                 msleep(1);
0291                 continue;
0292             }
0293             if (!(sr & AT25_SR_nRDY))
0294                 break;
0295         } while (retries++ < 3 || time_before_eq(jiffies, timeout));
0296
0297         if ((sr < 0) || (sr & AT25_SR_nRDY)) {
0298             dev_err(&at25->spi->dev,
0299                 "write %u bytes offset %u, timeout after %u msecs\n",
0300                 segment, offset,
0301                 jiffies_to_msecs(jiffies -
0302                     (timeout - EE_TIMEOUT)));
0303             status = -ETIMEDOUT;
0304             break;
0305         }
0306
0307         off += segment;
0308         buf += segment;
0309         count -= segment;
0310
0311     } while (count > 0);
0312
0313     mutex_unlock(&at25->lock);
0314
0315     kfree(bounce);
0316     return status;
0317 }
0318
0319 /*-------------------------------------------------------------------------*/
0320
0321 static int at25_fw_to_chip(struct device *dev, struct spi_eeprom *chip)
0322 {
0323     u32 val;
0324     int err;
0325
0326     strscpy(chip->name, "at25", sizeof(chip->name));
0327
0328     err = device_property_read_u32(dev, "size", &val);
0329     if (err)
0330         err = device_property_read_u32(dev, "at25,byte-len", &val);
0331     if (err) {
0332         dev_err(dev, "Error: missing \"size\" property\n");
0333         return err;
0334     }
0335     chip->byte_len = val;
0336
0337     err = device_property_read_u32(dev, "pagesize", &val);
0338     if (err)
0339         err = device_property_read_u32(dev, "at25,page-size", &val);
0340     if (err) {
0341         dev_err(dev, "Error: missing \"pagesize\" property\n");
0342         return err;
0343     }
0344     chip->page_size = val;
0345
0346     err = device_property_read_u32(dev, "address-width", &val);
0347     if (err) {
0348         err = device_property_read_u32(dev, "at25,addr-mode", &val);
0349         if (err) {
0350             dev_err(dev, "Error: missing \"address-width\" property\n");
0351             return err;
0352         }
0353         chip->flags = (u16)val;
0354     } else {
0355         switch (val) {
0356         case 9:
0357             chip->flags |= EE_INSTR_BIT3_IS_ADDR;
0358             fallthrough;
0359         case 8:
0360             chip->flags |= EE_ADDR1;
0361             break;
0362         case 16:
0363             chip->flags |= EE_ADDR2;
0364             break;
0365         case 24:
0366             chip->flags |= EE_ADDR3;
0367             break;
0368         default:
0369             dev_err(dev,
0370                 "Error: bad \"address-width\" property: %u\n",
0371                 val);
0372             return -ENODEV;
0373         }
0374         if (device_property_present(dev, "read-only"))
0375             chip->flags |= EE_READONLY;
0376     }
0377     return 0;
0378 }
0379
0380 static int at25_fram_to_chip(struct device *dev, struct spi_eeprom *chip)
0381 {
0382     struct at25_data *at25 = container_of(chip, struct at25_data, chip);
0383     u8 sernum[FM25_SN_LEN];
0384     u8 id[FM25_ID_LEN];
0385     int i;
0386
0387     strscpy(chip->name, "fm25", sizeof(chip->name));
0388
0389     /* Get ID of chip */
0390     fm25_aux_read(at25, id, FM25_RDID, FM25_ID_LEN);
0391     if (id[6] != 0xc2) {
0392         dev_err(dev, "Error: no Cypress FRAM (id %02x)\n", id[6]);
0393         return -ENODEV;
0394     }
0395     /* Set size found in ID */
0396     if (id[7] < 0x21 || id[7] > 0x26) {
0397         dev_err(dev, "Error: unsupported size (id %02x)\n", id[7]);
0398         return -ENODEV;
0399     }
0400
0401     chip->byte_len = BIT(id[7] - 0x21 + 4) * 1024;
0402     if (chip->byte_len > 64 * 1024)
0403         chip->flags |= EE_ADDR3;
0404     else
0405         chip->flags |= EE_ADDR2;
0406
0407     if (id[8]) {
0408         fm25_aux_read(at25, sernum, FM25_RDSN, FM25_SN_LEN);
0409         /* Swap byte order */
0410         for (i = 0; i < FM25_SN_LEN; i++)
0411             at25->sernum[i] = sernum[FM25_SN_LEN - 1 - i];
0412     }
0413
0414     chip->page_size = PAGE_SIZE;
0415     return 0;
0416 }
0417
0418 static const struct of_device_id at25_of_match[] = {
0419     { .compatible = "atmel,at25" },
0420     { .compatible = "cypress,fm25" },
0421     { }
0422 };
0423 MODULE_DEVICE_TABLE(of, at25_of_match);
0424
0425 static const struct spi_device_id at25_spi_ids[] = {
0426     { .name = "at25" },
0427     { .name = "fm25" },
0428     { }
0429 };
0430 MODULE_DEVICE_TABLE(spi, at25_spi_ids);
0431
0432 static int at25_probe(struct spi_device *spi)
0433 {
0434     struct at25_data    *at25 = NULL;
0435     int         err;
0436     int         sr;
0437     struct spi_eeprom *pdata;
0438     bool is_fram;
0439
0440     err = device_property_match_string(&spi->dev, "compatible", "cypress,fm25");
0441     if (err >= 0)
0442         is_fram = true;
0443     else
0444         is_fram = false;
0445
0446     /*
0447      * Ping the chip ... the status register is pretty portable,
0448      * unlike probing manufacturer IDs. We do expect that system
0449      * firmware didn't write it in the past few milliseconds!
0450      */
0451     sr = spi_w8r8(spi, AT25_RDSR);
0452     if (sr < 0 || sr & AT25_SR_nRDY) {
0453         dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr);
0454         return -ENXIO;
0455     }
0456
0457     at25 = devm_kzalloc(&spi->dev, sizeof(*at25), GFP_KERNEL);
0458     if (!at25)
0459         return -ENOMEM;
0460
0461     mutex_init(&at25->lock);
0462     at25->spi = spi;
0463     spi_set_drvdata(spi, at25);
0464
0465     /* Chip description */
0466     pdata = dev_get_platdata(&spi->dev);
0467     if (pdata) {
0468         at25->chip = *pdata;
0469     } else {
0470         if (is_fram)
0471             err = at25_fram_to_chip(&spi->dev, &at25->chip);
0472         else
0473             err = at25_fw_to_chip(&spi->dev, &at25->chip);
0474         if (err)
0475             return err;
0476     }
0477
0478     /* For now we only support 8/16/24 bit addressing */
0479     if (at25->chip.flags & EE_ADDR1)
0480         at25->addrlen = 1;
0481     else if (at25->chip.flags & EE_ADDR2)
0482         at25->addrlen = 2;
0483     else if (at25->chip.flags & EE_ADDR3)
0484         at25->addrlen = 3;
0485     else {
0486         dev_dbg(&spi->dev, "unsupported address type\n");
0487         return -EINVAL;
0488     }
0489
0490     at25->nvmem_config.type = is_fram ? NVMEM_TYPE_FRAM : NVMEM_TYPE_EEPROM;
0491     at25->nvmem_config.name = dev_name(&spi->dev);
0492     at25->nvmem_config.dev = &spi->dev;
0493     at25->nvmem_config.read_only = at25->chip.flags & EE_READONLY;
0494     at25->nvmem_config.root_only = true;
0495     at25->nvmem_config.owner = THIS_MODULE;
0496     at25->nvmem_config.compat = true;
0497     at25->nvmem_config.base_dev = &spi->dev;
0498     at25->nvmem_config.reg_read = at25_ee_read;
0499     at25->nvmem_config.reg_write = at25_ee_write;
0500     at25->nvmem_config.priv = at25;
0501     at25->nvmem_config.stride = 1;
0502     at25->nvmem_config.word_size = 1;
0503     at25->nvmem_config.size = at25->chip.byte_len;
0504
0505     at25->nvmem = devm_nvmem_register(&spi->dev, &at25->nvmem_config);
0506     if (IS_ERR(at25->nvmem))
0507         return PTR_ERR(at25->nvmem);
0508
0509     dev_info(&spi->dev, "%d %s %s %s%s, pagesize %u\n",
0510          (at25->chip.byte_len < 1024) ?
0511             at25->chip.byte_len : (at25->chip.byte_len / 1024),
0512          (at25->chip.byte_len < 1024) ? "Byte" : "KByte",
0513          at25->chip.name, is_fram ? "fram" : "eeprom",
0514          (at25->chip.flags & EE_READONLY) ? " (readonly)" : "",
0515          at25->chip.page_size);
0516     return 0;
0517 }
0518
0519 /*-------------------------------------------------------------------------*/
0520
0521 static struct spi_driver at25_driver = {
0522     .driver = {
0523         .name       = "at25",
0524         .of_match_table = at25_of_match,
0525         .dev_groups = sernum_groups,
0526     },
0527     .probe      = at25_probe,
0528     .id_table   = at25_spi_ids,
0529 };
0530
0531 module_spi_driver(at25_driver);
0532
0533 MODULE_DESCRIPTION("Driver for most SPI EEPROMs");
0534 MODULE_AUTHOR("David Brownell");
0535 MODULE_LICENSE("GPL");
0536 MODULE_ALIAS("spi:at25");