drivers/misc/dw-xdata-pcie.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates.
0004  * Synopsys DesignWare xData driver
0005  *
0006  * Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
0007  */
0008
0009 #include <linux/miscdevice.h>
0010 #include <linux/bitfield.h>
0011 #include <linux/pci-epf.h>
0012 #include <linux/kernel.h>
0013 #include <linux/module.h>
0014 #include <linux/device.h>
0015 #include <linux/bitops.h>
0016 #include <linux/mutex.h>
0017 #include <linux/delay.h>
0018 #include <linux/pci.h>
0019
0020 #define DW_XDATA_DRIVER_NAME        "dw-xdata-pcie"
0021
0022 #define DW_XDATA_EP_MEM_OFFSET      0x8000000
0023
0024 static DEFINE_IDA(xdata_ida);
0025
0026 #define STATUS_DONE         BIT(0)
0027
0028 #define CONTROL_DOORBELL        BIT(0)
0029 #define CONTROL_IS_WRITE        BIT(1)
0030 #define CONTROL_LENGTH(a)       FIELD_PREP(GENMASK(13, 2), a)
0031 #define CONTROL_PATTERN_INC     BIT(16)
0032 #define CONTROL_NO_ADDR_INC     BIT(18)
0033
0034 #define XPERF_CONTROL_ENABLE        BIT(5)
0035
0036 #define BURST_REPEAT            BIT(31)
0037 #define BURST_VALUE         0x1001
0038
0039 #define PATTERN_VALUE           0x0
0040
0041 struct dw_xdata_regs {
0042     u32 addr_lsb;                   /* 0x000 */
0043     u32 addr_msb;                   /* 0x004 */
0044     u32 burst_cnt;                  /* 0x008 */
0045     u32 control;                    /* 0x00c */
0046     u32 pattern;                    /* 0x010 */
0047     u32 status;                 /* 0x014 */
0048     u32 RAM_addr;                   /* 0x018 */
0049     u32 RAM_port;                   /* 0x01c */
0050     u32 _reserved0[14];             /* 0x020..0x054 */
0051     u32 perf_control;               /* 0x058 */
0052     u32 _reserved1[41];             /* 0x05c..0x0fc */
0053     u32 wr_cnt_lsb;                 /* 0x100 */
0054     u32 wr_cnt_msb;                 /* 0x104 */
0055     u32 rd_cnt_lsb;                 /* 0x108 */
0056     u32 rd_cnt_msb;                 /* 0x10c */
0057 } __packed;
0058
0059 struct dw_xdata_region {
0060     phys_addr_t paddr;              /* physical address */
0061     void __iomem *vaddr;                /* virtual address */
0062 };
0063
0064 struct dw_xdata {
0065     struct dw_xdata_region rg_region;       /* registers */
0066     size_t max_wr_len;              /* max wr xfer len */
0067     size_t max_rd_len;              /* max rd xfer len */
0068     struct mutex mutex;
0069     struct pci_dev *pdev;
0070     struct miscdevice misc_dev;
0071 };
0072
0073 static inline struct dw_xdata_regs __iomem *__dw_regs(struct dw_xdata *dw)
0074 {
0075     return dw->rg_region.vaddr;
0076 }
0077
0078 static void dw_xdata_stop(struct dw_xdata *dw)
0079 {
0080     u32 burst;
0081
0082     mutex_lock(&dw->mutex);
0083
0084     burst = readl(&(__dw_regs(dw)->burst_cnt));
0085
0086     if (burst & BURST_REPEAT) {
0087         burst &= ~(u32)BURST_REPEAT;
0088         writel(burst, &(__dw_regs(dw)->burst_cnt));
0089     }
0090
0091     mutex_unlock(&dw->mutex);
0092 }
0093
0094 static void dw_xdata_start(struct dw_xdata *dw, bool write)
0095 {
0096     struct device *dev = &dw->pdev->dev;
0097     u32 control, status;
0098
0099     /* Stop first if xfer in progress */
0100     dw_xdata_stop(dw);
0101
0102     mutex_lock(&dw->mutex);
0103
0104     /* Clear status register */
0105     writel(0x0, &(__dw_regs(dw)->status));
0106
0107     /* Burst count register set for continuous until stopped */
0108     writel(BURST_REPEAT | BURST_VALUE, &(__dw_regs(dw)->burst_cnt));
0109
0110     /* Pattern register */
0111     writel(PATTERN_VALUE, &(__dw_regs(dw)->pattern));
0112
0113     /* Control register */
0114     control = CONTROL_DOORBELL | CONTROL_PATTERN_INC | CONTROL_NO_ADDR_INC;
0115     if (write) {
0116         control |= CONTROL_IS_WRITE;
0117         control |= CONTROL_LENGTH(dw->max_wr_len);
0118     } else {
0119         control |= CONTROL_LENGTH(dw->max_rd_len);
0120     }
0121     writel(control, &(__dw_regs(dw)->control));
0122
0123     /*
0124      * The xData HW block needs about 100 ms to initiate the traffic
0125      * generation according this HW block datasheet.
0126      */
0127     usleep_range(100, 150);
0128
0129     status = readl(&(__dw_regs(dw)->status));
0130
0131     mutex_unlock(&dw->mutex);
0132
0133     if (!(status & STATUS_DONE))
0134         dev_dbg(dev, "xData: started %s direction\n",
0135             write ? "write" : "read");
0136 }
0137
0138 static void dw_xdata_perf_meas(struct dw_xdata *dw, u64 *data, bool write)
0139 {
0140     if (write) {
0141         *data = readl(&(__dw_regs(dw)->wr_cnt_msb));
0142         *data <<= 32;
0143         *data |= readl(&(__dw_regs(dw)->wr_cnt_lsb));
0144     } else {
0145         *data = readl(&(__dw_regs(dw)->rd_cnt_msb));
0146         *data <<= 32;
0147         *data |= readl(&(__dw_regs(dw)->rd_cnt_lsb));
0148     }
0149 }
0150
0151 static u64 dw_xdata_perf_diff(u64 *m1, u64 *m2, u64 time)
0152 {
0153     u64 rate = (*m1 - *m2);
0154
0155     rate *= (1000 * 1000 * 1000);
0156     rate >>= 20;
0157     rate = DIV_ROUND_CLOSEST_ULL(rate, time);
0158
0159     return rate;
0160 }
0161
0162 static void dw_xdata_perf(struct dw_xdata *dw, u64 *rate, bool write)
0163 {
0164     struct device *dev = &dw->pdev->dev;
0165     u64 data[2], time[2], diff;
0166
0167     mutex_lock(&dw->mutex);
0168
0169     /* First acquisition of current count frames */
0170     writel(0x0, &(__dw_regs(dw)->perf_control));
0171     dw_xdata_perf_meas(dw, &data[0], write);
0172     time[0] = jiffies;
0173     writel((u32)XPERF_CONTROL_ENABLE, &(__dw_regs(dw)->perf_control));
0174
0175     /*
0176      * Wait 100ms between the 1st count frame acquisition and the 2nd
0177      * count frame acquisition, in order to calculate the speed later
0178      */
0179     mdelay(100);
0180
0181     /* Second acquisition of current count frames */
0182     writel(0x0, &(__dw_regs(dw)->perf_control));
0183     dw_xdata_perf_meas(dw, &data[1], write);
0184     time[1] = jiffies;
0185     writel((u32)XPERF_CONTROL_ENABLE, &(__dw_regs(dw)->perf_control));
0186
0187     /*
0188      * Speed calculation
0189      *
0190      * rate = (2nd count frames - 1st count frames) / (time elapsed)
0191      */
0192     diff = jiffies_to_nsecs(time[1] - time[0]);
0193     *rate = dw_xdata_perf_diff(&data[1], &data[0], diff);
0194
0195     mutex_unlock(&dw->mutex);
0196
0197     dev_dbg(dev, "xData: time=%llu us, %s=%llu MB/s\n",
0198         diff, write ? "write" : "read", *rate);
0199 }
0200
0201 static struct dw_xdata *misc_dev_to_dw(struct miscdevice *misc_dev)
0202 {
0203     return container_of(misc_dev, struct dw_xdata, misc_dev);
0204 }
0205
0206 static ssize_t write_show(struct device *dev, struct device_attribute *attr,
0207               char *buf)
0208 {
0209     struct miscdevice *misc_dev = dev_get_drvdata(dev);
0210     struct dw_xdata *dw = misc_dev_to_dw(misc_dev);
0211     u64 rate;
0212
0213     dw_xdata_perf(dw, &rate, true);
0214
0215     return sysfs_emit(buf, "%llu\n", rate);
0216 }
0217
0218 static ssize_t write_store(struct device *dev, struct device_attribute *attr,
0219                const char *buf, size_t size)
0220 {
0221     struct miscdevice *misc_dev = dev_get_drvdata(dev);
0222     struct dw_xdata *dw = misc_dev_to_dw(misc_dev);
0223     bool enabled;
0224     int ret;
0225
0226     ret = kstrtobool(buf, &enabled);
0227     if (ret < 0)
0228         return ret;
0229
0230     if (enabled) {
0231         dev_dbg(dev, "xData: requested write transfer\n");
0232         dw_xdata_start(dw, true);
0233     } else {
0234         dev_dbg(dev, "xData: requested stop transfer\n");
0235         dw_xdata_stop(dw);
0236     }
0237
0238     return size;
0239 }
0240
0241 static DEVICE_ATTR_RW(write);
0242
0243 static ssize_t read_show(struct device *dev, struct device_attribute *attr,
0244              char *buf)
0245 {
0246     struct miscdevice *misc_dev = dev_get_drvdata(dev);
0247     struct dw_xdata *dw = misc_dev_to_dw(misc_dev);
0248     u64 rate;
0249
0250     dw_xdata_perf(dw, &rate, false);
0251
0252     return sysfs_emit(buf, "%llu\n", rate);
0253 }
0254
0255 static ssize_t read_store(struct device *dev, struct device_attribute *attr,
0256               const char *buf, size_t size)
0257 {
0258     struct miscdevice *misc_dev = dev_get_drvdata(dev);
0259     struct dw_xdata *dw = misc_dev_to_dw(misc_dev);
0260     bool enabled;
0261     int ret;
0262
0263     ret = kstrtobool(buf, &enabled);
0264     if (ret < 0)
0265         return ret;
0266
0267     if (enabled) {
0268         dev_dbg(dev, "xData: requested read transfer\n");
0269         dw_xdata_start(dw, false);
0270     } else {
0271         dev_dbg(dev, "xData: requested stop transfer\n");
0272         dw_xdata_stop(dw);
0273     }
0274
0275     return size;
0276 }
0277
0278 static DEVICE_ATTR_RW(read);
0279
0280 static struct attribute *xdata_attrs[] = {
0281     &dev_attr_write.attr,
0282     &dev_attr_read.attr,
0283     NULL,
0284 };
0285
0286 ATTRIBUTE_GROUPS(xdata);
0287
0288 static int dw_xdata_pcie_probe(struct pci_dev *pdev,
0289                    const struct pci_device_id *pid)
0290 {
0291     struct device *dev = &pdev->dev;
0292     struct dw_xdata *dw;
0293     char name[24];
0294     u64 addr;
0295     int err;
0296     int id;
0297
0298     /* Enable PCI device */
0299     err = pcim_enable_device(pdev);
0300     if (err) {
0301         dev_err(dev, "enabling device failed\n");
0302         return err;
0303     }
0304
0305     /* Mapping PCI BAR regions */
0306     err = pcim_iomap_regions(pdev, BIT(BAR_0), pci_name(pdev));
0307     if (err) {
0308         dev_err(dev, "xData BAR I/O remapping failed\n");
0309         return err;
0310     }
0311
0312     pci_set_master(pdev);
0313
0314     /* Allocate memory */
0315     dw = devm_kzalloc(dev, sizeof(*dw), GFP_KERNEL);
0316     if (!dw)
0317         return -ENOMEM;
0318
0319     /* Data structure initialization */
0320     mutex_init(&dw->mutex);
0321
0322     dw->rg_region.vaddr = pcim_iomap_table(pdev)[BAR_0];
0323     if (!dw->rg_region.vaddr)
0324         return -ENOMEM;
0325
0326     dw->rg_region.paddr = pdev->resource[BAR_0].start;
0327
0328     dw->max_wr_len = pcie_get_mps(pdev);
0329     dw->max_wr_len >>= 2;
0330
0331     dw->max_rd_len = pcie_get_readrq(pdev);
0332     dw->max_rd_len >>= 2;
0333
0334     dw->pdev = pdev;
0335
0336     id = ida_simple_get(&xdata_ida, 0, 0, GFP_KERNEL);
0337     if (id < 0) {
0338         dev_err(dev, "xData: unable to get id\n");
0339         return id;
0340     }
0341
0342     snprintf(name, sizeof(name), DW_XDATA_DRIVER_NAME ".%d", id);
0343     dw->misc_dev.name = kstrdup(name, GFP_KERNEL);
0344     if (!dw->misc_dev.name) {
0345         err = -ENOMEM;
0346         goto err_ida_remove;
0347     }
0348
0349     dw->misc_dev.minor = MISC_DYNAMIC_MINOR;
0350     dw->misc_dev.parent = dev;
0351     dw->misc_dev.groups = xdata_groups;
0352
0353     writel(0x0, &(__dw_regs(dw)->RAM_addr));
0354     writel(0x0, &(__dw_regs(dw)->RAM_port));
0355
0356     addr = dw->rg_region.paddr + DW_XDATA_EP_MEM_OFFSET;
0357     writel(lower_32_bits(addr), &(__dw_regs(dw)->addr_lsb));
0358     writel(upper_32_bits(addr), &(__dw_regs(dw)->addr_msb));
0359     dev_dbg(dev, "xData: target address = 0x%.16llx\n", addr);
0360
0361     dev_dbg(dev, "xData: wr_len = %zu, rd_len = %zu\n",
0362         dw->max_wr_len * 4, dw->max_rd_len * 4);
0363
0364     /* Saving data structure reference */
0365     pci_set_drvdata(pdev, dw);
0366
0367     /* Register misc device */
0368     err = misc_register(&dw->misc_dev);
0369     if (err) {
0370         dev_err(dev, "xData: failed to register device\n");
0371         goto err_kfree_name;
0372     }
0373
0374     return 0;
0375
0376 err_kfree_name:
0377     kfree(dw->misc_dev.name);
0378
0379 err_ida_remove:
0380     ida_simple_remove(&xdata_ida, id);
0381
0382     return err;
0383 }
0384
0385 static void dw_xdata_pcie_remove(struct pci_dev *pdev)
0386 {
0387     struct dw_xdata *dw = pci_get_drvdata(pdev);
0388     int id;
0389
0390     if (sscanf(dw->misc_dev.name, DW_XDATA_DRIVER_NAME ".%d", &id) != 1)
0391         return;
0392
0393     if (id < 0)
0394         return;
0395
0396     dw_xdata_stop(dw);
0397     misc_deregister(&dw->misc_dev);
0398     kfree(dw->misc_dev.name);
0399     ida_simple_remove(&xdata_ida, id);
0400 }
0401
0402 static const struct pci_device_id dw_xdata_pcie_id_table[] = {
0403     { PCI_DEVICE_DATA(SYNOPSYS, EDDA, NULL) },
0404     { }
0405 };
0406 MODULE_DEVICE_TABLE(pci, dw_xdata_pcie_id_table);
0407
0408 static struct pci_driver dw_xdata_pcie_driver = {
0409     .name       = DW_XDATA_DRIVER_NAME,
0410     .id_table   = dw_xdata_pcie_id_table,
0411     .probe      = dw_xdata_pcie_probe,
0412     .remove     = dw_xdata_pcie_remove,
0413 };
0414
0415 module_pci_driver(dw_xdata_pcie_driver);
0416
0417 MODULE_LICENSE("GPL v2");
0418 MODULE_DESCRIPTION("Synopsys DesignWare xData PCIe driver");
0419 MODULE_AUTHOR("Gustavo Pimentel <gustavo.pimentel@synopsys.com>");
0420