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0006 #include <linux/spinlock.h>
0007 #include <linux/kernel.h>
0008 #include <linux/module.h>
0009 #include <linux/device.h>
0010 #include <linux/mutex.h>
0011 #include <linux/init.h>
0012 #include <linux/list.h>
0013 #include <linux/mm.h>
0014 #include <linux/of.h>
0015 #include <linux/slab.h>
0016 #include <linux/idr.h>
0017 #include <linux/pci.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/sched/task.h>
0020
0021 #include <asm/cputable.h>
0022 #include <asm/mmu.h>
0023 #include <misc/cxl-base.h>
0024
0025 #include "cxl.h"
0026 #include "trace.h"
0027
0028 static DEFINE_SPINLOCK(adapter_idr_lock);
0029 static DEFINE_IDR(cxl_adapter_idr);
0030
0031 uint cxl_verbose;
0032 module_param_named(verbose, cxl_verbose, uint, 0600);
0033 MODULE_PARM_DESC(verbose, "Enable verbose dmesg output");
0034
0035 const struct cxl_backend_ops *cxl_ops;
0036
0037 int cxl_afu_slbia(struct cxl_afu *afu)
0038 {
0039 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
0040
0041 pr_devel("cxl_afu_slbia issuing SLBIA command\n");
0042 cxl_p2n_write(afu, CXL_SLBIA_An, CXL_TLB_SLB_IQ_ALL);
0043 while (cxl_p2n_read(afu, CXL_SLBIA_An) & CXL_TLB_SLB_P) {
0044 if (time_after_eq(jiffies, timeout)) {
0045 dev_warn(&afu->dev, "WARNING: CXL AFU SLBIA timed out!\n");
0046 return -EBUSY;
0047 }
0048
0049
0050
0051 if (!cxl_ops->link_ok(afu->adapter, afu))
0052 return -EIO;
0053 cpu_relax();
0054 }
0055 return 0;
0056 }
0057
0058 static inline void _cxl_slbia(struct cxl_context *ctx, struct mm_struct *mm)
0059 {
0060 unsigned long flags;
0061
0062 if (ctx->mm != mm)
0063 return;
0064
0065 pr_devel("%s matched mm - card: %i afu: %i pe: %i\n", __func__,
0066 ctx->afu->adapter->adapter_num, ctx->afu->slice, ctx->pe);
0067
0068 spin_lock_irqsave(&ctx->sste_lock, flags);
0069 trace_cxl_slbia(ctx);
0070 memset(ctx->sstp, 0, ctx->sst_size);
0071 spin_unlock_irqrestore(&ctx->sste_lock, flags);
0072 mb();
0073 cxl_afu_slbia(ctx->afu);
0074 }
0075
0076 static inline void cxl_slbia_core(struct mm_struct *mm)
0077 {
0078 struct cxl *adapter;
0079 struct cxl_afu *afu;
0080 struct cxl_context *ctx;
0081 int card, slice, id;
0082
0083 pr_devel("%s called\n", __func__);
0084
0085 spin_lock(&adapter_idr_lock);
0086 idr_for_each_entry(&cxl_adapter_idr, adapter, card) {
0087
0088 spin_lock(&adapter->afu_list_lock);
0089 for (slice = 0; slice < adapter->slices; slice++) {
0090 afu = adapter->afu[slice];
0091 if (!afu || !afu->enabled)
0092 continue;
0093 rcu_read_lock();
0094 idr_for_each_entry(&afu->contexts_idr, ctx, id)
0095 _cxl_slbia(ctx, mm);
0096 rcu_read_unlock();
0097 }
0098 spin_unlock(&adapter->afu_list_lock);
0099 }
0100 spin_unlock(&adapter_idr_lock);
0101 }
0102
0103 static struct cxl_calls cxl_calls = {
0104 .cxl_slbia = cxl_slbia_core,
0105 .owner = THIS_MODULE,
0106 };
0107
0108 int cxl_alloc_sst(struct cxl_context *ctx)
0109 {
0110 unsigned long vsid;
0111 u64 ea_mask, size, sstp0, sstp1;
0112
0113 sstp0 = 0;
0114 sstp1 = 0;
0115
0116 ctx->sst_size = PAGE_SIZE;
0117 ctx->sst_lru = 0;
0118 ctx->sstp = (struct cxl_sste *)get_zeroed_page(GFP_KERNEL);
0119 if (!ctx->sstp) {
0120 pr_err("cxl_alloc_sst: Unable to allocate segment table\n");
0121 return -ENOMEM;
0122 }
0123 pr_devel("SSTP allocated at 0x%p\n", ctx->sstp);
0124
0125 vsid = get_kernel_vsid((u64)ctx->sstp, mmu_kernel_ssize) << 12;
0126
0127 sstp0 |= (u64)mmu_kernel_ssize << CXL_SSTP0_An_B_SHIFT;
0128 sstp0 |= (SLB_VSID_KERNEL | mmu_psize_defs[mmu_linear_psize].sllp) << 50;
0129
0130 size = (((u64)ctx->sst_size >> 8) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT;
0131 if (unlikely(size & ~CXL_SSTP0_An_SegTableSize_MASK)) {
0132 WARN(1, "Impossible segment table size\n");
0133 return -EINVAL;
0134 }
0135 sstp0 |= size;
0136
0137 if (mmu_kernel_ssize == MMU_SEGSIZE_256M)
0138 ea_mask = 0xfffff00ULL;
0139 else
0140 ea_mask = 0xffffffff00ULL;
0141
0142 sstp0 |= vsid >> (50-14);
0143 sstp1 |= (vsid << (64-(50-14))) & ~ea_mask;
0144 sstp1 |= (u64)ctx->sstp & ea_mask;
0145 sstp1 |= CXL_SSTP1_An_V;
0146
0147 pr_devel("Looked up %#llx: slbfee. %#llx (ssize: %x, vsid: %#lx), copied to SSTP0: %#llx, SSTP1: %#llx\n",
0148 (u64)ctx->sstp, (u64)ctx->sstp & ESID_MASK, mmu_kernel_ssize, vsid, sstp0, sstp1);
0149
0150
0151 ctx->sstp0 = sstp0;
0152 ctx->sstp1 = sstp1;
0153
0154 return 0;
0155 }
0156
0157
0158 void cxl_dump_debug_buffer(void *buf, size_t buf_len)
0159 {
0160 #ifdef DEBUG
0161 int i, *ptr;
0162
0163
0164
0165
0166
0167 ptr = (int *) buf;
0168 for (i = 0; i * 4 < buf_len; i += 4) {
0169 if ((i + 3) * 4 < buf_len)
0170 pr_devel("%.8x %.8x %.8x %.8x\n", ptr[i], ptr[i + 1],
0171 ptr[i + 2], ptr[i + 3]);
0172 else if ((i + 2) * 4 < buf_len)
0173 pr_devel("%.8x %.8x %.8x\n", ptr[i], ptr[i + 1],
0174 ptr[i + 2]);
0175 else if ((i + 1) * 4 < buf_len)
0176 pr_devel("%.8x %.8x\n", ptr[i], ptr[i + 1]);
0177 else
0178 pr_devel("%.8x\n", ptr[i]);
0179 }
0180 #endif
0181 }
0182
0183
0184 struct cxl *get_cxl_adapter(int num)
0185 {
0186 struct cxl *adapter;
0187
0188 spin_lock(&adapter_idr_lock);
0189 if ((adapter = idr_find(&cxl_adapter_idr, num)))
0190 get_device(&adapter->dev);
0191 spin_unlock(&adapter_idr_lock);
0192
0193 return adapter;
0194 }
0195
0196 static int cxl_alloc_adapter_nr(struct cxl *adapter)
0197 {
0198 int i;
0199
0200 idr_preload(GFP_KERNEL);
0201 spin_lock(&adapter_idr_lock);
0202 i = idr_alloc(&cxl_adapter_idr, adapter, 0, 0, GFP_NOWAIT);
0203 spin_unlock(&adapter_idr_lock);
0204 idr_preload_end();
0205 if (i < 0)
0206 return i;
0207
0208 adapter->adapter_num = i;
0209
0210 return 0;
0211 }
0212
0213 void cxl_remove_adapter_nr(struct cxl *adapter)
0214 {
0215 idr_remove(&cxl_adapter_idr, adapter->adapter_num);
0216 }
0217
0218 struct cxl *cxl_alloc_adapter(void)
0219 {
0220 struct cxl *adapter;
0221
0222 if (!(adapter = kzalloc(sizeof(struct cxl), GFP_KERNEL)))
0223 return NULL;
0224
0225 spin_lock_init(&adapter->afu_list_lock);
0226
0227 if (cxl_alloc_adapter_nr(adapter))
0228 goto err1;
0229
0230 if (dev_set_name(&adapter->dev, "card%i", adapter->adapter_num))
0231 goto err2;
0232
0233
0234 atomic_set(&adapter->contexts_num, -1);
0235
0236 return adapter;
0237 err2:
0238 cxl_remove_adapter_nr(adapter);
0239 err1:
0240 kfree(adapter);
0241 return NULL;
0242 }
0243
0244 struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice)
0245 {
0246 struct cxl_afu *afu;
0247
0248 if (!(afu = kzalloc(sizeof(struct cxl_afu), GFP_KERNEL)))
0249 return NULL;
0250
0251 afu->adapter = adapter;
0252 afu->dev.parent = &adapter->dev;
0253 afu->dev.release = cxl_ops->release_afu;
0254 afu->slice = slice;
0255 idr_init(&afu->contexts_idr);
0256 mutex_init(&afu->contexts_lock);
0257 spin_lock_init(&afu->afu_cntl_lock);
0258 atomic_set(&afu->configured_state, -1);
0259 afu->prefault_mode = CXL_PREFAULT_NONE;
0260 afu->irqs_max = afu->adapter->user_irqs;
0261
0262 return afu;
0263 }
0264
0265 int cxl_afu_select_best_mode(struct cxl_afu *afu)
0266 {
0267 if (afu->modes_supported & CXL_MODE_DIRECTED)
0268 return cxl_ops->afu_activate_mode(afu, CXL_MODE_DIRECTED);
0269
0270 if (afu->modes_supported & CXL_MODE_DEDICATED)
0271 return cxl_ops->afu_activate_mode(afu, CXL_MODE_DEDICATED);
0272
0273 dev_warn(&afu->dev, "No supported programming modes available\n");
0274
0275 return 0;
0276 }
0277
0278 int cxl_adapter_context_get(struct cxl *adapter)
0279 {
0280 int rc;
0281
0282 rc = atomic_inc_unless_negative(&adapter->contexts_num);
0283 return rc ? 0 : -EBUSY;
0284 }
0285
0286 void cxl_adapter_context_put(struct cxl *adapter)
0287 {
0288 atomic_dec_if_positive(&adapter->contexts_num);
0289 }
0290
0291 int cxl_adapter_context_lock(struct cxl *adapter)
0292 {
0293 int rc;
0294
0295 rc = atomic_cmpxchg(&adapter->contexts_num, 0, -1);
0296 return rc ? -EBUSY : 0;
0297 }
0298
0299 void cxl_adapter_context_unlock(struct cxl *adapter)
0300 {
0301 int val = atomic_cmpxchg(&adapter->contexts_num, -1, 0);
0302
0303
0304
0305
0306
0307
0308
0309 if (val != -1) {
0310 atomic_set(&adapter->contexts_num, 0);
0311 WARN(1, "Adapter context unlocked with %d active contexts",
0312 val);
0313 }
0314 }
0315
0316 static int __init init_cxl(void)
0317 {
0318 int rc = 0;
0319
0320 if (!tlbie_capable)
0321 return -EINVAL;
0322
0323 if ((rc = cxl_file_init()))
0324 return rc;
0325
0326 cxl_debugfs_init();
0327
0328
0329
0330
0331
0332 if (cxl_is_power8()) {
0333 rc = register_cxl_calls(&cxl_calls);
0334 if (rc)
0335 goto err;
0336 }
0337
0338 if (cpu_has_feature(CPU_FTR_HVMODE)) {
0339 cxl_ops = &cxl_native_ops;
0340 rc = pci_register_driver(&cxl_pci_driver);
0341 }
0342 #ifdef CONFIG_PPC_PSERIES
0343 else {
0344 cxl_ops = &cxl_guest_ops;
0345 rc = platform_driver_register(&cxl_of_driver);
0346 }
0347 #endif
0348 if (rc)
0349 goto err1;
0350
0351 return 0;
0352 err1:
0353 if (cxl_is_power8())
0354 unregister_cxl_calls(&cxl_calls);
0355 err:
0356 cxl_debugfs_exit();
0357 cxl_file_exit();
0358
0359 return rc;
0360 }
0361
0362 static void exit_cxl(void)
0363 {
0364 if (cpu_has_feature(CPU_FTR_HVMODE))
0365 pci_unregister_driver(&cxl_pci_driver);
0366 #ifdef CONFIG_PPC_PSERIES
0367 else
0368 platform_driver_unregister(&cxl_of_driver);
0369 #endif
0370
0371 cxl_debugfs_exit();
0372 cxl_file_exit();
0373 if (cxl_is_power8())
0374 unregister_cxl_calls(&cxl_calls);
0375 idr_destroy(&cxl_adapter_idr);
0376 }
0377
0378 module_init(init_cxl);
0379 module_exit(exit_cxl);
0380
0381 MODULE_DESCRIPTION("IBM Coherent Accelerator");
0382 MODULE_AUTHOR("Ian Munsie <imunsie@au1.ibm.com>");
0383 MODULE_LICENSE("GPL");