Back to home page

OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright 2014 IBM Corp.
0004  */
0005 
0006 #ifndef _CXL_H_
0007 #define _CXL_H_
0008 
0009 #include <linux/interrupt.h>
0010 #include <linux/semaphore.h>
0011 #include <linux/device.h>
0012 #include <linux/types.h>
0013 #include <linux/cdev.h>
0014 #include <linux/pid.h>
0015 #include <linux/io.h>
0016 #include <linux/pci.h>
0017 #include <linux/fs.h>
0018 #include <asm/cputable.h>
0019 #include <asm/mmu.h>
0020 #include <asm/reg.h>
0021 #include <misc/cxl-base.h>
0022 
0023 #include <misc/cxl.h>
0024 #include <uapi/misc/cxl.h>
0025 
0026 extern uint cxl_verbose;
0027 
0028 struct property;
0029 
0030 #define CXL_TIMEOUT 5
0031 
0032 /*
0033  * Bump version each time a user API change is made, whether it is
0034  * backwards compatible ot not.
0035  */
0036 #define CXL_API_VERSION 3
0037 #define CXL_API_VERSION_COMPATIBLE 1
0038 
0039 /*
0040  * Opaque types to avoid accidentally passing registers for the wrong MMIO
0041  *
0042  * At the end of the day, I'm not married to using typedef here, but it might
0043  * (and has!) help avoid bugs like mixing up CXL_PSL_CtxTime and
0044  * CXL_PSL_CtxTime_An, or calling cxl_p1n_write instead of cxl_p1_write.
0045  *
0046  * I'm quite happy if these are changed back to #defines before upstreaming, it
0047  * should be little more than a regexp search+replace operation in this file.
0048  */
0049 typedef struct {
0050     const int x;
0051 } cxl_p1_reg_t;
0052 typedef struct {
0053     const int x;
0054 } cxl_p1n_reg_t;
0055 typedef struct {
0056     const int x;
0057 } cxl_p2n_reg_t;
0058 #define cxl_reg_off(reg) \
0059     (reg.x)
0060 
0061 /* Memory maps. Ref CXL Appendix A */
0062 
0063 /* PSL Privilege 1 Memory Map */
0064 /* Configuration and Control area - CAIA 1&2 */
0065 static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000};
0066 static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008};
0067 static const cxl_p1_reg_t CXL_PSL_KEY1    = {0x0010};
0068 static const cxl_p1_reg_t CXL_PSL_KEY2    = {0x0018};
0069 static const cxl_p1_reg_t CXL_PSL_Control = {0x0020};
0070 /* Downloading */
0071 static const cxl_p1_reg_t CXL_PSL_DLCNTL  = {0x0060};
0072 static const cxl_p1_reg_t CXL_PSL_DLADDR  = {0x0068};
0073 
0074 /* PSL Lookaside Buffer Management Area - CAIA 1 */
0075 static const cxl_p1_reg_t CXL_PSL_LBISEL  = {0x0080};
0076 static const cxl_p1_reg_t CXL_PSL_SLBIE   = {0x0088};
0077 static const cxl_p1_reg_t CXL_PSL_SLBIA   = {0x0090};
0078 static const cxl_p1_reg_t CXL_PSL_TLBIE   = {0x00A0};
0079 static const cxl_p1_reg_t CXL_PSL_TLBIA   = {0x00A8};
0080 static const cxl_p1_reg_t CXL_PSL_AFUSEL  = {0x00B0};
0081 
0082 /* 0x00C0:7EFF Implementation dependent area */
0083 /* PSL registers - CAIA 1 */
0084 static const cxl_p1_reg_t CXL_PSL_FIR1      = {0x0100};
0085 static const cxl_p1_reg_t CXL_PSL_FIR2      = {0x0108};
0086 static const cxl_p1_reg_t CXL_PSL_Timebase  = {0x0110};
0087 static const cxl_p1_reg_t CXL_PSL_VERSION   = {0x0118};
0088 static const cxl_p1_reg_t CXL_PSL_RESLCKTO  = {0x0128};
0089 static const cxl_p1_reg_t CXL_PSL_TB_CTLSTAT = {0x0140};
0090 static const cxl_p1_reg_t CXL_PSL_FIR_CNTL  = {0x0148};
0091 static const cxl_p1_reg_t CXL_PSL_DSNDCTL   = {0x0150};
0092 static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158};
0093 static const cxl_p1_reg_t CXL_PSL_TRACE     = {0x0170};
0094 /* PSL registers - CAIA 2 */
0095 static const cxl_p1_reg_t CXL_PSL9_CONTROL  = {0x0020};
0096 static const cxl_p1_reg_t CXL_XSL9_INV      = {0x0110};
0097 static const cxl_p1_reg_t CXL_XSL9_DBG      = {0x0130};
0098 static const cxl_p1_reg_t CXL_XSL9_DEF      = {0x0140};
0099 static const cxl_p1_reg_t CXL_XSL9_DSNCTL   = {0x0168};
0100 static const cxl_p1_reg_t CXL_PSL9_FIR1     = {0x0300};
0101 static const cxl_p1_reg_t CXL_PSL9_FIR_MASK = {0x0308};
0102 static const cxl_p1_reg_t CXL_PSL9_Timebase = {0x0310};
0103 static const cxl_p1_reg_t CXL_PSL9_DEBUG    = {0x0320};
0104 static const cxl_p1_reg_t CXL_PSL9_FIR_CNTL = {0x0348};
0105 static const cxl_p1_reg_t CXL_PSL9_DSNDCTL  = {0x0350};
0106 static const cxl_p1_reg_t CXL_PSL9_TB_CTLSTAT = {0x0340};
0107 static const cxl_p1_reg_t CXL_PSL9_TRACECFG = {0x0368};
0108 static const cxl_p1_reg_t CXL_PSL9_APCDEDALLOC = {0x0378};
0109 static const cxl_p1_reg_t CXL_PSL9_APCDEDTYPE = {0x0380};
0110 static const cxl_p1_reg_t CXL_PSL9_TNR_ADDR = {0x0388};
0111 static const cxl_p1_reg_t CXL_PSL9_CTCCFG = {0x0390};
0112 static const cxl_p1_reg_t CXL_PSL9_GP_CT = {0x0398};
0113 static const cxl_p1_reg_t CXL_XSL9_IERAT = {0x0588};
0114 static const cxl_p1_reg_t CXL_XSL9_ILPP  = {0x0590};
0115 
0116 /* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */
0117 /* 0x8000:FFFF Reserved PCIe MSI-X Table Area */
0118 
0119 /* PSL Slice Privilege 1 Memory Map */
0120 /* Configuration Area - CAIA 1&2 */
0121 static const cxl_p1n_reg_t CXL_PSL_SR_An          = {0x00};
0122 static const cxl_p1n_reg_t CXL_PSL_LPID_An        = {0x08};
0123 static const cxl_p1n_reg_t CXL_PSL_AMBAR_An       = {0x10};
0124 static const cxl_p1n_reg_t CXL_PSL_SPOffset_An    = {0x18};
0125 static const cxl_p1n_reg_t CXL_PSL_ID_An          = {0x20};
0126 static const cxl_p1n_reg_t CXL_PSL_SERR_An        = {0x28};
0127 /* Memory Management and Lookaside Buffer Management - CAIA 1*/
0128 static const cxl_p1n_reg_t CXL_PSL_SDR_An         = {0x30};
0129 /* Memory Management and Lookaside Buffer Management - CAIA 1&2 */
0130 static const cxl_p1n_reg_t CXL_PSL_AMOR_An        = {0x38};
0131 /* Pointer Area - CAIA 1&2 */
0132 static const cxl_p1n_reg_t CXL_HAURP_An           = {0x80};
0133 static const cxl_p1n_reg_t CXL_PSL_SPAP_An        = {0x88};
0134 static const cxl_p1n_reg_t CXL_PSL_LLCMD_An       = {0x90};
0135 /* Control Area - CAIA 1&2 */
0136 static const cxl_p1n_reg_t CXL_PSL_SCNTL_An       = {0xA0};
0137 static const cxl_p1n_reg_t CXL_PSL_CtxTime_An     = {0xA8};
0138 static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0};
0139 static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An  = {0xB8};
0140 /* 0xC0:FF Implementation Dependent Area - CAIA 1&2 */
0141 static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An   = {0xC0};
0142 static const cxl_p1n_reg_t CXL_AFU_DEBUG_An       = {0xC8};
0143 /* 0xC0:FF Implementation Dependent Area - CAIA 1 */
0144 static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A     = {0xD0};
0145 static const cxl_p1n_reg_t CXL_PSL_COALLOC_A      = {0xD8};
0146 static const cxl_p1n_reg_t CXL_PSL_RXCTL_A        = {0xE0};
0147 static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE    = {0xE8};
0148 
0149 /* PSL Slice Privilege 2 Memory Map */
0150 /* Configuration and Control Area - CAIA 1&2 */
0151 static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000};
0152 static const cxl_p2n_reg_t CXL_CSRP_An        = {0x008};
0153 /* Configuration and Control Area - CAIA 1 */
0154 static const cxl_p2n_reg_t CXL_AURP0_An       = {0x010};
0155 static const cxl_p2n_reg_t CXL_AURP1_An       = {0x018};
0156 static const cxl_p2n_reg_t CXL_SSTP0_An       = {0x020};
0157 static const cxl_p2n_reg_t CXL_SSTP1_An       = {0x028};
0158 /* Configuration and Control Area - CAIA 1 */
0159 static const cxl_p2n_reg_t CXL_PSL_AMR_An     = {0x030};
0160 /* Segment Lookaside Buffer Management - CAIA 1 */
0161 static const cxl_p2n_reg_t CXL_SLBIE_An       = {0x040};
0162 static const cxl_p2n_reg_t CXL_SLBIA_An       = {0x048};
0163 static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050};
0164 /* Interrupt Registers - CAIA 1&2 */
0165 static const cxl_p2n_reg_t CXL_PSL_DSISR_An   = {0x060};
0166 static const cxl_p2n_reg_t CXL_PSL_DAR_An     = {0x068};
0167 static const cxl_p2n_reg_t CXL_PSL_DSR_An     = {0x070};
0168 static const cxl_p2n_reg_t CXL_PSL_TFC_An     = {0x078};
0169 static const cxl_p2n_reg_t CXL_PSL_PEHandle_An = {0x080};
0170 static const cxl_p2n_reg_t CXL_PSL_ErrStat_An = {0x088};
0171 /* AFU Registers - CAIA 1&2 */
0172 static const cxl_p2n_reg_t CXL_AFU_Cntl_An    = {0x090};
0173 static const cxl_p2n_reg_t CXL_AFU_ERR_An     = {0x098};
0174 /* Work Element Descriptor - CAIA 1&2 */
0175 static const cxl_p2n_reg_t CXL_PSL_WED_An     = {0x0A0};
0176 /* 0x0C0:FFF Implementation Dependent Area */
0177 
0178 #define CXL_PSL_SPAP_Addr 0x0ffffffffffff000ULL
0179 #define CXL_PSL_SPAP_Size 0x0000000000000ff0ULL
0180 #define CXL_PSL_SPAP_Size_Shift 4
0181 #define CXL_PSL_SPAP_V    0x0000000000000001ULL
0182 
0183 /****** CXL_PSL_Control ****************************************************/
0184 #define CXL_PSL_Control_tb              (0x1ull << (63-63))
0185 #define CXL_PSL_Control_Fr              (0x1ull << (63-31))
0186 #define CXL_PSL_Control_Fs_MASK         (0x3ull << (63-29))
0187 #define CXL_PSL_Control_Fs_Complete     (0x3ull << (63-29))
0188 
0189 /****** CXL_PSL_DLCNTL *****************************************************/
0190 #define CXL_PSL_DLCNTL_D (0x1ull << (63-28))
0191 #define CXL_PSL_DLCNTL_C (0x1ull << (63-29))
0192 #define CXL_PSL_DLCNTL_E (0x1ull << (63-30))
0193 #define CXL_PSL_DLCNTL_S (0x1ull << (63-31))
0194 #define CXL_PSL_DLCNTL_CE (CXL_PSL_DLCNTL_C | CXL_PSL_DLCNTL_E)
0195 #define CXL_PSL_DLCNTL_DCES (CXL_PSL_DLCNTL_D | CXL_PSL_DLCNTL_CE | CXL_PSL_DLCNTL_S)
0196 
0197 /****** CXL_PSL_SR_An ******************************************************/
0198 #define CXL_PSL_SR_An_SF  MSR_SF            /* 64bit */
0199 #define CXL_PSL_SR_An_TA  (1ull << (63-1))  /* Tags active,   GA1: 0 */
0200 #define CXL_PSL_SR_An_HV  MSR_HV            /* Hypervisor,    GA1: 0 */
0201 #define CXL_PSL_SR_An_XLAT_hpt (0ull << (63-6))/* Hashed page table (HPT) mode */
0202 #define CXL_PSL_SR_An_XLAT_roh (2ull << (63-6))/* Radix on HPT mode */
0203 #define CXL_PSL_SR_An_XLAT_ror (3ull << (63-6))/* Radix on Radix mode */
0204 #define CXL_PSL_SR_An_BOT (1ull << (63-10)) /* Use the in-memory segment table */
0205 #define CXL_PSL_SR_An_PR  MSR_PR            /* Problem state, GA1: 1 */
0206 #define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */
0207 #define CXL_PSL_SR_An_TC  (1ull << (63-54)) /* Page Table secondary hash */
0208 #define CXL_PSL_SR_An_US  (1ull << (63-56)) /* User state,    GA1: X */
0209 #define CXL_PSL_SR_An_SC  (1ull << (63-58)) /* Segment Table secondary hash */
0210 #define CXL_PSL_SR_An_R   MSR_DR            /* Relocate,      GA1: 1 */
0211 #define CXL_PSL_SR_An_MP  (1ull << (63-62)) /* Master Process */
0212 #define CXL_PSL_SR_An_LE  (1ull << (63-63)) /* Little Endian */
0213 
0214 /****** CXL_PSL_ID_An ****************************************************/
0215 #define CXL_PSL_ID_An_F (1ull << (63-31))
0216 #define CXL_PSL_ID_An_L (1ull << (63-30))
0217 
0218 /****** CXL_PSL_SERR_An ****************************************************/
0219 #define CXL_PSL_SERR_An_afuto   (1ull << (63-0))
0220 #define CXL_PSL_SERR_An_afudis  (1ull << (63-1))
0221 #define CXL_PSL_SERR_An_afuov   (1ull << (63-2))
0222 #define CXL_PSL_SERR_An_badsrc  (1ull << (63-3))
0223 #define CXL_PSL_SERR_An_badctx  (1ull << (63-4))
0224 #define CXL_PSL_SERR_An_llcmdis (1ull << (63-5))
0225 #define CXL_PSL_SERR_An_llcmdto (1ull << (63-6))
0226 #define CXL_PSL_SERR_An_afupar  (1ull << (63-7))
0227 #define CXL_PSL_SERR_An_afudup  (1ull << (63-8))
0228 #define CXL_PSL_SERR_An_IRQS    ( \
0229     CXL_PSL_SERR_An_afuto | CXL_PSL_SERR_An_afudis | CXL_PSL_SERR_An_afuov | \
0230     CXL_PSL_SERR_An_badsrc | CXL_PSL_SERR_An_badctx | CXL_PSL_SERR_An_llcmdis | \
0231     CXL_PSL_SERR_An_llcmdto | CXL_PSL_SERR_An_afupar | CXL_PSL_SERR_An_afudup)
0232 #define CXL_PSL_SERR_An_afuto_mask  (1ull << (63-32))
0233 #define CXL_PSL_SERR_An_afudis_mask (1ull << (63-33))
0234 #define CXL_PSL_SERR_An_afuov_mask  (1ull << (63-34))
0235 #define CXL_PSL_SERR_An_badsrc_mask (1ull << (63-35))
0236 #define CXL_PSL_SERR_An_badctx_mask (1ull << (63-36))
0237 #define CXL_PSL_SERR_An_llcmdis_mask    (1ull << (63-37))
0238 #define CXL_PSL_SERR_An_llcmdto_mask    (1ull << (63-38))
0239 #define CXL_PSL_SERR_An_afupar_mask (1ull << (63-39))
0240 #define CXL_PSL_SERR_An_afudup_mask (1ull << (63-40))
0241 #define CXL_PSL_SERR_An_IRQ_MASKS   ( \
0242     CXL_PSL_SERR_An_afuto_mask | CXL_PSL_SERR_An_afudis_mask | CXL_PSL_SERR_An_afuov_mask | \
0243     CXL_PSL_SERR_An_badsrc_mask | CXL_PSL_SERR_An_badctx_mask | CXL_PSL_SERR_An_llcmdis_mask | \
0244     CXL_PSL_SERR_An_llcmdto_mask | CXL_PSL_SERR_An_afupar_mask | CXL_PSL_SERR_An_afudup_mask)
0245 
0246 #define CXL_PSL_SERR_An_AE  (1ull << (63-30))
0247 
0248 /****** CXL_PSL_SCNTL_An ****************************************************/
0249 #define CXL_PSL_SCNTL_An_CR          (0x1ull << (63-15))
0250 /* Programming Modes: */
0251 #define CXL_PSL_SCNTL_An_PM_MASK     (0xffffull << (63-31))
0252 #define CXL_PSL_SCNTL_An_PM_Shared   (0x0000ull << (63-31))
0253 #define CXL_PSL_SCNTL_An_PM_OS       (0x0001ull << (63-31))
0254 #define CXL_PSL_SCNTL_An_PM_Process  (0x0002ull << (63-31))
0255 #define CXL_PSL_SCNTL_An_PM_AFU      (0x0004ull << (63-31))
0256 #define CXL_PSL_SCNTL_An_PM_AFU_PBT  (0x0104ull << (63-31))
0257 /* Purge Status (ro) */
0258 #define CXL_PSL_SCNTL_An_Ps_MASK     (0x3ull << (63-39))
0259 #define CXL_PSL_SCNTL_An_Ps_Pending  (0x1ull << (63-39))
0260 #define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39))
0261 /* Purge */
0262 #define CXL_PSL_SCNTL_An_Pc          (0x1ull << (63-48))
0263 /* Suspend Status (ro) */
0264 #define CXL_PSL_SCNTL_An_Ss_MASK     (0x3ull << (63-55))
0265 #define CXL_PSL_SCNTL_An_Ss_Pending  (0x1ull << (63-55))
0266 #define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55))
0267 /* Suspend Control */
0268 #define CXL_PSL_SCNTL_An_Sc          (0x1ull << (63-63))
0269 
0270 /* AFU Slice Enable Status (ro) */
0271 #define CXL_AFU_Cntl_An_ES_MASK     (0x7ull << (63-2))
0272 #define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2))
0273 #define CXL_AFU_Cntl_An_ES_Enabled  (0x4ull << (63-2))
0274 /* AFU Slice Enable */
0275 #define CXL_AFU_Cntl_An_E           (0x1ull << (63-3))
0276 /* AFU Slice Reset status (ro) */
0277 #define CXL_AFU_Cntl_An_RS_MASK     (0x3ull << (63-5))
0278 #define CXL_AFU_Cntl_An_RS_Pending  (0x1ull << (63-5))
0279 #define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5))
0280 /* AFU Slice Reset */
0281 #define CXL_AFU_Cntl_An_RA          (0x1ull << (63-7))
0282 
0283 /****** CXL_SSTP0/1_An ******************************************************/
0284 /* These top bits are for the segment that CONTAINS the segment table */
0285 #define CXL_SSTP0_An_B_SHIFT    SLB_VSID_SSIZE_SHIFT
0286 #define CXL_SSTP0_An_KS             (1ull << (63-2))
0287 #define CXL_SSTP0_An_KP             (1ull << (63-3))
0288 #define CXL_SSTP0_An_N              (1ull << (63-4))
0289 #define CXL_SSTP0_An_L              (1ull << (63-5))
0290 #define CXL_SSTP0_An_C              (1ull << (63-6))
0291 #define CXL_SSTP0_An_TA             (1ull << (63-7))
0292 #define CXL_SSTP0_An_LP_SHIFT                (63-9)  /* 2 Bits */
0293 /* And finally, the virtual address & size of the segment table: */
0294 #define CXL_SSTP0_An_SegTableSize_SHIFT      (63-31) /* 12 Bits */
0295 #define CXL_SSTP0_An_SegTableSize_MASK \
0296     (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT)
0297 #define CXL_SSTP0_An_STVA_U_MASK   ((1ull << (63-49))-1)
0298 #define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1))
0299 #define CXL_SSTP1_An_V              (1ull << (63-63))
0300 
0301 /****** CXL_PSL_SLBIE_[An] - CAIA 1 **************************************************/
0302 /* write: */
0303 #define CXL_SLBIE_C        PPC_BIT(36)         /* Class */
0304 #define CXL_SLBIE_SS       PPC_BITMASK(37, 38) /* Segment Size */
0305 #define CXL_SLBIE_SS_SHIFT PPC_BITLSHIFT(38)
0306 #define CXL_SLBIE_TA       PPC_BIT(38)         /* Tags Active */
0307 /* read: */
0308 #define CXL_SLBIE_MAX      PPC_BITMASK(24, 31)
0309 #define CXL_SLBIE_PENDING  PPC_BITMASK(56, 63)
0310 
0311 /****** Common to all CXL_TLBIA/SLBIA_[An] - CAIA 1 **********************************/
0312 #define CXL_TLB_SLB_P          (1ull) /* Pending (read) */
0313 
0314 /****** Common to all CXL_TLB/SLB_IA/IE_[An] registers - CAIA 1 **********************/
0315 #define CXL_TLB_SLB_IQ_ALL     (0ull) /* Inv qualifier */
0316 #define CXL_TLB_SLB_IQ_LPID    (1ull) /* Inv qualifier */
0317 #define CXL_TLB_SLB_IQ_LPIDPID (3ull) /* Inv qualifier */
0318 
0319 /****** CXL_PSL_AFUSEL ******************************************************/
0320 #define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */
0321 
0322 /****** CXL_PSL_DSISR_An - CAIA 1 ****************************************************/
0323 #define CXL_PSL_DSISR_An_DS (1ull << (63-0))  /* Segment not found */
0324 #define CXL_PSL_DSISR_An_DM (1ull << (63-1))  /* PTE not found (See also: M) or protection fault */
0325 #define CXL_PSL_DSISR_An_ST (1ull << (63-2))  /* Segment Table PTE not found */
0326 #define CXL_PSL_DSISR_An_UR (1ull << (63-3))  /* AURP PTE not found */
0327 #define CXL_PSL_DSISR_TRANS (CXL_PSL_DSISR_An_DS | CXL_PSL_DSISR_An_DM | CXL_PSL_DSISR_An_ST | CXL_PSL_DSISR_An_UR)
0328 #define CXL_PSL_DSISR_An_PE (1ull << (63-4))  /* PSL Error (implementation specific) */
0329 #define CXL_PSL_DSISR_An_AE (1ull << (63-5))  /* AFU Error */
0330 #define CXL_PSL_DSISR_An_OC (1ull << (63-6))  /* OS Context Warning */
0331 #define CXL_PSL_DSISR_PENDING (CXL_PSL_DSISR_TRANS | CXL_PSL_DSISR_An_PE | CXL_PSL_DSISR_An_AE | CXL_PSL_DSISR_An_OC)
0332 /* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */
0333 #define CXL_PSL_DSISR_An_M  DSISR_NOHPTE      /* PTE not found */
0334 #define CXL_PSL_DSISR_An_P  DSISR_PROTFAULT   /* Storage protection violation */
0335 #define CXL_PSL_DSISR_An_A  (1ull << (63-37)) /* AFU lock access to write through or cache inhibited storage */
0336 #define CXL_PSL_DSISR_An_S  DSISR_ISSTORE     /* Access was afu_wr or afu_zero */
0337 #define CXL_PSL_DSISR_An_K  DSISR_KEYFAULT    /* Access not permitted by virtual page class key protection */
0338 
0339 /****** CXL_PSL_DSISR_An - CAIA 2 ****************************************************/
0340 #define CXL_PSL9_DSISR_An_TF (1ull << (63-3))  /* Translation fault */
0341 #define CXL_PSL9_DSISR_An_PE (1ull << (63-4))  /* PSL Error (implementation specific) */
0342 #define CXL_PSL9_DSISR_An_AE (1ull << (63-5))  /* AFU Error */
0343 #define CXL_PSL9_DSISR_An_OC (1ull << (63-6))  /* OS Context Warning */
0344 #define CXL_PSL9_DSISR_An_S (1ull << (63-38))  /* TF for a write operation */
0345 #define CXL_PSL9_DSISR_PENDING (CXL_PSL9_DSISR_An_TF | CXL_PSL9_DSISR_An_PE | CXL_PSL9_DSISR_An_AE | CXL_PSL9_DSISR_An_OC)
0346 /*
0347  * NOTE: Bits 56:63 (Checkout Response Status) are valid when DSISR_An[TF] = 1
0348  * Status (0:7) Encoding
0349  */
0350 #define CXL_PSL9_DSISR_An_CO_MASK 0x00000000000000ffULL
0351 #define CXL_PSL9_DSISR_An_SF      0x0000000000000080ULL  /* Segment Fault                        0b10000000 */
0352 #define CXL_PSL9_DSISR_An_PF_SLR  0x0000000000000088ULL  /* PTE not found (Single Level Radix)   0b10001000 */
0353 #define CXL_PSL9_DSISR_An_PF_RGC  0x000000000000008CULL  /* PTE not found (Radix Guest (child))  0b10001100 */
0354 #define CXL_PSL9_DSISR_An_PF_RGP  0x0000000000000090ULL  /* PTE not found (Radix Guest (parent)) 0b10010000 */
0355 #define CXL_PSL9_DSISR_An_PF_HRH  0x0000000000000094ULL  /* PTE not found (HPT/Radix Host)       0b10010100 */
0356 #define CXL_PSL9_DSISR_An_PF_STEG 0x000000000000009CULL  /* PTE not found (STEG VA)              0b10011100 */
0357 #define CXL_PSL9_DSISR_An_URTCH   0x00000000000000B4ULL  /* Unsupported Radix Tree Configuration 0b10110100 */
0358 
0359 /****** CXL_PSL_TFC_An ******************************************************/
0360 #define CXL_PSL_TFC_An_A  (1ull << (63-28)) /* Acknowledge non-translation fault */
0361 #define CXL_PSL_TFC_An_C  (1ull << (63-29)) /* Continue (abort transaction) */
0362 #define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */
0363 #define CXL_PSL_TFC_An_R  (1ull << (63-31)) /* Restart PSL transaction */
0364 
0365 /****** CXL_PSL_DEBUG *****************************************************/
0366 #define CXL_PSL_DEBUG_CDC  (1ull << (63-27)) /* Coherent Data cache support */
0367 
0368 /****** CXL_XSL9_IERAT_ERAT - CAIA 2 **********************************/
0369 #define CXL_XSL9_IERAT_MLPID    (1ull << (63-0))  /* Match LPID */
0370 #define CXL_XSL9_IERAT_MPID     (1ull << (63-1))  /* Match PID */
0371 #define CXL_XSL9_IERAT_PRS      (1ull << (63-4))  /* PRS bit for Radix invalidations */
0372 #define CXL_XSL9_IERAT_INVR     (1ull << (63-3))  /* Invalidate Radix */
0373 #define CXL_XSL9_IERAT_IALL     (1ull << (63-8))  /* Invalidate All */
0374 #define CXL_XSL9_IERAT_IINPROG  (1ull << (63-63)) /* Invalidate in progress */
0375 
0376 /* cxl_process_element->software_status */
0377 #define CXL_PE_SOFTWARE_STATE_V (1ul << (31 -  0)) /* Valid */
0378 #define CXL_PE_SOFTWARE_STATE_C (1ul << (31 - 29)) /* Complete */
0379 #define CXL_PE_SOFTWARE_STATE_S (1ul << (31 - 30)) /* Suspend */
0380 #define CXL_PE_SOFTWARE_STATE_T (1ul << (31 - 31)) /* Terminate */
0381 
0382 /****** CXL_PSL_RXCTL_An (Implementation Specific) **************************
0383  * Controls AFU Hang Pulse, which sets the timeout for the AFU to respond to
0384  * the PSL for any response (except MMIO). Timeouts will occur between 1x to 2x
0385  * of the hang pulse frequency.
0386  */
0387 #define CXL_PSL_RXCTL_AFUHP_4S      0x7000000000000000ULL
0388 
0389 /* SPA->sw_command_status */
0390 #define CXL_SPA_SW_CMD_MASK         0xffff000000000000ULL
0391 #define CXL_SPA_SW_CMD_TERMINATE    0x0001000000000000ULL
0392 #define CXL_SPA_SW_CMD_REMOVE       0x0002000000000000ULL
0393 #define CXL_SPA_SW_CMD_SUSPEND      0x0003000000000000ULL
0394 #define CXL_SPA_SW_CMD_RESUME       0x0004000000000000ULL
0395 #define CXL_SPA_SW_CMD_ADD          0x0005000000000000ULL
0396 #define CXL_SPA_SW_CMD_UPDATE       0x0006000000000000ULL
0397 #define CXL_SPA_SW_STATE_MASK       0x0000ffff00000000ULL
0398 #define CXL_SPA_SW_STATE_TERMINATED 0x0000000100000000ULL
0399 #define CXL_SPA_SW_STATE_REMOVED    0x0000000200000000ULL
0400 #define CXL_SPA_SW_STATE_SUSPENDED  0x0000000300000000ULL
0401 #define CXL_SPA_SW_STATE_RESUMED    0x0000000400000000ULL
0402 #define CXL_SPA_SW_STATE_ADDED      0x0000000500000000ULL
0403 #define CXL_SPA_SW_STATE_UPDATED    0x0000000600000000ULL
0404 #define CXL_SPA_SW_PSL_ID_MASK      0x00000000ffff0000ULL
0405 #define CXL_SPA_SW_LINK_MASK        0x000000000000ffffULL
0406 
0407 #define CXL_MAX_SLICES 4
0408 #define MAX_AFU_MMIO_REGS 3
0409 
0410 #define CXL_MODE_TIME_SLICED 0x4
0411 #define CXL_SUPPORTED_MODES (CXL_MODE_DEDICATED | CXL_MODE_DIRECTED)
0412 
0413 #define CXL_DEV_MINORS 13   /* 1 control + 4 AFUs * 3 (dedicated/master/shared) */
0414 #define CXL_CARD_MINOR(adapter) (adapter->adapter_num * CXL_DEV_MINORS)
0415 #define CXL_DEVT_ADAPTER(dev) (MINOR(dev) / CXL_DEV_MINORS)
0416 
0417 #define CXL_PSL9_TRACEID_MAX 0xAU
0418 #define CXL_PSL9_TRACESTATE_FIN 0x3U
0419 
0420 enum cxl_context_status {
0421     CLOSED,
0422     OPENED,
0423     STARTED
0424 };
0425 
0426 enum prefault_modes {
0427     CXL_PREFAULT_NONE,
0428     CXL_PREFAULT_WED,
0429     CXL_PREFAULT_ALL,
0430 };
0431 
0432 enum cxl_attrs {
0433     CXL_ADAPTER_ATTRS,
0434     CXL_AFU_MASTER_ATTRS,
0435     CXL_AFU_ATTRS,
0436 };
0437 
0438 struct cxl_sste {
0439     __be64 esid_data;
0440     __be64 vsid_data;
0441 };
0442 
0443 #define to_cxl_adapter(d) container_of(d, struct cxl, dev)
0444 #define to_cxl_afu(d) container_of(d, struct cxl_afu, dev)
0445 
0446 struct cxl_afu_native {
0447     void __iomem *p1n_mmio;
0448     void __iomem *afu_desc_mmio;
0449     irq_hw_number_t psl_hwirq;
0450     unsigned int psl_virq;
0451     struct mutex spa_mutex;
0452     /*
0453      * Only the first part of the SPA is used for the process element
0454      * linked list. The only other part that software needs to worry about
0455      * is sw_command_status, which we store a separate pointer to.
0456      * Everything else in the SPA is only used by hardware
0457      */
0458     struct cxl_process_element *spa;
0459     __be64 *sw_command_status;
0460     unsigned int spa_size;
0461     int spa_order;
0462     int spa_max_procs;
0463     u64 pp_offset;
0464 };
0465 
0466 struct cxl_afu_guest {
0467     struct cxl_afu *parent;
0468     u64 handle;
0469     phys_addr_t p2n_phys;
0470     u64 p2n_size;
0471     int max_ints;
0472     bool handle_err;
0473     struct delayed_work work_err;
0474     int previous_state;
0475 };
0476 
0477 struct cxl_afu {
0478     struct cxl_afu_native *native;
0479     struct cxl_afu_guest *guest;
0480     irq_hw_number_t serr_hwirq;
0481     unsigned int serr_virq;
0482     char *psl_irq_name;
0483     char *err_irq_name;
0484     void __iomem *p2n_mmio;
0485     phys_addr_t psn_phys;
0486     u64 pp_size;
0487 
0488     struct cxl *adapter;
0489     struct device dev;
0490     struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d;
0491     struct device *chardev_s, *chardev_m, *chardev_d;
0492     struct idr contexts_idr;
0493     struct dentry *debugfs;
0494     struct mutex contexts_lock;
0495     spinlock_t afu_cntl_lock;
0496 
0497     /* -1: AFU deconfigured/locked, >= 0: number of readers */
0498     atomic_t configured_state;
0499 
0500     /* AFU error buffer fields and bin attribute for sysfs */
0501     u64 eb_len, eb_offset;
0502     struct bin_attribute attr_eb;
0503 
0504     /* pointer to the vphb */
0505     struct pci_controller *phb;
0506 
0507     int pp_irqs;
0508     int irqs_max;
0509     int num_procs;
0510     int max_procs_virtualised;
0511     int slice;
0512     int modes_supported;
0513     int current_mode;
0514     int crs_num;
0515     u64 crs_len;
0516     u64 crs_offset;
0517     struct list_head crs;
0518     enum prefault_modes prefault_mode;
0519     bool psa;
0520     bool pp_psa;
0521     bool enabled;
0522 };
0523 
0524 
0525 struct cxl_irq_name {
0526     struct list_head list;
0527     char *name;
0528 };
0529 
0530 struct irq_avail {
0531     irq_hw_number_t offset;
0532     irq_hw_number_t range;
0533     unsigned long   *bitmap;
0534 };
0535 
0536 /*
0537  * This is a cxl context.  If the PSL is in dedicated mode, there will be one
0538  * of these per AFU.  If in AFU directed there can be lots of these.
0539  */
0540 struct cxl_context {
0541     struct cxl_afu *afu;
0542 
0543     /* Problem state MMIO */
0544     phys_addr_t psn_phys;
0545     u64 psn_size;
0546 
0547     /* Used to unmap any mmaps when force detaching */
0548     struct address_space *mapping;
0549     struct mutex mapping_lock;
0550     struct page *ff_page;
0551     bool mmio_err_ff;
0552     bool kernelapi;
0553 
0554     spinlock_t sste_lock; /* Protects segment table entries */
0555     struct cxl_sste *sstp;
0556     u64 sstp0, sstp1;
0557     unsigned int sst_size, sst_lru;
0558 
0559     wait_queue_head_t wq;
0560     /* use mm context associated with this pid for ds faults */
0561     struct pid *pid;
0562     spinlock_t lock; /* Protects pending_irq_mask, pending_fault and fault_addr */
0563     /* Only used in PR mode */
0564     u64 process_token;
0565 
0566     /* driver private data */
0567     void *priv;
0568 
0569     unsigned long *irq_bitmap; /* Accessed from IRQ context */
0570     struct cxl_irq_ranges irqs;
0571     struct list_head irq_names;
0572     u64 fault_addr;
0573     u64 fault_dsisr;
0574     u64 afu_err;
0575 
0576     /*
0577      * This status and it's lock pretects start and detach context
0578      * from racing.  It also prevents detach from racing with
0579      * itself
0580      */
0581     enum cxl_context_status status;
0582     struct mutex status_mutex;
0583 
0584 
0585     /* XXX: Is it possible to need multiple work items at once? */
0586     struct work_struct fault_work;
0587     u64 dsisr;
0588     u64 dar;
0589 
0590     struct cxl_process_element *elem;
0591 
0592     /*
0593      * pe is the process element handle, assigned by this driver when the
0594      * context is initialized.
0595      *
0596      * external_pe is the PE shown outside of cxl.
0597      * On bare-metal, pe=external_pe, because we decide what the handle is.
0598      * In a guest, we only find out about the pe used by pHyp when the
0599      * context is attached, and that's the value we want to report outside
0600      * of cxl.
0601      */
0602     int pe;
0603     int external_pe;
0604 
0605     u32 irq_count;
0606     bool pe_inserted;
0607     bool master;
0608     bool kernel;
0609     bool pending_irq;
0610     bool pending_fault;
0611     bool pending_afu_err;
0612 
0613     /* Used by AFU drivers for driver specific event delivery */
0614     struct cxl_afu_driver_ops *afu_driver_ops;
0615     atomic_t afu_driver_events;
0616 
0617     struct rcu_head rcu;
0618 
0619     struct mm_struct *mm;
0620 
0621     u16 tidr;
0622     bool assign_tidr;
0623 };
0624 
0625 struct cxl_irq_info;
0626 
0627 struct cxl_service_layer_ops {
0628     int (*adapter_regs_init)(struct cxl *adapter, struct pci_dev *dev);
0629     int (*invalidate_all)(struct cxl *adapter);
0630     int (*afu_regs_init)(struct cxl_afu *afu);
0631     int (*sanitise_afu_regs)(struct cxl_afu *afu);
0632     int (*register_serr_irq)(struct cxl_afu *afu);
0633     void (*release_serr_irq)(struct cxl_afu *afu);
0634     irqreturn_t (*handle_interrupt)(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
0635     irqreturn_t (*fail_irq)(struct cxl_afu *afu, struct cxl_irq_info *irq_info);
0636     int (*activate_dedicated_process)(struct cxl_afu *afu);
0637     int (*attach_afu_directed)(struct cxl_context *ctx, u64 wed, u64 amr);
0638     int (*attach_dedicated_process)(struct cxl_context *ctx, u64 wed, u64 amr);
0639     void (*update_dedicated_ivtes)(struct cxl_context *ctx);
0640     void (*debugfs_add_adapter_regs)(struct cxl *adapter, struct dentry *dir);
0641     void (*debugfs_add_afu_regs)(struct cxl_afu *afu, struct dentry *dir);
0642     void (*psl_irq_dump_registers)(struct cxl_context *ctx);
0643     void (*err_irq_dump_registers)(struct cxl *adapter);
0644     void (*debugfs_stop_trace)(struct cxl *adapter);
0645     void (*write_timebase_ctrl)(struct cxl *adapter);
0646     u64 (*timebase_read)(struct cxl *adapter);
0647     int capi_mode;
0648     bool needs_reset_before_disable;
0649 };
0650 
0651 struct cxl_native {
0652     u64 afu_desc_off;
0653     u64 afu_desc_size;
0654     void __iomem *p1_mmio;
0655     void __iomem *p2_mmio;
0656     irq_hw_number_t err_hwirq;
0657     unsigned int err_virq;
0658     u64 ps_off;
0659     bool no_data_cache; /* set if no data cache on the card */
0660     const struct cxl_service_layer_ops *sl_ops;
0661 };
0662 
0663 struct cxl_guest {
0664     struct platform_device *pdev;
0665     int irq_nranges;
0666     struct cdev cdev;
0667     irq_hw_number_t irq_base_offset;
0668     struct irq_avail *irq_avail;
0669     spinlock_t irq_alloc_lock;
0670     u64 handle;
0671     char *status;
0672     u16 vendor;
0673     u16 device;
0674     u16 subsystem_vendor;
0675     u16 subsystem;
0676 };
0677 
0678 struct cxl {
0679     struct cxl_native *native;
0680     struct cxl_guest *guest;
0681     spinlock_t afu_list_lock;
0682     struct cxl_afu *afu[CXL_MAX_SLICES];
0683     struct device dev;
0684     struct dentry *trace;
0685     struct dentry *psl_err_chk;
0686     struct dentry *debugfs;
0687     char *irq_name;
0688     struct bin_attribute cxl_attr;
0689     int adapter_num;
0690     int user_irqs;
0691     u64 ps_size;
0692     u16 psl_rev;
0693     u16 base_image;
0694     u8 vsec_status;
0695     u8 caia_major;
0696     u8 caia_minor;
0697     u8 slices;
0698     bool user_image_loaded;
0699     bool perst_loads_image;
0700     bool perst_select_user;
0701     bool perst_same_image;
0702     bool psl_timebase_synced;
0703     bool tunneled_ops_supported;
0704 
0705     /*
0706      * number of contexts mapped on to this card. Possible values are:
0707      * >0: Number of contexts mapped and new one can be mapped.
0708      *  0: No active contexts and new ones can be mapped.
0709      * -1: No contexts mapped and new ones cannot be mapped.
0710      */
0711     atomic_t contexts_num;
0712 };
0713 
0714 int cxl_pci_alloc_one_irq(struct cxl *adapter);
0715 void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq);
0716 int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num);
0717 void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter);
0718 int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq);
0719 int cxl_update_image_control(struct cxl *adapter);
0720 int cxl_pci_reset(struct cxl *adapter);
0721 void cxl_pci_release_afu(struct device *dev);
0722 ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
0723 
0724 /* common == phyp + powernv - CAIA 1&2 */
0725 struct cxl_process_element_common {
0726     __be32 tid;
0727     __be32 pid;
0728     __be64 csrp;
0729     union {
0730         struct {
0731             __be64 aurp0;
0732             __be64 aurp1;
0733             __be64 sstp0;
0734             __be64 sstp1;
0735         } psl8;  /* CAIA 1 */
0736         struct {
0737             u8     reserved2[8];
0738             u8     reserved3[8];
0739             u8     reserved4[8];
0740             u8     reserved5[8];
0741         } psl9;  /* CAIA 2 */
0742     } u;
0743     __be64 amr;
0744     u8     reserved6[4];
0745     __be64 wed;
0746 } __packed;
0747 
0748 /* just powernv - CAIA 1&2 */
0749 struct cxl_process_element {
0750     __be64 sr;
0751     __be64 SPOffset;
0752     union {
0753         __be64 sdr;          /* CAIA 1 */
0754         u8     reserved1[8]; /* CAIA 2 */
0755     } u;
0756     __be64 haurp;
0757     __be32 ctxtime;
0758     __be16 ivte_offsets[4];
0759     __be16 ivte_ranges[4];
0760     __be32 lpid;
0761     struct cxl_process_element_common common;
0762     __be32 software_state;
0763 } __packed;
0764 
0765 static inline bool cxl_adapter_link_ok(struct cxl *cxl, struct cxl_afu *afu)
0766 {
0767     struct pci_dev *pdev;
0768 
0769     if (cpu_has_feature(CPU_FTR_HVMODE)) {
0770         pdev = to_pci_dev(cxl->dev.parent);
0771         return !pci_channel_offline(pdev);
0772     }
0773     return true;
0774 }
0775 
0776 static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg)
0777 {
0778     WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
0779     return cxl->native->p1_mmio + cxl_reg_off(reg);
0780 }
0781 
0782 static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val)
0783 {
0784     if (likely(cxl_adapter_link_ok(cxl, NULL)))
0785         out_be64(_cxl_p1_addr(cxl, reg), val);
0786 }
0787 
0788 static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg)
0789 {
0790     if (likely(cxl_adapter_link_ok(cxl, NULL)))
0791         return in_be64(_cxl_p1_addr(cxl, reg));
0792     else
0793         return ~0ULL;
0794 }
0795 
0796 static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg)
0797 {
0798     WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
0799     return afu->native->p1n_mmio + cxl_reg_off(reg);
0800 }
0801 
0802 static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val)
0803 {
0804     if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
0805         out_be64(_cxl_p1n_addr(afu, reg), val);
0806 }
0807 
0808 static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg)
0809 {
0810     if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
0811         return in_be64(_cxl_p1n_addr(afu, reg));
0812     else
0813         return ~0ULL;
0814 }
0815 
0816 static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg)
0817 {
0818     return afu->p2n_mmio + cxl_reg_off(reg);
0819 }
0820 
0821 static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val)
0822 {
0823     if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
0824         out_be64(_cxl_p2n_addr(afu, reg), val);
0825 }
0826 
0827 static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg)
0828 {
0829     if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
0830         return in_be64(_cxl_p2n_addr(afu, reg));
0831     else
0832         return ~0ULL;
0833 }
0834 
0835 static inline bool cxl_is_power8(void)
0836 {
0837     if ((pvr_version_is(PVR_POWER8E)) ||
0838         (pvr_version_is(PVR_POWER8NVL)) ||
0839         (pvr_version_is(PVR_POWER8)))
0840         return true;
0841     return false;
0842 }
0843 
0844 static inline bool cxl_is_power9(void)
0845 {
0846     if (pvr_version_is(PVR_POWER9))
0847         return true;
0848     return false;
0849 }
0850 
0851 ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
0852                 loff_t off, size_t count);
0853 
0854 
0855 struct cxl_calls {
0856     void (*cxl_slbia)(struct mm_struct *mm);
0857     struct module *owner;
0858 };
0859 int register_cxl_calls(struct cxl_calls *calls);
0860 void unregister_cxl_calls(struct cxl_calls *calls);
0861 int cxl_update_properties(struct device_node *dn, struct property *new_prop);
0862 
0863 void cxl_remove_adapter_nr(struct cxl *adapter);
0864 
0865 void cxl_release_spa(struct cxl_afu *afu);
0866 
0867 dev_t cxl_get_dev(void);
0868 int cxl_file_init(void);
0869 void cxl_file_exit(void);
0870 int cxl_register_adapter(struct cxl *adapter);
0871 int cxl_register_afu(struct cxl_afu *afu);
0872 int cxl_chardev_d_afu_add(struct cxl_afu *afu);
0873 int cxl_chardev_m_afu_add(struct cxl_afu *afu);
0874 int cxl_chardev_s_afu_add(struct cxl_afu *afu);
0875 void cxl_chardev_afu_remove(struct cxl_afu *afu);
0876 
0877 void cxl_context_detach_all(struct cxl_afu *afu);
0878 void cxl_context_free(struct cxl_context *ctx);
0879 void cxl_context_detach(struct cxl_context *ctx);
0880 
0881 int cxl_sysfs_adapter_add(struct cxl *adapter);
0882 void cxl_sysfs_adapter_remove(struct cxl *adapter);
0883 int cxl_sysfs_afu_add(struct cxl_afu *afu);
0884 void cxl_sysfs_afu_remove(struct cxl_afu *afu);
0885 int cxl_sysfs_afu_m_add(struct cxl_afu *afu);
0886 void cxl_sysfs_afu_m_remove(struct cxl_afu *afu);
0887 
0888 struct cxl *cxl_alloc_adapter(void);
0889 struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice);
0890 int cxl_afu_select_best_mode(struct cxl_afu *afu);
0891 
0892 int cxl_native_register_psl_irq(struct cxl_afu *afu);
0893 void cxl_native_release_psl_irq(struct cxl_afu *afu);
0894 int cxl_native_register_psl_err_irq(struct cxl *adapter);
0895 void cxl_native_release_psl_err_irq(struct cxl *adapter);
0896 int cxl_native_register_serr_irq(struct cxl_afu *afu);
0897 void cxl_native_release_serr_irq(struct cxl_afu *afu);
0898 int afu_register_irqs(struct cxl_context *ctx, u32 count);
0899 void afu_release_irqs(struct cxl_context *ctx, void *cookie);
0900 void afu_irq_name_free(struct cxl_context *ctx);
0901 
0902 int cxl_attach_afu_directed_psl9(struct cxl_context *ctx, u64 wed, u64 amr);
0903 int cxl_attach_afu_directed_psl8(struct cxl_context *ctx, u64 wed, u64 amr);
0904 int cxl_activate_dedicated_process_psl9(struct cxl_afu *afu);
0905 int cxl_activate_dedicated_process_psl8(struct cxl_afu *afu);
0906 int cxl_attach_dedicated_process_psl9(struct cxl_context *ctx, u64 wed, u64 amr);
0907 int cxl_attach_dedicated_process_psl8(struct cxl_context *ctx, u64 wed, u64 amr);
0908 void cxl_update_dedicated_ivtes_psl9(struct cxl_context *ctx);
0909 void cxl_update_dedicated_ivtes_psl8(struct cxl_context *ctx);
0910 
0911 #ifdef CONFIG_DEBUG_FS
0912 
0913 void cxl_debugfs_init(void);
0914 void cxl_debugfs_exit(void);
0915 void cxl_debugfs_adapter_add(struct cxl *adapter);
0916 void cxl_debugfs_adapter_remove(struct cxl *adapter);
0917 void cxl_debugfs_afu_add(struct cxl_afu *afu);
0918 void cxl_debugfs_afu_remove(struct cxl_afu *afu);
0919 void cxl_debugfs_add_adapter_regs_psl9(struct cxl *adapter, struct dentry *dir);
0920 void cxl_debugfs_add_adapter_regs_psl8(struct cxl *adapter, struct dentry *dir);
0921 void cxl_debugfs_add_afu_regs_psl9(struct cxl_afu *afu, struct dentry *dir);
0922 void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir);
0923 
0924 #else /* CONFIG_DEBUG_FS */
0925 
0926 static inline void __init cxl_debugfs_init(void)
0927 {
0928 }
0929 
0930 static inline void cxl_debugfs_exit(void)
0931 {
0932 }
0933 
0934 static inline void cxl_debugfs_adapter_add(struct cxl *adapter)
0935 {
0936 }
0937 
0938 static inline void cxl_debugfs_adapter_remove(struct cxl *adapter)
0939 {
0940 }
0941 
0942 static inline void cxl_debugfs_afu_add(struct cxl_afu *afu)
0943 {
0944 }
0945 
0946 static inline void cxl_debugfs_afu_remove(struct cxl_afu *afu)
0947 {
0948 }
0949 
0950 static inline void cxl_debugfs_add_adapter_regs_psl9(struct cxl *adapter,
0951                             struct dentry *dir)
0952 {
0953 }
0954 
0955 static inline void cxl_debugfs_add_adapter_regs_psl8(struct cxl *adapter,
0956                             struct dentry *dir)
0957 {
0958 }
0959 
0960 static inline void cxl_debugfs_add_afu_regs_psl9(struct cxl_afu *afu, struct dentry *dir)
0961 {
0962 }
0963 
0964 static inline void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir)
0965 {
0966 }
0967 
0968 #endif /* CONFIG_DEBUG_FS */
0969 
0970 void cxl_handle_fault(struct work_struct *work);
0971 void cxl_prefault(struct cxl_context *ctx, u64 wed);
0972 int cxl_handle_mm_fault(struct mm_struct *mm, u64 dsisr, u64 dar);
0973 
0974 struct cxl *get_cxl_adapter(int num);
0975 int cxl_alloc_sst(struct cxl_context *ctx);
0976 void cxl_dump_debug_buffer(void *addr, size_t size);
0977 
0978 void init_cxl_native(void);
0979 
0980 struct cxl_context *cxl_context_alloc(void);
0981 int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master);
0982 void cxl_context_set_mapping(struct cxl_context *ctx,
0983             struct address_space *mapping);
0984 void cxl_context_free(struct cxl_context *ctx);
0985 int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma);
0986 unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq,
0987              irq_handler_t handler, void *cookie, const char *name);
0988 void cxl_unmap_irq(unsigned int virq, void *cookie);
0989 int __detach_context(struct cxl_context *ctx);
0990 
0991 /*
0992  * This must match the layout of the H_COLLECT_CA_INT_INFO retbuf defined
0993  * in PAPR.
0994  * Field pid_tid is now 'reserved' because it's no more used on bare-metal.
0995  * On a guest environment, PSL_PID_An is located on the upper 32 bits and
0996  * PSL_TID_An register in the lower 32 bits.
0997  */
0998 struct cxl_irq_info {
0999     u64 dsisr;
1000     u64 dar;
1001     u64 dsr;
1002     u64 reserved;
1003     u64 afu_err;
1004     u64 errstat;
1005     u64 proc_handle;
1006     u64 padding[2]; /* to match the expected retbuf size for plpar_hcall9 */
1007 };
1008 
1009 void cxl_assign_psn_space(struct cxl_context *ctx);
1010 int cxl_invalidate_all_psl9(struct cxl *adapter);
1011 int cxl_invalidate_all_psl8(struct cxl *adapter);
1012 irqreturn_t cxl_irq_psl9(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
1013 irqreturn_t cxl_irq_psl8(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
1014 irqreturn_t cxl_fail_irq_psl(struct cxl_afu *afu, struct cxl_irq_info *irq_info);
1015 int cxl_register_one_irq(struct cxl *adapter, irq_handler_t handler,
1016             void *cookie, irq_hw_number_t *dest_hwirq,
1017             unsigned int *dest_virq, const char *name);
1018 
1019 int cxl_check_error(struct cxl_afu *afu);
1020 int cxl_afu_slbia(struct cxl_afu *afu);
1021 int cxl_data_cache_flush(struct cxl *adapter);
1022 int cxl_afu_disable(struct cxl_afu *afu);
1023 int cxl_psl_purge(struct cxl_afu *afu);
1024 int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
1025               u32 *phb_index, u64 *capp_unit_id);
1026 int cxl_slot_is_switched(struct pci_dev *dev);
1027 int cxl_get_xsl9_dsnctl(struct pci_dev *dev, u64 capp_unit_id, u64 *reg);
1028 u64 cxl_calculate_sr(bool master, bool kernel, bool real_mode, bool p9);
1029 
1030 void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx);
1031 void cxl_native_irq_dump_regs_psl8(struct cxl_context *ctx);
1032 void cxl_native_err_irq_dump_regs_psl8(struct cxl *adapter);
1033 void cxl_native_err_irq_dump_regs_psl9(struct cxl *adapter);
1034 int cxl_pci_vphb_add(struct cxl_afu *afu);
1035 void cxl_pci_vphb_remove(struct cxl_afu *afu);
1036 void cxl_release_mapping(struct cxl_context *ctx);
1037 
1038 extern struct pci_driver cxl_pci_driver;
1039 extern struct platform_driver cxl_of_driver;
1040 int afu_allocate_irqs(struct cxl_context *ctx, u32 count);
1041 
1042 int afu_open(struct inode *inode, struct file *file);
1043 int afu_release(struct inode *inode, struct file *file);
1044 long afu_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
1045 int afu_mmap(struct file *file, struct vm_area_struct *vm);
1046 __poll_t afu_poll(struct file *file, struct poll_table_struct *poll);
1047 ssize_t afu_read(struct file *file, char __user *buf, size_t count, loff_t *off);
1048 extern const struct file_operations afu_fops;
1049 
1050 struct cxl *cxl_guest_init_adapter(struct device_node *np, struct platform_device *dev);
1051 void cxl_guest_remove_adapter(struct cxl *adapter);
1052 int cxl_of_read_adapter_handle(struct cxl *adapter, struct device_node *np);
1053 int cxl_of_read_adapter_properties(struct cxl *adapter, struct device_node *np);
1054 ssize_t cxl_guest_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
1055 ssize_t cxl_guest_read_afu_vpd(struct cxl_afu *afu, void *buf, size_t len);
1056 int cxl_guest_init_afu(struct cxl *adapter, int slice, struct device_node *afu_np);
1057 void cxl_guest_remove_afu(struct cxl_afu *afu);
1058 int cxl_of_read_afu_handle(struct cxl_afu *afu, struct device_node *afu_np);
1059 int cxl_of_read_afu_properties(struct cxl_afu *afu, struct device_node *afu_np);
1060 int cxl_guest_add_chardev(struct cxl *adapter);
1061 void cxl_guest_remove_chardev(struct cxl *adapter);
1062 void cxl_guest_reload_module(struct cxl *adapter);
1063 int cxl_of_probe(struct platform_device *pdev);
1064 
1065 struct cxl_backend_ops {
1066     struct module *module;
1067     int (*adapter_reset)(struct cxl *adapter);
1068     int (*alloc_one_irq)(struct cxl *adapter);
1069     void (*release_one_irq)(struct cxl *adapter, int hwirq);
1070     int (*alloc_irq_ranges)(struct cxl_irq_ranges *irqs,
1071                 struct cxl *adapter, unsigned int num);
1072     void (*release_irq_ranges)(struct cxl_irq_ranges *irqs,
1073                 struct cxl *adapter);
1074     int (*setup_irq)(struct cxl *adapter, unsigned int hwirq,
1075             unsigned int virq);
1076     irqreturn_t (*handle_psl_slice_error)(struct cxl_context *ctx,
1077                     u64 dsisr, u64 errstat);
1078     irqreturn_t (*psl_interrupt)(int irq, void *data);
1079     int (*ack_irq)(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask);
1080     void (*irq_wait)(struct cxl_context *ctx);
1081     int (*attach_process)(struct cxl_context *ctx, bool kernel,
1082             u64 wed, u64 amr);
1083     int (*detach_process)(struct cxl_context *ctx);
1084     void (*update_ivtes)(struct cxl_context *ctx);
1085     bool (*support_attributes)(const char *attr_name, enum cxl_attrs type);
1086     bool (*link_ok)(struct cxl *cxl, struct cxl_afu *afu);
1087     void (*release_afu)(struct device *dev);
1088     ssize_t (*afu_read_err_buffer)(struct cxl_afu *afu, char *buf,
1089                 loff_t off, size_t count);
1090     int (*afu_check_and_enable)(struct cxl_afu *afu);
1091     int (*afu_activate_mode)(struct cxl_afu *afu, int mode);
1092     int (*afu_deactivate_mode)(struct cxl_afu *afu, int mode);
1093     int (*afu_reset)(struct cxl_afu *afu);
1094     int (*afu_cr_read8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 *val);
1095     int (*afu_cr_read16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 *val);
1096     int (*afu_cr_read32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 *val);
1097     int (*afu_cr_read64)(struct cxl_afu *afu, int cr_idx, u64 offset, u64 *val);
1098     int (*afu_cr_write8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 val);
1099     int (*afu_cr_write16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 val);
1100     int (*afu_cr_write32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 val);
1101     ssize_t (*read_adapter_vpd)(struct cxl *adapter, void *buf, size_t count);
1102 };
1103 extern const struct cxl_backend_ops cxl_native_ops;
1104 extern const struct cxl_backend_ops cxl_guest_ops;
1105 extern const struct cxl_backend_ops *cxl_ops;
1106 
1107 /* check if the given pci_dev is on the cxl vphb bus */
1108 bool cxl_pci_is_vphb_device(struct pci_dev *dev);
1109 
1110 /* decode AFU error bits in the PSL register PSL_SERR_An */
1111 void cxl_afu_decode_psl_serr(struct cxl_afu *afu, u64 serr);
1112 
1113 /*
1114  * Increments the number of attached contexts on an adapter.
1115  * In case an adapter_context_lock is taken the return -EBUSY.
1116  */
1117 int cxl_adapter_context_get(struct cxl *adapter);
1118 
1119 /* Decrements the number of attached contexts on an adapter */
1120 void cxl_adapter_context_put(struct cxl *adapter);
1121 
1122 /* If no active contexts then prevents contexts from being attached */
1123 int cxl_adapter_context_lock(struct cxl *adapter);
1124 
1125 /* Unlock the contexts-lock if taken. Warn and force unlock otherwise */
1126 void cxl_adapter_context_unlock(struct cxl *adapter);
1127 
1128 /* Increases the reference count to "struct mm_struct" */
1129 void cxl_context_mm_count_get(struct cxl_context *ctx);
1130 
1131 /* Decrements the reference count to "struct mm_struct" */
1132 void cxl_context_mm_count_put(struct cxl_context *ctx);
1133 
1134 #endif
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!