drivers/misc/cs5535-mfgpt.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Driver for the CS5535/CS5536 Multi-Function General Purpose Timers (MFGPT)
0004  *
0005  * Copyright (C) 2006, Advanced Micro Devices, Inc.
0006  * Copyright (C) 2007  Andres Salomon <dilinger@debian.org>
0007  * Copyright (C) 2009  Andres Salomon <dilinger@collabora.co.uk>
0008  *
0009  * The MFGPTs are documented in AMD Geode CS5536 Companion Device Data Book.
0010  */
0011
0012 #include <linux/kernel.h>
0013 #include <linux/spinlock.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/module.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/cs5535.h>
0018 #include <linux/slab.h>
0019
0020 #define DRV_NAME "cs5535-mfgpt"
0021
0022 static int mfgpt_reset_timers;
0023 module_param_named(mfgptfix, mfgpt_reset_timers, int, 0644);
0024 MODULE_PARM_DESC(mfgptfix, "Try to reset the MFGPT timers during init; "
0025         "required by some broken BIOSes (ie, TinyBIOS < 0.99) or kexec "
0026         "(1 = reset the MFGPT using an undocumented bit, "
0027         "2 = perform a soft reset by unconfiguring all timers); "
0028         "use what works best for you.");
0029
0030 struct cs5535_mfgpt_timer {
0031     struct cs5535_mfgpt_chip *chip;
0032     int nr;
0033 };
0034
0035 static struct cs5535_mfgpt_chip {
0036     DECLARE_BITMAP(avail, MFGPT_MAX_TIMERS);
0037     resource_size_t base;
0038
0039     struct platform_device *pdev;
0040     spinlock_t lock;
0041     int initialized;
0042 } cs5535_mfgpt_chip;
0043
0044 int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp,
0045         int event, int enable)
0046 {
0047     uint32_t msr, mask, value, dummy;
0048     int shift = (cmp == MFGPT_CMP1) ? 0 : 8;
0049
0050     if (!timer) {
0051         WARN_ON(1);
0052         return -EIO;
0053     }
0054
0055     /*
0056      * The register maps for these are described in sections 6.17.1.x of
0057      * the AMD Geode CS5536 Companion Device Data Book.
0058      */
0059     switch (event) {
0060     case MFGPT_EVENT_RESET:
0061         /*
0062          * XXX: According to the docs, we cannot reset timers above
0063          * 6; that is, resets for 7 and 8 will be ignored.  Is this
0064          * a problem?   -dilinger
0065          */
0066         msr = MSR_MFGPT_NR;
0067         mask = 1 << (timer->nr + 24);
0068         break;
0069
0070     case MFGPT_EVENT_NMI:
0071         msr = MSR_MFGPT_NR;
0072         mask = 1 << (timer->nr + shift);
0073         break;
0074
0075     case MFGPT_EVENT_IRQ:
0076         msr = MSR_MFGPT_IRQ;
0077         mask = 1 << (timer->nr + shift);
0078         break;
0079
0080     default:
0081         return -EIO;
0082     }
0083
0084     rdmsr(msr, value, dummy);
0085
0086     if (enable)
0087         value |= mask;
0088     else
0089         value &= ~mask;
0090
0091     wrmsr(msr, value, dummy);
0092     return 0;
0093 }
0094 EXPORT_SYMBOL_GPL(cs5535_mfgpt_toggle_event);
0095
0096 int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp, int *irq,
0097         int enable)
0098 {
0099     uint32_t zsel, lpc, dummy;
0100     int shift;
0101
0102     if (!timer) {
0103         WARN_ON(1);
0104         return -EIO;
0105     }
0106
0107     /*
0108      * Unfortunately, MFGPTs come in pairs sharing their IRQ lines. If VSA
0109      * is using the same CMP of the timer's Siamese twin, the IRQ is set to
0110      * 2, and we mustn't use nor change it.
0111      * XXX: Likewise, 2 Linux drivers might clash if the 2nd overwrites the
0112      * IRQ of the 1st. This can only happen if forcing an IRQ, calling this
0113      * with *irq==0 is safe. Currently there _are_ no 2 drivers.
0114      */
0115     rdmsr(MSR_PIC_ZSEL_LOW, zsel, dummy);
0116     shift = ((cmp == MFGPT_CMP1 ? 0 : 4) + timer->nr % 4) * 4;
0117     if (((zsel >> shift) & 0xF) == 2)
0118         return -EIO;
0119
0120     /* Choose IRQ: if none supplied, keep IRQ already set or use default */
0121     if (!*irq)
0122         *irq = (zsel >> shift) & 0xF;
0123     if (!*irq)
0124         *irq = CONFIG_CS5535_MFGPT_DEFAULT_IRQ;
0125
0126     /* Can't use IRQ if it's 0 (=disabled), 2, or routed to LPC */
0127     if (*irq < 1 || *irq == 2 || *irq > 15)
0128         return -EIO;
0129     rdmsr(MSR_PIC_IRQM_LPC, lpc, dummy);
0130     if (lpc & (1 << *irq))
0131         return -EIO;
0132
0133     /* All chosen and checked - go for it */
0134     if (cs5535_mfgpt_toggle_event(timer, cmp, MFGPT_EVENT_IRQ, enable))
0135         return -EIO;
0136     if (enable) {
0137         zsel = (zsel & ~(0xF << shift)) | (*irq << shift);
0138         wrmsr(MSR_PIC_ZSEL_LOW, zsel, dummy);
0139     }
0140
0141     return 0;
0142 }
0143 EXPORT_SYMBOL_GPL(cs5535_mfgpt_set_irq);
0144
0145 struct cs5535_mfgpt_timer *cs5535_mfgpt_alloc_timer(int timer_nr, int domain)
0146 {
0147     struct cs5535_mfgpt_chip *mfgpt = &cs5535_mfgpt_chip;
0148     struct cs5535_mfgpt_timer *timer = NULL;
0149     unsigned long flags;
0150     int max;
0151
0152     if (!mfgpt->initialized)
0153         goto done;
0154
0155     /* only allocate timers from the working domain if requested */
0156     if (domain == MFGPT_DOMAIN_WORKING)
0157         max = 6;
0158     else
0159         max = MFGPT_MAX_TIMERS;
0160
0161     if (timer_nr >= max) {
0162         /* programmer error.  silly programmers! */
0163         WARN_ON(1);
0164         goto done;
0165     }
0166
0167     spin_lock_irqsave(&mfgpt->lock, flags);
0168     if (timer_nr < 0) {
0169         unsigned long t;
0170
0171         /* try to find any available timer */
0172         t = find_first_bit(mfgpt->avail, max);
0173         /* set timer_nr to -1 if no timers available */
0174         timer_nr = t < max ? (int) t : -1;
0175     } else {
0176         /* check if the requested timer's available */
0177         if (!test_bit(timer_nr, mfgpt->avail))
0178             timer_nr = -1;
0179     }
0180
0181     if (timer_nr >= 0)
0182         /* if timer_nr is not -1, it's an available timer */
0183         __clear_bit(timer_nr, mfgpt->avail);
0184     spin_unlock_irqrestore(&mfgpt->lock, flags);
0185
0186     if (timer_nr < 0)
0187         goto done;
0188
0189     timer = kmalloc(sizeof(*timer), GFP_KERNEL);
0190     if (!timer) {
0191         /* aw hell */
0192         spin_lock_irqsave(&mfgpt->lock, flags);
0193         __set_bit(timer_nr, mfgpt->avail);
0194         spin_unlock_irqrestore(&mfgpt->lock, flags);
0195         goto done;
0196     }
0197     timer->chip = mfgpt;
0198     timer->nr = timer_nr;
0199     dev_info(&mfgpt->pdev->dev, "registered timer %d\n", timer_nr);
0200
0201 done:
0202     return timer;
0203 }
0204 EXPORT_SYMBOL_GPL(cs5535_mfgpt_alloc_timer);
0205
0206 /*
0207  * XXX: This frees the timer memory, but never resets the actual hardware
0208  * timer.  The old geode_mfgpt code did this; it would be good to figure
0209  * out a way to actually release the hardware timer.  See comments below.
0210  */
0211 void cs5535_mfgpt_free_timer(struct cs5535_mfgpt_timer *timer)
0212 {
0213     unsigned long flags;
0214     uint16_t val;
0215
0216     /* timer can be made available again only if never set up */
0217     val = cs5535_mfgpt_read(timer, MFGPT_REG_SETUP);
0218     if (!(val & MFGPT_SETUP_SETUP)) {
0219         spin_lock_irqsave(&timer->chip->lock, flags);
0220         __set_bit(timer->nr, timer->chip->avail);
0221         spin_unlock_irqrestore(&timer->chip->lock, flags);
0222     }
0223
0224     kfree(timer);
0225 }
0226 EXPORT_SYMBOL_GPL(cs5535_mfgpt_free_timer);
0227
0228 uint16_t cs5535_mfgpt_read(struct cs5535_mfgpt_timer *timer, uint16_t reg)
0229 {
0230     return inw(timer->chip->base + reg + (timer->nr * 8));
0231 }
0232 EXPORT_SYMBOL_GPL(cs5535_mfgpt_read);
0233
0234 void cs5535_mfgpt_write(struct cs5535_mfgpt_timer *timer, uint16_t reg,
0235         uint16_t value)
0236 {
0237     outw(value, timer->chip->base + reg + (timer->nr * 8));
0238 }
0239 EXPORT_SYMBOL_GPL(cs5535_mfgpt_write);
0240
0241 /*
0242  * This is a sledgehammer that resets all MFGPT timers. This is required by
0243  * some broken BIOSes which leave the system in an unstable state
0244  * (TinyBIOS 0.98, for example; fixed in 0.99).  It's uncertain as to
0245  * whether or not this secret MSR can be used to release individual timers.
0246  * Jordan tells me that he and Mitch once played w/ it, but it's unclear
0247  * what the results of that were (and they experienced some instability).
0248  */
0249 static void reset_all_timers(void)
0250 {
0251     uint32_t val, dummy;
0252
0253     /* The following undocumented bit resets the MFGPT timers */
0254     val = 0xFF; dummy = 0;
0255     wrmsr(MSR_MFGPT_SETUP, val, dummy);
0256 }
0257
0258 /*
0259  * This is another sledgehammer to reset all MFGPT timers.
0260  * Instead of using the undocumented bit method it clears
0261  * IRQ, NMI and RESET settings.
0262  */
0263 static void soft_reset(void)
0264 {
0265     int i;
0266     struct cs5535_mfgpt_timer t;
0267
0268     for (i = 0; i < MFGPT_MAX_TIMERS; i++) {
0269         t.nr = i;
0270
0271         cs5535_mfgpt_toggle_event(&t, MFGPT_CMP1, MFGPT_EVENT_RESET, 0);
0272         cs5535_mfgpt_toggle_event(&t, MFGPT_CMP2, MFGPT_EVENT_RESET, 0);
0273         cs5535_mfgpt_toggle_event(&t, MFGPT_CMP1, MFGPT_EVENT_NMI, 0);
0274         cs5535_mfgpt_toggle_event(&t, MFGPT_CMP2, MFGPT_EVENT_NMI, 0);
0275         cs5535_mfgpt_toggle_event(&t, MFGPT_CMP1, MFGPT_EVENT_IRQ, 0);
0276         cs5535_mfgpt_toggle_event(&t, MFGPT_CMP2, MFGPT_EVENT_IRQ, 0);
0277     }
0278 }
0279
0280 /*
0281  * Check whether any MFGPTs are available for the kernel to use.  In most
0282  * cases, firmware that uses AMD's VSA code will claim all timers during
0283  * bootup; we certainly don't want to take them if they're already in use.
0284  * In other cases (such as with VSAless OpenFirmware), the system firmware
0285  * leaves timers available for us to use.
0286  */
0287 static int scan_timers(struct cs5535_mfgpt_chip *mfgpt)
0288 {
0289     struct cs5535_mfgpt_timer timer = { .chip = mfgpt };
0290     unsigned long flags;
0291     int timers = 0;
0292     uint16_t val;
0293     int i;
0294
0295     /* bios workaround */
0296     if (mfgpt_reset_timers == 1)
0297         reset_all_timers();
0298     else if (mfgpt_reset_timers == 2)
0299         soft_reset();
0300
0301     /* just to be safe, protect this section w/ lock */
0302     spin_lock_irqsave(&mfgpt->lock, flags);
0303     for (i = 0; i < MFGPT_MAX_TIMERS; i++) {
0304         timer.nr = i;
0305         val = cs5535_mfgpt_read(&timer, MFGPT_REG_SETUP);
0306         if (!(val & MFGPT_SETUP_SETUP) || mfgpt_reset_timers == 2) {
0307             __set_bit(i, mfgpt->avail);
0308             timers++;
0309         }
0310     }
0311     spin_unlock_irqrestore(&mfgpt->lock, flags);
0312
0313     return timers;
0314 }
0315
0316 static int cs5535_mfgpt_probe(struct platform_device *pdev)
0317 {
0318     struct resource *res;
0319     int err = -EIO, t;
0320
0321     if (mfgpt_reset_timers < 0 || mfgpt_reset_timers > 2) {
0322         dev_err(&pdev->dev, "Bad mfgpt_reset_timers value: %i\n",
0323             mfgpt_reset_timers);
0324         goto done;
0325     }
0326
0327     /* There are two ways to get the MFGPT base address; one is by
0328      * fetching it from MSR_LBAR_MFGPT, the other is by reading the
0329      * PCI BAR info.  The latter method is easier (especially across
0330      * different architectures), so we'll stick with that for now.  If
0331      * it turns out to be unreliable in the face of crappy BIOSes, we
0332      * can always go back to using MSRs.. */
0333
0334     res = platform_get_resource(pdev, IORESOURCE_IO, 0);
0335     if (!res) {
0336         dev_err(&pdev->dev, "can't fetch device resource info\n");
0337         goto done;
0338     }
0339
0340     if (!request_region(res->start, resource_size(res), pdev->name)) {
0341         dev_err(&pdev->dev, "can't request region\n");
0342         goto done;
0343     }
0344
0345     /* set up the driver-specific struct */
0346     cs5535_mfgpt_chip.base = res->start;
0347     cs5535_mfgpt_chip.pdev = pdev;
0348     spin_lock_init(&cs5535_mfgpt_chip.lock);
0349
0350     dev_info(&pdev->dev, "reserved resource region %pR\n", res);
0351
0352     /* detect the available timers */
0353     t = scan_timers(&cs5535_mfgpt_chip);
0354     dev_info(&pdev->dev, "%d MFGPT timers available\n", t);
0355     cs5535_mfgpt_chip.initialized = 1;
0356     return 0;
0357
0358 done:
0359     return err;
0360 }
0361
0362 static struct platform_driver cs5535_mfgpt_driver = {
0363     .driver = {
0364         .name = DRV_NAME,
0365     },
0366     .probe = cs5535_mfgpt_probe,
0367 };
0368
0369
0370 static int __init cs5535_mfgpt_init(void)
0371 {
0372     return platform_driver_register(&cs5535_mfgpt_driver);
0373 }
0374
0375 module_init(cs5535_mfgpt_init);
0376
0377 MODULE_AUTHOR("Andres Salomon <dilinger@queued.net>");
0378 MODULE_DESCRIPTION("CS5535/CS5536 MFGPT timer driver");
0379 MODULE_LICENSE("GPL");
0380 MODULE_ALIAS("platform:" DRV_NAME);