misc/cardreader/rtsx_pcr.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /* Driver for Realtek PCI-Express card reader
0003  *
0004  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
0005  *
0006  * Author:
0007  *   Wei WANG <wei_wang@realsil.com.cn>
0008  */
0009
0010 #ifndef __RTSX_PCR_H
0011 #define __RTSX_PCR_H
0012
0013 #include <linux/rtsx_pci.h>
0014
0015 #define MIN_DIV_N_PCR       80
0016 #define MAX_DIV_N_PCR       208
0017
0018 #define RTS522A_PME_FORCE_CTL   0xFF78
0019 #define RTS522A_AUTOLOAD_CFG1   0xFF7C
0020 #define RTS522A_PM_CTRL3        0xFF7E
0021
0022 #define RTS524A_PME_FORCE_CTL       0xFF78
0023 #define REG_EFUSE_BYPASS        0x08
0024 #define REG_EFUSE_POR           0x04
0025 #define REG_EFUSE_POWER_MASK        0x03
0026 #define REG_EFUSE_POWERON       0x03
0027 #define REG_EFUSE_POWEROFF      0x00
0028 #define RTS5250_CLK_CFG3        0xFF79
0029 #define RTS525A_CFG_MEM_PD      0xF0
0030 #define RTS524A_AUTOLOAD_CFG1       0xFF7C
0031 #define RTS524A_PM_CTRL3        0xFF7E
0032 #define RTS525A_BIOS_CFG        0xFF2D
0033 #define RTS525A_LOAD_BIOS_FLAG  0x01
0034 #define RTS525A_CLEAR_BIOS_FLAG 0x00
0035
0036 #define RTS525A_EFUSE_CTL       0xFC32
0037 #define REG_EFUSE_ENABLE        0x80
0038 #define REG_EFUSE_MODE          0x40
0039 #define RTS525A_EFUSE_ADD       0xFC33
0040 #define REG_EFUSE_ADD_MASK      0x3F
0041 #define RTS525A_EFUSE_DATA      0xFC35
0042
0043 #define LTR_ACTIVE_LATENCY_DEF      0x883C
0044 #define LTR_IDLE_LATENCY_DEF        0x892C
0045 #define LTR_L1OFF_LATENCY_DEF       0x9003
0046 #define L1_SNOOZE_DELAY_DEF     1
0047 #define LTR_L1OFF_SSPWRGATE_5249_DEF        0xAF
0048 #define LTR_L1OFF_SSPWRGATE_5250_DEF        0xFF
0049 #define LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF 0xAC
0050 #define LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF 0xF8
0051 #define CMD_TIMEOUT_DEF     100
0052 #define MASK_8_BIT_DEF      0xFF
0053
0054 #define SSC_CLOCK_STABLE_WAIT   130
0055
0056 #define RTS524A_OCP_THD_800 0x04
0057 #define RTS525A_OCP_THD_800 0x05
0058 #define RTS522A_OCP_THD_800 0x06
0059
0060
0061 int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
0062 int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
0063
0064 void rts5209_init_params(struct rtsx_pcr *pcr);
0065 void rts5229_init_params(struct rtsx_pcr *pcr);
0066 void rtl8411_init_params(struct rtsx_pcr *pcr);
0067 void rtl8402_init_params(struct rtsx_pcr *pcr);
0068 void rts5227_init_params(struct rtsx_pcr *pcr);
0069 void rts522a_init_params(struct rtsx_pcr *pcr);
0070 void rts5249_init_params(struct rtsx_pcr *pcr);
0071 void rts524a_init_params(struct rtsx_pcr *pcr);
0072 void rts525a_init_params(struct rtsx_pcr *pcr);
0073 void rtl8411b_init_params(struct rtsx_pcr *pcr);
0074 void rts5260_init_params(struct rtsx_pcr *pcr);
0075 void rts5261_init_params(struct rtsx_pcr *pcr);
0076 void rts5228_init_params(struct rtsx_pcr *pcr);
0077
0078 static inline u8 map_sd_drive(int idx)
0079 {
0080     u8 sd_drive[4] = {
0081         0x01,   /* Type D */
0082         0x02,   /* Type C */
0083         0x05,   /* Type A */
0084         0x03    /* Type B */
0085     };
0086
0087     return sd_drive[idx];
0088 }
0089
0090 #define rtsx_vendor_setting_valid(reg)      (!((reg) & 0x1000000))
0091 #define rts5209_vendor_setting1_valid(reg)  (!((reg) & 0x80))
0092 #define rts5209_vendor_setting2_valid(reg)  ((reg) & 0x80)
0093
0094 #define rtsx_check_mmc_support(reg)     ((reg) & 0x10)
0095 #define rtsx_reg_to_rtd3(reg)               ((reg) & 0x02)
0096 #define rtsx_reg_to_rtd3_uhsii(reg)             ((reg) & 0x04)
0097 #define rtsx_reg_to_aspm(reg)           (((reg) >> 28) & 0x03)
0098 #define rtsx_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 26) & 0x03)
0099 #define rtsx_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 5) & 0x03)
0100 #define rtsx_reg_to_card_drive_sel(reg)     ((((reg) >> 25) & 0x01) << 6)
0101 #define rtsx_reg_check_reverse_socket(reg)  ((reg) & 0x4000)
0102 #define rts5209_reg_to_aspm(reg)        (((reg) >> 5) & 0x03)
0103 #define rts5209_reg_check_ms_pmos(reg)      (!((reg) & 0x08))
0104 #define rts5209_reg_to_sd30_drive_sel_1v8(reg)  (((reg) >> 3) & 0x07)
0105 #define rts5209_reg_to_sd30_drive_sel_3v3(reg)  ((reg) & 0x07)
0106 #define rts5209_reg_to_card_drive_sel(reg)  ((reg) >> 8)
0107 #define rtl8411_reg_to_sd30_drive_sel_3v3(reg)  (((reg) >> 5) & 0x07)
0108 #define rtl8411b_reg_to_sd30_drive_sel_3v3(reg) ((reg) & 0x03)
0109
0110 #define set_pull_ctrl_tables(pcr, __device)             \
0111 do {                                    \
0112     pcr->sd_pull_ctl_enable_tbl  = __device##_sd_pull_ctl_enable_tbl;  \
0113     pcr->sd_pull_ctl_disable_tbl = __device##_sd_pull_ctl_disable_tbl; \
0114     pcr->ms_pull_ctl_enable_tbl  = __device##_ms_pull_ctl_enable_tbl;  \
0115     pcr->ms_pull_ctl_disable_tbl = __device##_ms_pull_ctl_disable_tbl; \
0116 } while (0)
0117
0118 /* generic operations */
0119 int rtsx_gops_pm_reset(struct rtsx_pcr *pcr);
0120 int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency);
0121 int rtsx_set_l1off_sub(struct rtsx_pcr *pcr, u8 val);
0122 void rtsx_pci_init_ocp(struct rtsx_pcr *pcr);
0123 void rtsx_pci_disable_ocp(struct rtsx_pcr *pcr);
0124 void rtsx_pci_enable_ocp(struct rtsx_pcr *pcr);
0125 int rtsx_pci_get_ocpstat(struct rtsx_pcr *pcr, u8 *val);
0126 void rtsx_pci_clear_ocpstat(struct rtsx_pcr *pcr);
0127 void rtsx_pci_enable_oobs_polling(struct rtsx_pcr *pcr);
0128 void rtsx_pci_disable_oobs_polling(struct rtsx_pcr *pcr);
0129 int rtsx_sd_power_off_card3v3(struct rtsx_pcr *pcr);
0130 int rtsx_ms_power_off_card3v3(struct rtsx_pcr *pcr);
0131
0132 #endif