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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /* Driver for Realtek PCI-Express card reader
0003  *
0004  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
0005  *
0006  * Author:
0007  *   Wei WANG <wei_wang@realsil.com.cn>
0008  */
0009 
0010 #include <linux/pci.h>
0011 #include <linux/module.h>
0012 #include <linux/slab.h>
0013 #include <linux/dma-mapping.h>
0014 #include <linux/highmem.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/delay.h>
0017 #include <linux/idr.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/mfd/core.h>
0020 #include <linux/rtsx_pci.h>
0021 #include <linux/mmc/card.h>
0022 #include <asm/unaligned.h>
0023 #include <linux/pm.h>
0024 #include <linux/pm_runtime.h>
0025 
0026 #include "rtsx_pcr.h"
0027 #include "rts5261.h"
0028 #include "rts5228.h"
0029 
0030 static bool msi_en = true;
0031 module_param(msi_en, bool, S_IRUGO | S_IWUSR);
0032 MODULE_PARM_DESC(msi_en, "Enable MSI");
0033 
0034 static DEFINE_IDR(rtsx_pci_idr);
0035 static DEFINE_SPINLOCK(rtsx_pci_lock);
0036 
0037 static struct mfd_cell rtsx_pcr_cells[] = {
0038     [RTSX_SD_CARD] = {
0039         .name = DRV_NAME_RTSX_PCI_SDMMC,
0040     },
0041 };
0042 
0043 static const struct pci_device_id rtsx_pci_ids[] = {
0044     { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
0045     { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
0046     { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
0047     { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 },
0048     { PCI_DEVICE(0x10EC, 0x522A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
0049     { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
0050     { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
0051     { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
0052     { PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
0053     { PCI_DEVICE(0x10EC, 0x525A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
0054     { PCI_DEVICE(0x10EC, 0x5260), PCI_CLASS_OTHERS << 16, 0xFF0000 },
0055     { PCI_DEVICE(0x10EC, 0x5261), PCI_CLASS_OTHERS << 16, 0xFF0000 },
0056     { PCI_DEVICE(0x10EC, 0x5228), PCI_CLASS_OTHERS << 16, 0xFF0000 },
0057     { 0, }
0058 };
0059 
0060 MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
0061 
0062 static int rtsx_comm_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency)
0063 {
0064     rtsx_pci_write_register(pcr, MSGTXDATA0,
0065                 MASK_8_BIT_DEF, (u8) (latency & 0xFF));
0066     rtsx_pci_write_register(pcr, MSGTXDATA1,
0067                 MASK_8_BIT_DEF, (u8)((latency >> 8) & 0xFF));
0068     rtsx_pci_write_register(pcr, MSGTXDATA2,
0069                 MASK_8_BIT_DEF, (u8)((latency >> 16) & 0xFF));
0070     rtsx_pci_write_register(pcr, MSGTXDATA3,
0071                 MASK_8_BIT_DEF, (u8)((latency >> 24) & 0xFF));
0072     rtsx_pci_write_register(pcr, LTR_CTL, LTR_TX_EN_MASK |
0073         LTR_LATENCY_MODE_MASK, LTR_TX_EN_1 | LTR_LATENCY_MODE_SW);
0074 
0075     return 0;
0076 }
0077 
0078 int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency)
0079 {
0080     return rtsx_comm_set_ltr_latency(pcr, latency);
0081 }
0082 
0083 static void rtsx_comm_set_aspm(struct rtsx_pcr *pcr, bool enable)
0084 {
0085     if (pcr->aspm_enabled == enable)
0086         return;
0087 
0088     if (pcr->aspm_mode == ASPM_MODE_CFG) {
0089         pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
0090                         PCI_EXP_LNKCTL_ASPMC,
0091                         enable ? pcr->aspm_en : 0);
0092     } else if (pcr->aspm_mode == ASPM_MODE_REG) {
0093         if (pcr->aspm_en & 0x02)
0094             rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, FORCE_ASPM_CTL0 |
0095                 FORCE_ASPM_CTL1, enable ? 0 : FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1);
0096         else
0097             rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, FORCE_ASPM_CTL0 |
0098                 FORCE_ASPM_CTL1, FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1);
0099     }
0100 
0101     if (!enable && (pcr->aspm_en & 0x02))
0102         mdelay(10);
0103 
0104     pcr->aspm_enabled = enable;
0105 }
0106 
0107 static void rtsx_disable_aspm(struct rtsx_pcr *pcr)
0108 {
0109     if (pcr->ops->set_aspm)
0110         pcr->ops->set_aspm(pcr, false);
0111     else
0112         rtsx_comm_set_aspm(pcr, false);
0113 }
0114 
0115 int rtsx_set_l1off_sub(struct rtsx_pcr *pcr, u8 val)
0116 {
0117     rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, val);
0118 
0119     return 0;
0120 }
0121 
0122 static void rtsx_set_l1off_sub_cfg_d0(struct rtsx_pcr *pcr, int active)
0123 {
0124     if (pcr->ops->set_l1off_cfg_sub_d0)
0125         pcr->ops->set_l1off_cfg_sub_d0(pcr, active);
0126 }
0127 
0128 static void rtsx_comm_pm_full_on(struct rtsx_pcr *pcr)
0129 {
0130     struct rtsx_cr_option *option = &pcr->option;
0131 
0132     rtsx_disable_aspm(pcr);
0133 
0134     /* Fixes DMA transfer timeout issue after disabling ASPM on RTS5260 */
0135     msleep(1);
0136 
0137     if (option->ltr_enabled)
0138         rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
0139 
0140     if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN))
0141         rtsx_set_l1off_sub_cfg_d0(pcr, 1);
0142 }
0143 
0144 static void rtsx_pm_full_on(struct rtsx_pcr *pcr)
0145 {
0146     rtsx_comm_pm_full_on(pcr);
0147 }
0148 
0149 void rtsx_pci_start_run(struct rtsx_pcr *pcr)
0150 {
0151     /* If pci device removed, don't queue idle work any more */
0152     if (pcr->remove_pci)
0153         return;
0154 
0155     if (pcr->state != PDEV_STAT_RUN) {
0156         pcr->state = PDEV_STAT_RUN;
0157         if (pcr->ops->enable_auto_blink)
0158             pcr->ops->enable_auto_blink(pcr);
0159         rtsx_pm_full_on(pcr);
0160     }
0161 }
0162 EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
0163 
0164 int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
0165 {
0166     int i;
0167     u32 val = HAIMR_WRITE_START;
0168 
0169     val |= (u32)(addr & 0x3FFF) << 16;
0170     val |= (u32)mask << 8;
0171     val |= (u32)data;
0172 
0173     rtsx_pci_writel(pcr, RTSX_HAIMR, val);
0174 
0175     for (i = 0; i < MAX_RW_REG_CNT; i++) {
0176         val = rtsx_pci_readl(pcr, RTSX_HAIMR);
0177         if ((val & HAIMR_TRANS_END) == 0) {
0178             if (data != (u8)val)
0179                 return -EIO;
0180             return 0;
0181         }
0182     }
0183 
0184     return -ETIMEDOUT;
0185 }
0186 EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
0187 
0188 int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
0189 {
0190     u32 val = HAIMR_READ_START;
0191     int i;
0192 
0193     val |= (u32)(addr & 0x3FFF) << 16;
0194     rtsx_pci_writel(pcr, RTSX_HAIMR, val);
0195 
0196     for (i = 0; i < MAX_RW_REG_CNT; i++) {
0197         val = rtsx_pci_readl(pcr, RTSX_HAIMR);
0198         if ((val & HAIMR_TRANS_END) == 0)
0199             break;
0200     }
0201 
0202     if (i >= MAX_RW_REG_CNT)
0203         return -ETIMEDOUT;
0204 
0205     if (data)
0206         *data = (u8)(val & 0xFF);
0207 
0208     return 0;
0209 }
0210 EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
0211 
0212 int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
0213 {
0214     int err, i, finished = 0;
0215     u8 tmp;
0216 
0217     rtsx_pci_write_register(pcr, PHYDATA0, 0xFF, (u8)val);
0218     rtsx_pci_write_register(pcr, PHYDATA1, 0xFF, (u8)(val >> 8));
0219     rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr);
0220     rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x81);
0221 
0222     for (i = 0; i < 100000; i++) {
0223         err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
0224         if (err < 0)
0225             return err;
0226 
0227         if (!(tmp & 0x80)) {
0228             finished = 1;
0229             break;
0230         }
0231     }
0232 
0233     if (!finished)
0234         return -ETIMEDOUT;
0235 
0236     return 0;
0237 }
0238 
0239 int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
0240 {
0241     if (pcr->ops->write_phy)
0242         return pcr->ops->write_phy(pcr, addr, val);
0243 
0244     return __rtsx_pci_write_phy_register(pcr, addr, val);
0245 }
0246 EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
0247 
0248 int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
0249 {
0250     int err, i, finished = 0;
0251     u16 data;
0252     u8 tmp, val1, val2;
0253 
0254     rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr);
0255     rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x80);
0256 
0257     for (i = 0; i < 100000; i++) {
0258         err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
0259         if (err < 0)
0260             return err;
0261 
0262         if (!(tmp & 0x80)) {
0263             finished = 1;
0264             break;
0265         }
0266     }
0267 
0268     if (!finished)
0269         return -ETIMEDOUT;
0270 
0271     rtsx_pci_read_register(pcr, PHYDATA0, &val1);
0272     rtsx_pci_read_register(pcr, PHYDATA1, &val2);
0273     data = val1 | (val2 << 8);
0274 
0275     if (val)
0276         *val = data;
0277 
0278     return 0;
0279 }
0280 
0281 int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
0282 {
0283     if (pcr->ops->read_phy)
0284         return pcr->ops->read_phy(pcr, addr, val);
0285 
0286     return __rtsx_pci_read_phy_register(pcr, addr, val);
0287 }
0288 EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
0289 
0290 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
0291 {
0292     if (pcr->ops->stop_cmd)
0293         return pcr->ops->stop_cmd(pcr);
0294 
0295     rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
0296     rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
0297 
0298     rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
0299     rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
0300 }
0301 EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
0302 
0303 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
0304         u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
0305 {
0306     unsigned long flags;
0307     u32 val = 0;
0308     u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
0309 
0310     val |= (u32)(cmd_type & 0x03) << 30;
0311     val |= (u32)(reg_addr & 0x3FFF) << 16;
0312     val |= (u32)mask << 8;
0313     val |= (u32)data;
0314 
0315     spin_lock_irqsave(&pcr->lock, flags);
0316     ptr += pcr->ci;
0317     if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
0318         put_unaligned_le32(val, ptr);
0319         ptr++;
0320         pcr->ci++;
0321     }
0322     spin_unlock_irqrestore(&pcr->lock, flags);
0323 }
0324 EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
0325 
0326 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
0327 {
0328     u32 val = 1 << 31;
0329 
0330     rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
0331 
0332     val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
0333     /* Hardware Auto Response */
0334     val |= 0x40000000;
0335     rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
0336 }
0337 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
0338 
0339 int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
0340 {
0341     struct completion trans_done;
0342     u32 val = 1 << 31;
0343     long timeleft;
0344     unsigned long flags;
0345     int err = 0;
0346 
0347     spin_lock_irqsave(&pcr->lock, flags);
0348 
0349     /* set up data structures for the wakeup system */
0350     pcr->done = &trans_done;
0351     pcr->trans_result = TRANS_NOT_READY;
0352     init_completion(&trans_done);
0353 
0354     rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
0355 
0356     val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
0357     /* Hardware Auto Response */
0358     val |= 0x40000000;
0359     rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
0360 
0361     spin_unlock_irqrestore(&pcr->lock, flags);
0362 
0363     /* Wait for TRANS_OK_INT */
0364     timeleft = wait_for_completion_interruptible_timeout(
0365             &trans_done, msecs_to_jiffies(timeout));
0366     if (timeleft <= 0) {
0367         pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
0368         err = -ETIMEDOUT;
0369         goto finish_send_cmd;
0370     }
0371 
0372     spin_lock_irqsave(&pcr->lock, flags);
0373     if (pcr->trans_result == TRANS_RESULT_FAIL)
0374         err = -EINVAL;
0375     else if (pcr->trans_result == TRANS_RESULT_OK)
0376         err = 0;
0377     else if (pcr->trans_result == TRANS_NO_DEVICE)
0378         err = -ENODEV;
0379     spin_unlock_irqrestore(&pcr->lock, flags);
0380 
0381 finish_send_cmd:
0382     spin_lock_irqsave(&pcr->lock, flags);
0383     pcr->done = NULL;
0384     spin_unlock_irqrestore(&pcr->lock, flags);
0385 
0386     if ((err < 0) && (err != -ENODEV))
0387         rtsx_pci_stop_cmd(pcr);
0388 
0389     if (pcr->finish_me)
0390         complete(pcr->finish_me);
0391 
0392     return err;
0393 }
0394 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
0395 
0396 static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
0397         dma_addr_t addr, unsigned int len, int end)
0398 {
0399     u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
0400     u64 val;
0401     u8 option = RTSX_SG_VALID | RTSX_SG_TRANS_DATA;
0402 
0403     pcr_dbg(pcr, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr, len);
0404 
0405     if (end)
0406         option |= RTSX_SG_END;
0407 
0408     if ((PCI_PID(pcr) == PID_5261) || (PCI_PID(pcr) == PID_5228)) {
0409         if (len > 0xFFFF)
0410             val = ((u64)addr << 32) | (((u64)len & 0xFFFF) << 16)
0411                 | (((u64)len >> 16) << 6) | option;
0412         else
0413             val = ((u64)addr << 32) | ((u64)len << 16) | option;
0414     } else {
0415         val = ((u64)addr << 32) | ((u64)len << 12) | option;
0416     }
0417     put_unaligned_le64(val, ptr);
0418     pcr->sgi++;
0419 }
0420 
0421 int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
0422         int num_sg, bool read, int timeout)
0423 {
0424     int err = 0, count;
0425 
0426     pcr_dbg(pcr, "--> %s: num_sg = %d\n", __func__, num_sg);
0427     count = rtsx_pci_dma_map_sg(pcr, sglist, num_sg, read);
0428     if (count < 1)
0429         return -EINVAL;
0430     pcr_dbg(pcr, "DMA mapping count: %d\n", count);
0431 
0432     err = rtsx_pci_dma_transfer(pcr, sglist, count, read, timeout);
0433 
0434     rtsx_pci_dma_unmap_sg(pcr, sglist, num_sg, read);
0435 
0436     return err;
0437 }
0438 EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
0439 
0440 int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
0441         int num_sg, bool read)
0442 {
0443     enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
0444 
0445     if (pcr->remove_pci)
0446         return -EINVAL;
0447 
0448     if ((sglist == NULL) || (num_sg <= 0))
0449         return -EINVAL;
0450 
0451     return dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dir);
0452 }
0453 EXPORT_SYMBOL_GPL(rtsx_pci_dma_map_sg);
0454 
0455 void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
0456         int num_sg, bool read)
0457 {
0458     enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
0459 
0460     dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dir);
0461 }
0462 EXPORT_SYMBOL_GPL(rtsx_pci_dma_unmap_sg);
0463 
0464 int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
0465         int count, bool read, int timeout)
0466 {
0467     struct completion trans_done;
0468     struct scatterlist *sg;
0469     dma_addr_t addr;
0470     long timeleft;
0471     unsigned long flags;
0472     unsigned int len;
0473     int i, err = 0;
0474     u32 val;
0475     u8 dir = read ? DEVICE_TO_HOST : HOST_TO_DEVICE;
0476 
0477     if (pcr->remove_pci)
0478         return -ENODEV;
0479 
0480     if ((sglist == NULL) || (count < 1))
0481         return -EINVAL;
0482 
0483     val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
0484     pcr->sgi = 0;
0485     for_each_sg(sglist, sg, count, i) {
0486         addr = sg_dma_address(sg);
0487         len = sg_dma_len(sg);
0488         rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
0489     }
0490 
0491     spin_lock_irqsave(&pcr->lock, flags);
0492 
0493     pcr->done = &trans_done;
0494     pcr->trans_result = TRANS_NOT_READY;
0495     init_completion(&trans_done);
0496     rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
0497     rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
0498 
0499     spin_unlock_irqrestore(&pcr->lock, flags);
0500 
0501     timeleft = wait_for_completion_interruptible_timeout(
0502             &trans_done, msecs_to_jiffies(timeout));
0503     if (timeleft <= 0) {
0504         pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
0505         err = -ETIMEDOUT;
0506         goto out;
0507     }
0508 
0509     spin_lock_irqsave(&pcr->lock, flags);
0510     if (pcr->trans_result == TRANS_RESULT_FAIL) {
0511         err = -EILSEQ;
0512         if (pcr->dma_error_count < RTS_MAX_TIMES_FREQ_REDUCTION)
0513             pcr->dma_error_count++;
0514     }
0515 
0516     else if (pcr->trans_result == TRANS_NO_DEVICE)
0517         err = -ENODEV;
0518     spin_unlock_irqrestore(&pcr->lock, flags);
0519 
0520 out:
0521     spin_lock_irqsave(&pcr->lock, flags);
0522     pcr->done = NULL;
0523     spin_unlock_irqrestore(&pcr->lock, flags);
0524 
0525     if ((err < 0) && (err != -ENODEV))
0526         rtsx_pci_stop_cmd(pcr);
0527 
0528     if (pcr->finish_me)
0529         complete(pcr->finish_me);
0530 
0531     return err;
0532 }
0533 EXPORT_SYMBOL_GPL(rtsx_pci_dma_transfer);
0534 
0535 int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
0536 {
0537     int err;
0538     int i, j;
0539     u16 reg;
0540     u8 *ptr;
0541 
0542     if (buf_len > 512)
0543         buf_len = 512;
0544 
0545     ptr = buf;
0546     reg = PPBUF_BASE2;
0547     for (i = 0; i < buf_len / 256; i++) {
0548         rtsx_pci_init_cmd(pcr);
0549 
0550         for (j = 0; j < 256; j++)
0551             rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
0552 
0553         err = rtsx_pci_send_cmd(pcr, 250);
0554         if (err < 0)
0555             return err;
0556 
0557         memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
0558         ptr += 256;
0559     }
0560 
0561     if (buf_len % 256) {
0562         rtsx_pci_init_cmd(pcr);
0563 
0564         for (j = 0; j < buf_len % 256; j++)
0565             rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
0566 
0567         err = rtsx_pci_send_cmd(pcr, 250);
0568         if (err < 0)
0569             return err;
0570     }
0571 
0572     memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
0573 
0574     return 0;
0575 }
0576 EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
0577 
0578 int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
0579 {
0580     int err;
0581     int i, j;
0582     u16 reg;
0583     u8 *ptr;
0584 
0585     if (buf_len > 512)
0586         buf_len = 512;
0587 
0588     ptr = buf;
0589     reg = PPBUF_BASE2;
0590     for (i = 0; i < buf_len / 256; i++) {
0591         rtsx_pci_init_cmd(pcr);
0592 
0593         for (j = 0; j < 256; j++) {
0594             rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
0595                     reg++, 0xFF, *ptr);
0596             ptr++;
0597         }
0598 
0599         err = rtsx_pci_send_cmd(pcr, 250);
0600         if (err < 0)
0601             return err;
0602     }
0603 
0604     if (buf_len % 256) {
0605         rtsx_pci_init_cmd(pcr);
0606 
0607         for (j = 0; j < buf_len % 256; j++) {
0608             rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
0609                     reg++, 0xFF, *ptr);
0610             ptr++;
0611         }
0612 
0613         err = rtsx_pci_send_cmd(pcr, 250);
0614         if (err < 0)
0615             return err;
0616     }
0617 
0618     return 0;
0619 }
0620 EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
0621 
0622 static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
0623 {
0624     rtsx_pci_init_cmd(pcr);
0625 
0626     while (*tbl & 0xFFFF0000) {
0627         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
0628                 (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
0629         tbl++;
0630     }
0631 
0632     return rtsx_pci_send_cmd(pcr, 100);
0633 }
0634 
0635 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
0636 {
0637     const u32 *tbl;
0638 
0639     if (card == RTSX_SD_CARD)
0640         tbl = pcr->sd_pull_ctl_enable_tbl;
0641     else if (card == RTSX_MS_CARD)
0642         tbl = pcr->ms_pull_ctl_enable_tbl;
0643     else
0644         return -EINVAL;
0645 
0646     return rtsx_pci_set_pull_ctl(pcr, tbl);
0647 }
0648 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
0649 
0650 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
0651 {
0652     const u32 *tbl;
0653 
0654     if (card == RTSX_SD_CARD)
0655         tbl = pcr->sd_pull_ctl_disable_tbl;
0656     else if (card == RTSX_MS_CARD)
0657         tbl = pcr->ms_pull_ctl_disable_tbl;
0658     else
0659         return -EINVAL;
0660 
0661     return rtsx_pci_set_pull_ctl(pcr, tbl);
0662 }
0663 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
0664 
0665 static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
0666 {
0667     struct rtsx_hw_param *hw_param = &pcr->hw_param;
0668 
0669     pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN
0670         | hw_param->interrupt_en;
0671 
0672     if (pcr->num_slots > 1)
0673         pcr->bier |= MS_INT_EN;
0674 
0675     /* Enable Bus Interrupt */
0676     rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
0677 
0678     pcr_dbg(pcr, "RTSX_BIER: 0x%08x\n", pcr->bier);
0679 }
0680 
0681 static inline u8 double_ssc_depth(u8 depth)
0682 {
0683     return ((depth > 1) ? (depth - 1) : depth);
0684 }
0685 
0686 static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
0687 {
0688     if (div > CLK_DIV_1) {
0689         if (ssc_depth > (div - 1))
0690             ssc_depth -= (div - 1);
0691         else
0692             ssc_depth = SSC_DEPTH_4M;
0693     }
0694 
0695     return ssc_depth;
0696 }
0697 
0698 int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
0699         u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
0700 {
0701     int err, clk;
0702     u8 n, clk_divider, mcu_cnt, div;
0703     static const u8 depth[] = {
0704         [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
0705         [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
0706         [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
0707         [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
0708         [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
0709     };
0710 
0711     if (PCI_PID(pcr) == PID_5261)
0712         return rts5261_pci_switch_clock(pcr, card_clock,
0713                 ssc_depth, initial_mode, double_clk, vpclk);
0714     if (PCI_PID(pcr) == PID_5228)
0715         return rts5228_pci_switch_clock(pcr, card_clock,
0716                 ssc_depth, initial_mode, double_clk, vpclk);
0717 
0718     if (initial_mode) {
0719         /* We use 250k(around) here, in initial stage */
0720         clk_divider = SD_CLK_DIVIDE_128;
0721         card_clock = 30000000;
0722     } else {
0723         clk_divider = SD_CLK_DIVIDE_0;
0724     }
0725     err = rtsx_pci_write_register(pcr, SD_CFG1,
0726             SD_CLK_DIVIDE_MASK, clk_divider);
0727     if (err < 0)
0728         return err;
0729 
0730     /* Reduce card clock by 20MHz each time a DMA transfer error occurs */
0731     if (card_clock == UHS_SDR104_MAX_DTR &&
0732         pcr->dma_error_count &&
0733         PCI_PID(pcr) == RTS5227_DEVICE_ID)
0734         card_clock = UHS_SDR104_MAX_DTR -
0735             (pcr->dma_error_count * 20000000);
0736 
0737     card_clock /= 1000000;
0738     pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
0739 
0740     clk = card_clock;
0741     if (!initial_mode && double_clk)
0742         clk = card_clock * 2;
0743     pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
0744         clk, pcr->cur_clock);
0745 
0746     if (clk == pcr->cur_clock)
0747         return 0;
0748 
0749     if (pcr->ops->conv_clk_and_div_n)
0750         n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
0751     else
0752         n = (u8)(clk - 2);
0753     if ((clk <= 2) || (n > MAX_DIV_N_PCR))
0754         return -EINVAL;
0755 
0756     mcu_cnt = (u8)(125/clk + 3);
0757     if (mcu_cnt > 15)
0758         mcu_cnt = 15;
0759 
0760     /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
0761     div = CLK_DIV_1;
0762     while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) {
0763         if (pcr->ops->conv_clk_and_div_n) {
0764             int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
0765                     DIV_N_TO_CLK) * 2;
0766             n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
0767                     CLK_TO_DIV_N);
0768         } else {
0769             n = (n + 2) * 2 - 2;
0770         }
0771         div++;
0772     }
0773     pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
0774 
0775     ssc_depth = depth[ssc_depth];
0776     if (double_clk)
0777         ssc_depth = double_ssc_depth(ssc_depth);
0778 
0779     ssc_depth = revise_ssc_depth(ssc_depth, div);
0780     pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
0781 
0782     rtsx_pci_init_cmd(pcr);
0783     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
0784             CLK_LOW_FREQ, CLK_LOW_FREQ);
0785     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
0786             0xFF, (div << 4) | mcu_cnt);
0787     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
0788     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
0789             SSC_DEPTH_MASK, ssc_depth);
0790     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
0791     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
0792     if (vpclk) {
0793         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
0794                 PHASE_NOT_RESET, 0);
0795         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
0796                 PHASE_NOT_RESET, PHASE_NOT_RESET);
0797     }
0798 
0799     err = rtsx_pci_send_cmd(pcr, 2000);
0800     if (err < 0)
0801         return err;
0802 
0803     /* Wait SSC clock stable */
0804     udelay(SSC_CLOCK_STABLE_WAIT);
0805     err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
0806     if (err < 0)
0807         return err;
0808 
0809     pcr->cur_clock = clk;
0810     return 0;
0811 }
0812 EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
0813 
0814 int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
0815 {
0816     if (pcr->ops->card_power_on)
0817         return pcr->ops->card_power_on(pcr, card);
0818 
0819     return 0;
0820 }
0821 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
0822 
0823 int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
0824 {
0825     if (pcr->ops->card_power_off)
0826         return pcr->ops->card_power_off(pcr, card);
0827 
0828     return 0;
0829 }
0830 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
0831 
0832 int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card)
0833 {
0834     static const unsigned int cd_mask[] = {
0835         [RTSX_SD_CARD] = SD_EXIST,
0836         [RTSX_MS_CARD] = MS_EXIST
0837     };
0838 
0839     if (!(pcr->flags & PCR_MS_PMOS)) {
0840         /* When using single PMOS, accessing card is not permitted
0841          * if the existing card is not the designated one.
0842          */
0843         if (pcr->card_exist & (~cd_mask[card]))
0844             return -EIO;
0845     }
0846 
0847     return 0;
0848 }
0849 EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check);
0850 
0851 int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
0852 {
0853     if (pcr->ops->switch_output_voltage)
0854         return pcr->ops->switch_output_voltage(pcr, voltage);
0855 
0856     return 0;
0857 }
0858 EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage);
0859 
0860 unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
0861 {
0862     unsigned int val;
0863 
0864     val = rtsx_pci_readl(pcr, RTSX_BIPR);
0865     if (pcr->ops->cd_deglitch)
0866         val = pcr->ops->cd_deglitch(pcr);
0867 
0868     return val;
0869 }
0870 EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
0871 
0872 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
0873 {
0874     struct completion finish;
0875 
0876     pcr->finish_me = &finish;
0877     init_completion(&finish);
0878 
0879     if (pcr->done)
0880         complete(pcr->done);
0881 
0882     if (!pcr->remove_pci)
0883         rtsx_pci_stop_cmd(pcr);
0884 
0885     wait_for_completion_interruptible_timeout(&finish,
0886             msecs_to_jiffies(2));
0887     pcr->finish_me = NULL;
0888 }
0889 EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
0890 
0891 static void rtsx_pci_card_detect(struct work_struct *work)
0892 {
0893     struct delayed_work *dwork;
0894     struct rtsx_pcr *pcr;
0895     unsigned long flags;
0896     unsigned int card_detect = 0, card_inserted, card_removed;
0897     u32 irq_status;
0898 
0899     dwork = to_delayed_work(work);
0900     pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
0901 
0902     pcr_dbg(pcr, "--> %s\n", __func__);
0903 
0904     mutex_lock(&pcr->pcr_mutex);
0905     spin_lock_irqsave(&pcr->lock, flags);
0906 
0907     irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
0908     pcr_dbg(pcr, "irq_status: 0x%08x\n", irq_status);
0909 
0910     irq_status &= CARD_EXIST;
0911     card_inserted = pcr->card_inserted & irq_status;
0912     card_removed = pcr->card_removed;
0913     pcr->card_inserted = 0;
0914     pcr->card_removed = 0;
0915 
0916     spin_unlock_irqrestore(&pcr->lock, flags);
0917 
0918     if (card_inserted || card_removed) {
0919         pcr_dbg(pcr, "card_inserted: 0x%x, card_removed: 0x%x\n",
0920             card_inserted, card_removed);
0921 
0922         if (pcr->ops->cd_deglitch)
0923             card_inserted = pcr->ops->cd_deglitch(pcr);
0924 
0925         card_detect = card_inserted | card_removed;
0926 
0927         pcr->card_exist |= card_inserted;
0928         pcr->card_exist &= ~card_removed;
0929     }
0930 
0931     mutex_unlock(&pcr->pcr_mutex);
0932 
0933     if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
0934         pcr->slots[RTSX_SD_CARD].card_event(
0935                 pcr->slots[RTSX_SD_CARD].p_dev);
0936     if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
0937         pcr->slots[RTSX_MS_CARD].card_event(
0938                 pcr->slots[RTSX_MS_CARD].p_dev);
0939 }
0940 
0941 static void rtsx_pci_process_ocp(struct rtsx_pcr *pcr)
0942 {
0943     if (pcr->ops->process_ocp) {
0944         pcr->ops->process_ocp(pcr);
0945     } else {
0946         if (!pcr->option.ocp_en)
0947             return;
0948         rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
0949         if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
0950             rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
0951             rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
0952             rtsx_pci_clear_ocpstat(pcr);
0953             pcr->ocp_stat = 0;
0954         }
0955     }
0956 }
0957 
0958 static int rtsx_pci_process_ocp_interrupt(struct rtsx_pcr *pcr)
0959 {
0960     if (pcr->option.ocp_en)
0961         rtsx_pci_process_ocp(pcr);
0962 
0963     return 0;
0964 }
0965 
0966 static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
0967 {
0968     struct rtsx_pcr *pcr = dev_id;
0969     u32 int_reg;
0970 
0971     if (!pcr)
0972         return IRQ_NONE;
0973 
0974     spin_lock(&pcr->lock);
0975 
0976     int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
0977     /* Clear interrupt flag */
0978     rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
0979     if ((int_reg & pcr->bier) == 0) {
0980         spin_unlock(&pcr->lock);
0981         return IRQ_NONE;
0982     }
0983     if (int_reg == 0xFFFFFFFF) {
0984         spin_unlock(&pcr->lock);
0985         return IRQ_HANDLED;
0986     }
0987 
0988     int_reg &= (pcr->bier | 0x7FFFFF);
0989 
0990     if (int_reg & SD_OC_INT)
0991         rtsx_pci_process_ocp_interrupt(pcr);
0992 
0993     if (int_reg & SD_INT) {
0994         if (int_reg & SD_EXIST) {
0995             pcr->card_inserted |= SD_EXIST;
0996         } else {
0997             pcr->card_removed |= SD_EXIST;
0998             pcr->card_inserted &= ~SD_EXIST;
0999             if (PCI_PID(pcr) == PID_5261) {
1000                 rtsx_pci_write_register(pcr, RTS5261_FW_STATUS,
1001                     RTS5261_EXPRESS_LINK_FAIL_MASK, 0);
1002                 pcr->extra_caps |= EXTRA_CAPS_SD_EXPRESS;
1003             }
1004         }
1005         pcr->dma_error_count = 0;
1006     }
1007 
1008     if (int_reg & MS_INT) {
1009         if (int_reg & MS_EXIST) {
1010             pcr->card_inserted |= MS_EXIST;
1011         } else {
1012             pcr->card_removed |= MS_EXIST;
1013             pcr->card_inserted &= ~MS_EXIST;
1014         }
1015     }
1016 
1017     if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
1018         if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
1019             pcr->trans_result = TRANS_RESULT_FAIL;
1020             if (pcr->done)
1021                 complete(pcr->done);
1022         } else if (int_reg & TRANS_OK_INT) {
1023             pcr->trans_result = TRANS_RESULT_OK;
1024             if (pcr->done)
1025                 complete(pcr->done);
1026         }
1027     }
1028 
1029     if ((pcr->card_inserted || pcr->card_removed) && !(int_reg & SD_OC_INT))
1030         schedule_delayed_work(&pcr->carddet_work,
1031                 msecs_to_jiffies(200));
1032 
1033     spin_unlock(&pcr->lock);
1034     return IRQ_HANDLED;
1035 }
1036 
1037 static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
1038 {
1039     pcr_dbg(pcr, "%s: pcr->msi_en = %d, pci->irq = %d\n",
1040             __func__, pcr->msi_en, pcr->pci->irq);
1041 
1042     if (request_irq(pcr->pci->irq, rtsx_pci_isr,
1043             pcr->msi_en ? 0 : IRQF_SHARED,
1044             DRV_NAME_RTSX_PCI, pcr)) {
1045         dev_err(&(pcr->pci->dev),
1046             "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
1047             pcr->pci->irq);
1048         return -1;
1049     }
1050 
1051     pcr->irq = pcr->pci->irq;
1052     pci_intx(pcr->pci, !pcr->msi_en);
1053 
1054     return 0;
1055 }
1056 
1057 static void rtsx_base_force_power_down(struct rtsx_pcr *pcr)
1058 {
1059     /* Set relink_time to 0 */
1060     rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
1061     rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
1062     rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
1063             RELINK_TIME_MASK, 0);
1064 
1065     rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
1066             D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
1067 
1068     rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN);
1069 }
1070 
1071 static void __maybe_unused rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
1072 {
1073     if (pcr->ops->turn_off_led)
1074         pcr->ops->turn_off_led(pcr);
1075 
1076     rtsx_pci_writel(pcr, RTSX_BIER, 0);
1077     pcr->bier = 0;
1078 
1079     rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
1080     rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state);
1081 
1082     if (pcr->ops->force_power_down)
1083         pcr->ops->force_power_down(pcr, pm_state, runtime);
1084     else
1085         rtsx_base_force_power_down(pcr);
1086 }
1087 
1088 void rtsx_pci_enable_ocp(struct rtsx_pcr *pcr)
1089 {
1090     u8 val = SD_OCP_INT_EN | SD_DETECT_EN;
1091 
1092     if (pcr->ops->enable_ocp) {
1093         pcr->ops->enable_ocp(pcr);
1094     } else {
1095         rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0);
1096         rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
1097     }
1098 
1099 }
1100 
1101 void rtsx_pci_disable_ocp(struct rtsx_pcr *pcr)
1102 {
1103     u8 mask = SD_OCP_INT_EN | SD_DETECT_EN;
1104 
1105     if (pcr->ops->disable_ocp) {
1106         pcr->ops->disable_ocp(pcr);
1107     } else {
1108         rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
1109         rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN,
1110                 OC_POWER_DOWN);
1111     }
1112 }
1113 
1114 void rtsx_pci_init_ocp(struct rtsx_pcr *pcr)
1115 {
1116     if (pcr->ops->init_ocp) {
1117         pcr->ops->init_ocp(pcr);
1118     } else {
1119         struct rtsx_cr_option *option = &(pcr->option);
1120 
1121         if (option->ocp_en) {
1122             u8 val = option->sd_800mA_ocp_thd;
1123 
1124             rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0);
1125             rtsx_pci_write_register(pcr, REG_OCPPARA1,
1126                 SD_OCP_TIME_MASK, SD_OCP_TIME_800);
1127             rtsx_pci_write_register(pcr, REG_OCPPARA2,
1128                 SD_OCP_THD_MASK, val);
1129             rtsx_pci_write_register(pcr, REG_OCPGLITCH,
1130                 SD_OCP_GLITCH_MASK, pcr->hw_param.ocp_glitch);
1131             rtsx_pci_enable_ocp(pcr);
1132         }
1133     }
1134 }
1135 
1136 int rtsx_pci_get_ocpstat(struct rtsx_pcr *pcr, u8 *val)
1137 {
1138     if (pcr->ops->get_ocpstat)
1139         return pcr->ops->get_ocpstat(pcr, val);
1140     else
1141         return rtsx_pci_read_register(pcr, REG_OCPSTAT, val);
1142 }
1143 
1144 void rtsx_pci_clear_ocpstat(struct rtsx_pcr *pcr)
1145 {
1146     if (pcr->ops->clear_ocpstat) {
1147         pcr->ops->clear_ocpstat(pcr);
1148     } else {
1149         u8 mask = SD_OCP_INT_CLR | SD_OC_CLR;
1150         u8 val = SD_OCP_INT_CLR | SD_OC_CLR;
1151 
1152         rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
1153         udelay(100);
1154         rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
1155     }
1156 }
1157 
1158 void rtsx_pci_enable_oobs_polling(struct rtsx_pcr *pcr)
1159 {
1160     u16 val;
1161 
1162     if ((PCI_PID(pcr) != PID_525A) && (PCI_PID(pcr) != PID_5260)) {
1163         rtsx_pci_read_phy_register(pcr, 0x01, &val);
1164         val |= 1<<9;
1165         rtsx_pci_write_phy_register(pcr, 0x01, val);
1166     }
1167     rtsx_pci_write_register(pcr, REG_CFG_OOBS_OFF_TIMER, 0xFF, 0x32);
1168     rtsx_pci_write_register(pcr, REG_CFG_OOBS_ON_TIMER, 0xFF, 0x05);
1169     rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x83);
1170     rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0xDE);
1171 
1172 }
1173 
1174 void rtsx_pci_disable_oobs_polling(struct rtsx_pcr *pcr)
1175 {
1176     u16 val;
1177 
1178     if ((PCI_PID(pcr) != PID_525A) && (PCI_PID(pcr) != PID_5260)) {
1179         rtsx_pci_read_phy_register(pcr, 0x01, &val);
1180         val &= ~(1<<9);
1181         rtsx_pci_write_phy_register(pcr, 0x01, val);
1182     }
1183     rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x03);
1184     rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0x00);
1185 
1186 }
1187 
1188 int rtsx_sd_power_off_card3v3(struct rtsx_pcr *pcr)
1189 {
1190     rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN |
1191         MS_CLK_EN | SD40_CLK_EN, 0);
1192     rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
1193     rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
1194 
1195     msleep(50);
1196 
1197     rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
1198 
1199     return 0;
1200 }
1201 
1202 int rtsx_ms_power_off_card3v3(struct rtsx_pcr *pcr)
1203 {
1204     rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN |
1205         MS_CLK_EN | SD40_CLK_EN, 0);
1206 
1207     rtsx_pci_card_pull_ctl_disable(pcr, RTSX_MS_CARD);
1208 
1209     rtsx_pci_write_register(pcr, CARD_OE, MS_OUTPUT_EN, 0);
1210     rtsx_pci_card_power_off(pcr, RTSX_MS_CARD);
1211 
1212     return 0;
1213 }
1214 
1215 static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
1216 {
1217     struct pci_dev *pdev = pcr->pci;
1218     int err;
1219 
1220     if (PCI_PID(pcr) == PID_5228)
1221         rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG1, RTS5228_LDO1_SR_TIME_MASK,
1222                 RTS5228_LDO1_SR_0_5);
1223 
1224     rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
1225 
1226     rtsx_pci_enable_bus_int(pcr);
1227 
1228     /* Power on SSC */
1229     if (PCI_PID(pcr) == PID_5261) {
1230         /* Gating real mcu clock */
1231         err = rtsx_pci_write_register(pcr, RTS5261_FW_CFG1,
1232             RTS5261_MCU_CLOCK_GATING, 0);
1233         err = rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL,
1234             SSC_POWER_DOWN, 0);
1235     } else {
1236         err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
1237     }
1238     if (err < 0)
1239         return err;
1240 
1241     /* Wait SSC power stable */
1242     udelay(200);
1243 
1244     rtsx_disable_aspm(pcr);
1245     if (pcr->ops->optimize_phy) {
1246         err = pcr->ops->optimize_phy(pcr);
1247         if (err < 0)
1248             return err;
1249     }
1250 
1251     rtsx_pci_init_cmd(pcr);
1252 
1253     /* Set mcu_cnt to 7 to ensure data can be sampled properly */
1254     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
1255 
1256     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
1257     /* Disable card clock */
1258     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
1259     /* Reset delink mode */
1260     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
1261     /* Card driving select */
1262     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,
1263             0xFF, pcr->card_drive_sel);
1264     /* Enable SSC Clock */
1265     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
1266             0xFF, SSC_8X_EN | SSC_SEL_4M);
1267     if (PCI_PID(pcr) == PID_5261)
1268         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,
1269             RTS5261_SSC_DEPTH_2M);
1270     else if (PCI_PID(pcr) == PID_5228)
1271         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,
1272             RTS5228_SSC_DEPTH_2M);
1273     else
1274         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
1275 
1276     /* Disable cd_pwr_save */
1277     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
1278     /* Clear Link Ready Interrupt */
1279     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
1280             LINK_RDY_INT, LINK_RDY_INT);
1281     /* Enlarge the estimation window of PERST# glitch
1282      * to reduce the chance of invalid card interrupt
1283      */
1284     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
1285     /* Update RC oscillator to 400k
1286      * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
1287      *                1: 2M  0: 400k
1288      */
1289     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
1290     /* Set interrupt write clear
1291      * bit 1: U_elbi_if_rd_clr_en
1292      *  1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
1293      *  0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
1294      */
1295     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
1296 
1297     err = rtsx_pci_send_cmd(pcr, 100);
1298     if (err < 0)
1299         return err;
1300 
1301     switch (PCI_PID(pcr)) {
1302     case PID_5250:
1303     case PID_524A:
1304     case PID_525A:
1305     case PID_5260:
1306     case PID_5261:
1307     case PID_5228:
1308         rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 1, 1);
1309         break;
1310     default:
1311         break;
1312     }
1313 
1314     /*init ocp*/
1315     rtsx_pci_init_ocp(pcr);
1316 
1317     /* Enable clk_request_n to enable clock power management */
1318     pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
1319                     0, PCI_EXP_LNKCTL_CLKREQ_EN);
1320     /* Enter L1 when host tx idle */
1321     pci_write_config_byte(pdev, 0x70F, 0x5B);
1322 
1323     if (pcr->ops->extra_init_hw) {
1324         err = pcr->ops->extra_init_hw(pcr);
1325         if (err < 0)
1326             return err;
1327     }
1328 
1329     if (pcr->aspm_mode == ASPM_MODE_REG)
1330         rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0x30, 0x30);
1331 
1332     /* No CD interrupt if probing driver with card inserted.
1333      * So we need to initialize pcr->card_exist here.
1334      */
1335     if (pcr->ops->cd_deglitch)
1336         pcr->card_exist = pcr->ops->cd_deglitch(pcr);
1337     else
1338         pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST;
1339 
1340     return 0;
1341 }
1342 
1343 static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
1344 {
1345     int err;
1346     u16 cfg_val;
1347     u8 val;
1348 
1349     spin_lock_init(&pcr->lock);
1350     mutex_init(&pcr->pcr_mutex);
1351 
1352     switch (PCI_PID(pcr)) {
1353     default:
1354     case 0x5209:
1355         rts5209_init_params(pcr);
1356         break;
1357 
1358     case 0x5229:
1359         rts5229_init_params(pcr);
1360         break;
1361 
1362     case 0x5289:
1363         rtl8411_init_params(pcr);
1364         break;
1365 
1366     case 0x5227:
1367         rts5227_init_params(pcr);
1368         break;
1369 
1370     case 0x522A:
1371         rts522a_init_params(pcr);
1372         break;
1373 
1374     case 0x5249:
1375         rts5249_init_params(pcr);
1376         break;
1377 
1378     case 0x524A:
1379         rts524a_init_params(pcr);
1380         break;
1381 
1382     case 0x525A:
1383         rts525a_init_params(pcr);
1384         break;
1385 
1386     case 0x5287:
1387         rtl8411b_init_params(pcr);
1388         break;
1389 
1390     case 0x5286:
1391         rtl8402_init_params(pcr);
1392         break;
1393 
1394     case 0x5260:
1395         rts5260_init_params(pcr);
1396         break;
1397 
1398     case 0x5261:
1399         rts5261_init_params(pcr);
1400         break;
1401 
1402     case 0x5228:
1403         rts5228_init_params(pcr);
1404         break;
1405     }
1406 
1407     pcr_dbg(pcr, "PID: 0x%04x, IC version: 0x%02x\n",
1408             PCI_PID(pcr), pcr->ic_version);
1409 
1410     pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1411             GFP_KERNEL);
1412     if (!pcr->slots)
1413         return -ENOMEM;
1414 
1415     if (pcr->aspm_mode == ASPM_MODE_CFG) {
1416         pcie_capability_read_word(pcr->pci, PCI_EXP_LNKCTL, &cfg_val);
1417         if (cfg_val & PCI_EXP_LNKCTL_ASPM_L1)
1418             pcr->aspm_enabled = true;
1419         else
1420             pcr->aspm_enabled = false;
1421 
1422     } else if (pcr->aspm_mode == ASPM_MODE_REG) {
1423         rtsx_pci_read_register(pcr, ASPM_FORCE_CTL, &val);
1424         if (val & FORCE_ASPM_CTL0 && val & FORCE_ASPM_CTL1)
1425             pcr->aspm_enabled = false;
1426         else
1427             pcr->aspm_enabled = true;
1428     }
1429 
1430     if (pcr->ops->fetch_vendor_settings)
1431         pcr->ops->fetch_vendor_settings(pcr);
1432 
1433     pcr_dbg(pcr, "pcr->aspm_en = 0x%x\n", pcr->aspm_en);
1434     pcr_dbg(pcr, "pcr->sd30_drive_sel_1v8 = 0x%x\n",
1435             pcr->sd30_drive_sel_1v8);
1436     pcr_dbg(pcr, "pcr->sd30_drive_sel_3v3 = 0x%x\n",
1437             pcr->sd30_drive_sel_3v3);
1438     pcr_dbg(pcr, "pcr->card_drive_sel = 0x%x\n",
1439             pcr->card_drive_sel);
1440     pcr_dbg(pcr, "pcr->flags = 0x%x\n", pcr->flags);
1441 
1442     pcr->state = PDEV_STAT_IDLE;
1443     err = rtsx_pci_init_hw(pcr);
1444     if (err < 0) {
1445         kfree(pcr->slots);
1446         return err;
1447     }
1448 
1449     return 0;
1450 }
1451 
1452 static int rtsx_pci_probe(struct pci_dev *pcidev,
1453               const struct pci_device_id *id)
1454 {
1455     struct rtsx_pcr *pcr;
1456     struct pcr_handle *handle;
1457     u32 base, len;
1458     int ret, i, bar = 0;
1459 
1460     dev_dbg(&(pcidev->dev),
1461         ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1462         pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1463         (int)pcidev->revision);
1464 
1465     ret = dma_set_mask(&pcidev->dev, DMA_BIT_MASK(32));
1466     if (ret < 0)
1467         return ret;
1468 
1469     ret = pci_enable_device(pcidev);
1470     if (ret)
1471         return ret;
1472 
1473     ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
1474     if (ret)
1475         goto disable;
1476 
1477     pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1478     if (!pcr) {
1479         ret = -ENOMEM;
1480         goto release_pci;
1481     }
1482 
1483     handle = kzalloc(sizeof(*handle), GFP_KERNEL);
1484     if (!handle) {
1485         ret = -ENOMEM;
1486         goto free_pcr;
1487     }
1488     handle->pcr = pcr;
1489 
1490     idr_preload(GFP_KERNEL);
1491     spin_lock(&rtsx_pci_lock);
1492     ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT);
1493     if (ret >= 0)
1494         pcr->id = ret;
1495     spin_unlock(&rtsx_pci_lock);
1496     idr_preload_end();
1497     if (ret < 0)
1498         goto free_handle;
1499 
1500     pcr->pci = pcidev;
1501     dev_set_drvdata(&pcidev->dev, handle);
1502 
1503     if (CHK_PCI_PID(pcr, 0x525A))
1504         bar = 1;
1505     len = pci_resource_len(pcidev, bar);
1506     base = pci_resource_start(pcidev, bar);
1507     pcr->remap_addr = ioremap(base, len);
1508     if (!pcr->remap_addr) {
1509         ret = -ENOMEM;
1510         goto free_idr;
1511     }
1512 
1513     pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1514             RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1515             GFP_KERNEL);
1516     if (pcr->rtsx_resv_buf == NULL) {
1517         ret = -ENXIO;
1518         goto unmap;
1519     }
1520     pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1521     pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1522     pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1523     pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1524     pcr->card_inserted = 0;
1525     pcr->card_removed = 0;
1526     INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1527 
1528     pcr->msi_en = msi_en;
1529     if (pcr->msi_en) {
1530         ret = pci_enable_msi(pcidev);
1531         if (ret)
1532             pcr->msi_en = false;
1533     }
1534 
1535     ret = rtsx_pci_acquire_irq(pcr);
1536     if (ret < 0)
1537         goto disable_msi;
1538 
1539     pci_set_master(pcidev);
1540     synchronize_irq(pcr->irq);
1541 
1542     ret = rtsx_pci_init_chip(pcr);
1543     if (ret < 0)
1544         goto disable_irq;
1545 
1546     for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
1547         rtsx_pcr_cells[i].platform_data = handle;
1548         rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
1549     }
1550 
1551 
1552     ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1553             ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
1554     if (ret < 0)
1555         goto free_slots;
1556 
1557     pm_runtime_allow(&pcidev->dev);
1558     pm_runtime_put(&pcidev->dev);
1559 
1560     return 0;
1561 
1562 free_slots:
1563     kfree(pcr->slots);
1564 disable_irq:
1565     free_irq(pcr->irq, (void *)pcr);
1566 disable_msi:
1567     if (pcr->msi_en)
1568         pci_disable_msi(pcr->pci);
1569     dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1570             pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1571 unmap:
1572     iounmap(pcr->remap_addr);
1573 free_idr:
1574     spin_lock(&rtsx_pci_lock);
1575     idr_remove(&rtsx_pci_idr, pcr->id);
1576     spin_unlock(&rtsx_pci_lock);
1577 free_handle:
1578     kfree(handle);
1579 free_pcr:
1580     kfree(pcr);
1581 release_pci:
1582     pci_release_regions(pcidev);
1583 disable:
1584     pci_disable_device(pcidev);
1585 
1586     return ret;
1587 }
1588 
1589 static void rtsx_pci_remove(struct pci_dev *pcidev)
1590 {
1591     struct pcr_handle *handle = pci_get_drvdata(pcidev);
1592     struct rtsx_pcr *pcr = handle->pcr;
1593 
1594     pcr->remove_pci = true;
1595 
1596     pm_runtime_get_sync(&pcidev->dev);
1597     pm_runtime_forbid(&pcidev->dev);
1598 
1599     /* Disable interrupts at the pcr level */
1600     spin_lock_irq(&pcr->lock);
1601     rtsx_pci_writel(pcr, RTSX_BIER, 0);
1602     pcr->bier = 0;
1603     spin_unlock_irq(&pcr->lock);
1604 
1605     cancel_delayed_work_sync(&pcr->carddet_work);
1606 
1607     mfd_remove_devices(&pcidev->dev);
1608 
1609     dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1610             pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1611     free_irq(pcr->irq, (void *)pcr);
1612     if (pcr->msi_en)
1613         pci_disable_msi(pcr->pci);
1614     iounmap(pcr->remap_addr);
1615 
1616     pci_release_regions(pcidev);
1617     pci_disable_device(pcidev);
1618 
1619     spin_lock(&rtsx_pci_lock);
1620     idr_remove(&rtsx_pci_idr, pcr->id);
1621     spin_unlock(&rtsx_pci_lock);
1622 
1623     kfree(pcr->slots);
1624     kfree(pcr);
1625     kfree(handle);
1626 
1627     dev_dbg(&(pcidev->dev),
1628         ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1629         pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1630 }
1631 
1632 static int __maybe_unused rtsx_pci_suspend(struct device *dev_d)
1633 {
1634     struct pci_dev *pcidev = to_pci_dev(dev_d);
1635     struct pcr_handle *handle = pci_get_drvdata(pcidev);
1636     struct rtsx_pcr *pcr = handle->pcr;
1637 
1638     dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1639 
1640     cancel_delayed_work_sync(&pcr->carddet_work);
1641 
1642     mutex_lock(&pcr->pcr_mutex);
1643 
1644     rtsx_pci_power_off(pcr, HOST_ENTER_S3, false);
1645 
1646     mutex_unlock(&pcr->pcr_mutex);
1647     return 0;
1648 }
1649 
1650 static int __maybe_unused rtsx_pci_resume(struct device *dev_d)
1651 {
1652     struct pci_dev *pcidev = to_pci_dev(dev_d);
1653     struct pcr_handle *handle = pci_get_drvdata(pcidev);
1654     struct rtsx_pcr *pcr = handle->pcr;
1655     int ret = 0;
1656 
1657     dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1658 
1659     mutex_lock(&pcr->pcr_mutex);
1660 
1661     ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1662     if (ret)
1663         goto out;
1664 
1665     ret = rtsx_pci_init_hw(pcr);
1666     if (ret)
1667         goto out;
1668 
1669 out:
1670     mutex_unlock(&pcr->pcr_mutex);
1671     return ret;
1672 }
1673 
1674 #ifdef CONFIG_PM
1675 
1676 static void rtsx_enable_aspm(struct rtsx_pcr *pcr)
1677 {
1678     if (pcr->ops->set_aspm)
1679         pcr->ops->set_aspm(pcr, true);
1680     else
1681         rtsx_comm_set_aspm(pcr, true);
1682 }
1683 
1684 static void rtsx_comm_pm_power_saving(struct rtsx_pcr *pcr)
1685 {
1686     struct rtsx_cr_option *option = &pcr->option;
1687 
1688     if (option->ltr_enabled) {
1689         u32 latency = option->ltr_l1off_latency;
1690 
1691         if (rtsx_check_dev_flag(pcr, L1_SNOOZE_TEST_EN))
1692             mdelay(option->l1_snooze_delay);
1693 
1694         rtsx_set_ltr_latency(pcr, latency);
1695     }
1696 
1697     if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN))
1698         rtsx_set_l1off_sub_cfg_d0(pcr, 0);
1699 
1700     rtsx_enable_aspm(pcr);
1701 }
1702 
1703 static void rtsx_pm_power_saving(struct rtsx_pcr *pcr)
1704 {
1705     rtsx_comm_pm_power_saving(pcr);
1706 }
1707 
1708 static void rtsx_pci_shutdown(struct pci_dev *pcidev)
1709 {
1710     struct pcr_handle *handle = pci_get_drvdata(pcidev);
1711     struct rtsx_pcr *pcr = handle->pcr;
1712 
1713     dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1714 
1715     rtsx_pci_power_off(pcr, HOST_ENTER_S1, false);
1716 
1717     pci_disable_device(pcidev);
1718     free_irq(pcr->irq, (void *)pcr);
1719     if (pcr->msi_en)
1720         pci_disable_msi(pcr->pci);
1721 }
1722 
1723 static int rtsx_pci_runtime_idle(struct device *device)
1724 {
1725     struct pci_dev *pcidev = to_pci_dev(device);
1726     struct pcr_handle *handle = pci_get_drvdata(pcidev);
1727     struct rtsx_pcr *pcr = handle->pcr;
1728 
1729     dev_dbg(device, "--> %s\n", __func__);
1730 
1731     mutex_lock(&pcr->pcr_mutex);
1732 
1733     pcr->state = PDEV_STAT_IDLE;
1734 
1735     if (pcr->ops->disable_auto_blink)
1736         pcr->ops->disable_auto_blink(pcr);
1737     if (pcr->ops->turn_off_led)
1738         pcr->ops->turn_off_led(pcr);
1739 
1740     rtsx_pm_power_saving(pcr);
1741 
1742     mutex_unlock(&pcr->pcr_mutex);
1743 
1744     if (pcr->rtd3_en)
1745         pm_schedule_suspend(device, 10000);
1746 
1747     return -EBUSY;
1748 }
1749 
1750 static int rtsx_pci_runtime_suspend(struct device *device)
1751 {
1752     struct pci_dev *pcidev = to_pci_dev(device);
1753     struct pcr_handle *handle = pci_get_drvdata(pcidev);
1754     struct rtsx_pcr *pcr = handle->pcr;
1755 
1756     dev_dbg(device, "--> %s\n", __func__);
1757 
1758     cancel_delayed_work_sync(&pcr->carddet_work);
1759 
1760     mutex_lock(&pcr->pcr_mutex);
1761     rtsx_pci_power_off(pcr, HOST_ENTER_S3, true);
1762 
1763     mutex_unlock(&pcr->pcr_mutex);
1764 
1765     return 0;
1766 }
1767 
1768 static int rtsx_pci_runtime_resume(struct device *device)
1769 {
1770     struct pci_dev *pcidev = to_pci_dev(device);
1771     struct pcr_handle *handle = pci_get_drvdata(pcidev);
1772     struct rtsx_pcr *pcr = handle->pcr;
1773 
1774     dev_dbg(device, "--> %s\n", __func__);
1775 
1776     mutex_lock(&pcr->pcr_mutex);
1777 
1778     rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1779 
1780     rtsx_pci_init_hw(pcr);
1781 
1782     if (pcr->slots[RTSX_SD_CARD].p_dev != NULL) {
1783         pcr->slots[RTSX_SD_CARD].card_event(
1784                 pcr->slots[RTSX_SD_CARD].p_dev);
1785     }
1786 
1787     mutex_unlock(&pcr->pcr_mutex);
1788     return 0;
1789 }
1790 
1791 #else /* CONFIG_PM */
1792 
1793 #define rtsx_pci_shutdown NULL
1794 #define rtsx_pci_runtime_suspend NULL
1795 #define rtsx_pic_runtime_resume NULL
1796 
1797 #endif /* CONFIG_PM */
1798 
1799 static const struct dev_pm_ops rtsx_pci_pm_ops = {
1800     SET_SYSTEM_SLEEP_PM_OPS(rtsx_pci_suspend, rtsx_pci_resume)
1801     SET_RUNTIME_PM_OPS(rtsx_pci_runtime_suspend, rtsx_pci_runtime_resume, rtsx_pci_runtime_idle)
1802 };
1803 
1804 static struct pci_driver rtsx_pci_driver = {
1805     .name = DRV_NAME_RTSX_PCI,
1806     .id_table = rtsx_pci_ids,
1807     .probe = rtsx_pci_probe,
1808     .remove = rtsx_pci_remove,
1809     .driver.pm = &rtsx_pci_pm_ops,
1810     .shutdown = rtsx_pci_shutdown,
1811 };
1812 module_pci_driver(rtsx_pci_driver);
1813 
1814 MODULE_LICENSE("GPL");
1815 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1816 MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");
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