misc/cardreader/rts5261.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Driver for Realtek PCI-Express card reader
0003  *
0004  * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
0005  *
0006  * Author:
0007  *   Rui FENG <rui_feng@realsil.com.cn>
0008  *   Wei WANG <wei_wang@realsil.com.cn>
0009  */
0010 #ifndef RTS5261_H
0011 #define RTS5261_H
0012
0013 /*New add*/
0014 #define rts5261_vendor_setting_valid(reg)   ((reg) & 0x010000)
0015 #define rts5261_reg_to_aspm(reg) \
0016     (((~(reg) >> 28) & 0x02) | (((reg) >> 28) & 0x01))
0017 #define rts5261_reg_check_reverse_socket(reg)   ((reg) & 0x04)
0018 #define rts5261_reg_to_sd30_drive_sel_1v8(reg)  (((reg) >> 22) & 0x03)
0019 #define rts5261_reg_to_sd30_drive_sel_3v3(reg)  (((reg) >> 16) & 0x03)
0020 #define rts5261_reg_to_rtd3(reg)        ((reg) & 0x08)
0021 #define rts5261_reg_check_mmc_support(reg)  ((reg) & 0x10)
0022
0023 #define RTS5261_AUTOLOAD_CFG0       0xFF7B
0024 #define RTS5261_AUTOLOAD_CFG1       0xFF7C
0025 #define RTS5261_AUTOLOAD_CFG2       0xFF7D
0026 #define RTS5261_AUTOLOAD_CFG3       0xFF7E
0027 #define RTS5261_AUTOLOAD_CFG4       0xFF7F
0028 #define RTS5261_FORCE_PRSNT_LOW     (1 << 6)
0029 #define RTS5261_AUX_CLK_16M_EN      (1 << 5)
0030
0031 #define RTS5261_REG_VREF        0xFE97
0032 #define RTS5261_PWD_SUSPND_EN       (1 << 4)
0033
0034 #define RTS5261_PAD_H3L1        0xFF79
0035 #define PAD_GPIO_H3L1           (1 << 3)
0036
0037 /* SSC_CTL2 0xFC12 */
0038 #define RTS5261_SSC_DEPTH_MASK      0x07
0039 #define RTS5261_SSC_DEPTH_DISALBE   0x00
0040 #define RTS5261_SSC_DEPTH_8M        0x01
0041 #define RTS5261_SSC_DEPTH_4M        0x02
0042 #define RTS5261_SSC_DEPTH_2M        0x03
0043 #define RTS5261_SSC_DEPTH_1M        0x04
0044 #define RTS5261_SSC_DEPTH_512K      0x05
0045 #define RTS5261_SSC_DEPTH_256K      0x06
0046 #define RTS5261_SSC_DEPTH_128K      0x07
0047
0048 /* efuse control register*/
0049 #define RTS5261_EFUSE_CTL       0xFC30
0050 #define RTS5261_EFUSE_ENABLE        0x80
0051 /* EFUSE_MODE: 0=READ 1=PROGRAM */
0052 #define RTS5261_EFUSE_MODE_MASK     0x40
0053 #define RTS5261_EFUSE_PROGRAM       0x40
0054
0055 #define RTS5261_EFUSE_ADDR      0xFC31
0056 #define RTS5261_EFUSE_ADDR_MASK     0x3F
0057
0058 #define RTS5261_EFUSE_WRITE_DATA    0xFC32
0059 #define RTS5261_EFUSE_READ_DATA     0xFC34
0060
0061 /* DMACTL 0xFE2C */
0062 #define RTS5261_DMA_PACK_SIZE_MASK  0xF0
0063
0064 /* FW status register */
0065 #define RTS5261_FW_STATUS       0xFF56
0066 #define RTS5261_EXPRESS_LINK_FAIL_MASK  (0x01<<7)
0067
0068 /* FW control register */
0069 #define RTS5261_FW_CTL          0xFF5F
0070 #define RTS5261_INFORM_RTD3_COLD    (0x01<<5)
0071
0072 #define RTS5261_REG_FPDCTL      0xFF60
0073
0074 #define RTS5261_REG_LDO12_CFG       0xFF6E
0075 #define RTS5261_LDO12_VO_TUNE_MASK  (0x07<<1)
0076 #define RTS5261_LDO12_115       (0x03<<1)
0077 #define RTS5261_LDO12_120       (0x04<<1)
0078 #define RTS5261_LDO12_125       (0x05<<1)
0079 #define RTS5261_LDO12_130       (0x06<<1)
0080 #define RTS5261_LDO12_135       (0x07<<1)
0081
0082 /* LDO control register */
0083 #define RTS5261_CARD_PWR_CTL        0xFD50
0084 #define RTS5261_SD_CLK_ISO      (0x01<<7)
0085 #define RTS5261_PAD_SD_DAT_FW_CTRL  (0x01<<6)
0086 #define RTS5261_PUPDC           (0x01<<5)
0087 #define RTS5261_SD_CMD_ISO      (0x01<<4)
0088 #define RTS5261_SD_DAT_ISO_MASK     (0x0F<<0)
0089
0090 #define RTS5261_LDO1233318_POW_CTL  0xFF70
0091 #define RTS5261_LDO3318_POWERON     (0x01<<3)
0092 #define RTS5261_LDO3_POWERON        (0x01<<2)
0093 #define RTS5261_LDO2_POWERON        (0x01<<1)
0094 #define RTS5261_LDO1_POWERON        (0x01<<0)
0095 #define RTS5261_LDO_POWERON_MASK    (0x0F<<0)
0096
0097 #define RTS5261_DV3318_CFG      0xFF71
0098 #define RTS5261_DV3318_TUNE_MASK    (0x07<<4)
0099 #define RTS5261_DV3318_18       (0x02<<4)
0100 #define RTS5261_DV3318_19       (0x04<<4)
0101 #define RTS5261_DV3318_33       (0x07<<4)
0102
0103 /* CRD6603-433 190319 request changed */
0104 #define RTS5261_LDO1_OCP_THD_740    (0x00<<5)
0105 #define RTS5261_LDO1_OCP_THD_800    (0x01<<5)
0106 #define RTS5261_LDO1_OCP_THD_860    (0x02<<5)
0107 #define RTS5261_LDO1_OCP_THD_920    (0x03<<5)
0108 #define RTS5261_LDO1_OCP_THD_980    (0x04<<5)
0109 #define RTS5261_LDO1_OCP_THD_1040   (0x05<<5)
0110 #define RTS5261_LDO1_OCP_THD_1100   (0x06<<5)
0111 #define RTS5261_LDO1_OCP_THD_1160   (0x07<<5)
0112
0113 #define RTS5261_LDO1_LMT_THD_450    (0x00<<2)
0114 #define RTS5261_LDO1_LMT_THD_1000   (0x01<<2)
0115 #define RTS5261_LDO1_LMT_THD_1500   (0x02<<2)
0116 #define RTS5261_LDO1_LMT_THD_2000   (0x03<<2)
0117
0118 #define RTS5261_LDO1_CFG1       0xFF73
0119 #define RTS5261_LDO1_TUNE_MASK      (0x07<<1)
0120 #define RTS5261_LDO1_18         (0x05<<1)
0121 #define RTS5261_LDO1_33         (0x07<<1)
0122 #define RTS5261_LDO1_PWD_MASK       (0x01<<0)
0123
0124 #define RTS5261_LDO2_CFG0       0xFF74
0125 #define RTS5261_LDO2_OCP_THD_MASK   (0x07<<5)
0126 #define RTS5261_LDO2_OCP_EN     (0x01<<4)
0127 #define RTS5261_LDO2_OCP_LMT_THD_MASK   (0x03<<2)
0128 #define RTS5261_LDO2_OCP_LMT_EN     (0x01<<1)
0129
0130 #define RTS5261_LDO2_OCP_THD_620    (0x00<<5)
0131 #define RTS5261_LDO2_OCP_THD_650    (0x01<<5)
0132 #define RTS5261_LDO2_OCP_THD_680    (0x02<<5)
0133 #define RTS5261_LDO2_OCP_THD_720    (0x03<<5)
0134 #define RTS5261_LDO2_OCP_THD_750    (0x04<<5)
0135 #define RTS5261_LDO2_OCP_THD_780    (0x05<<5)
0136 #define RTS5261_LDO2_OCP_THD_810    (0x06<<5)
0137 #define RTS5261_LDO2_OCP_THD_840    (0x07<<5)
0138
0139 #define RTS5261_LDO2_CFG1       0xFF75
0140 #define RTS5261_LDO2_TUNE_MASK      (0x07<<1)
0141 #define RTS5261_LDO2_18         (0x05<<1)
0142 #define RTS5261_LDO2_33         (0x07<<1)
0143 #define RTS5261_LDO2_PWD_MASK       (0x01<<0)
0144
0145 #define RTS5261_LDO3_CFG0       0xFF76
0146 #define RTS5261_LDO3_OCP_THD_MASK   (0x07<<5)
0147 #define RTS5261_LDO3_OCP_EN     (0x01<<4)
0148 #define RTS5261_LDO3_OCP_LMT_THD_MASK   (0x03<<2)
0149 #define RTS5261_LDO3_OCP_LMT_EN     (0x01<<1)
0150
0151 #define RTS5261_LDO3_OCP_THD_620    (0x00<<5)
0152 #define RTS5261_LDO3_OCP_THD_650    (0x01<<5)
0153 #define RTS5261_LDO3_OCP_THD_680    (0x02<<5)
0154 #define RTS5261_LDO3_OCP_THD_720    (0x03<<5)
0155 #define RTS5261_LDO3_OCP_THD_750    (0x04<<5)
0156 #define RTS5261_LDO3_OCP_THD_780    (0x05<<5)
0157 #define RTS5261_LDO3_OCP_THD_810    (0x06<<5)
0158 #define RTS5261_LDO3_OCP_THD_840    (0x07<<5)
0159
0160 #define RTS5261_LDO3_CFG1       0xFF77
0161 #define RTS5261_LDO3_TUNE_MASK      (0x07<<1)
0162 #define RTS5261_LDO3_18         (0x05<<1)
0163 #define RTS5261_LDO3_33         (0x07<<1)
0164 #define RTS5261_LDO3_PWD_MASK       (0x01<<0)
0165
0166 #define RTS5261_REG_PME_FORCE_CTL   0xFF78
0167 #define FORCE_PM_CONTROL        0x20
0168 #define FORCE_PM_VALUE          0x10
0169 #define REG_EFUSE_BYPASS        0x08
0170 #define REG_EFUSE_POR           0x04
0171 #define REG_EFUSE_POWER_MASK        0x03
0172 #define REG_EFUSE_POWERON       0x03
0173 #define REG_EFUSE_POWEROFF      0x00
0174
0175
0176 /* Single LUN, support SD/SD EXPRESS */
0177 #define DEFAULT_SINGLE      0
0178 #define SD_LUN          1
0179 #define SD_EXPRESS_LUN      2
0180
0181 /* For Change_FPGA_SSCClock Function */
0182 #define MULTIPLY_BY_1    0x00
0183 #define MULTIPLY_BY_2    0x01
0184 #define MULTIPLY_BY_3    0x02
0185 #define MULTIPLY_BY_4    0x03
0186 #define MULTIPLY_BY_5    0x04
0187 #define MULTIPLY_BY_6    0x05
0188 #define MULTIPLY_BY_7    0x06
0189 #define MULTIPLY_BY_8    0x07
0190 #define MULTIPLY_BY_9    0x08
0191 #define MULTIPLY_BY_10   0x09
0192
0193 #define DIVIDE_BY_2      0x01
0194 #define DIVIDE_BY_3      0x02
0195 #define DIVIDE_BY_4      0x03
0196 #define DIVIDE_BY_5      0x04
0197 #define DIVIDE_BY_6      0x05
0198 #define DIVIDE_BY_7      0x06
0199 #define DIVIDE_BY_8      0x07
0200 #define DIVIDE_BY_9      0x08
0201 #define DIVIDE_BY_10     0x09
0202
0203 int rts5261_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
0204         u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
0205
0206 #endif /* RTS5261_H */