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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /* Driver for Realtek PCI-Express card reader
0003  *
0004  * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
0005  *
0006  * Author:
0007  *   Rui FENG <rui_feng@realsil.com.cn>
0008  *   Wei WANG <wei_wang@realsil.com.cn>
0009  */
0010 
0011 #include <linux/module.h>
0012 #include <linux/delay.h>
0013 #include <linux/rtsx_pci.h>
0014 
0015 #include "rts5261.h"
0016 #include "rtsx_pcr.h"
0017 
0018 static u8 rts5261_get_ic_version(struct rtsx_pcr *pcr)
0019 {
0020     u8 val;
0021 
0022     rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
0023     return val & IC_VERSION_MASK;
0024 }
0025 
0026 static void rts5261_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
0027 {
0028     u8 driving_3v3[4][3] = {
0029         {0x96, 0x96, 0x96},
0030         {0x96, 0x96, 0x96},
0031         {0x7F, 0x7F, 0x7F},
0032         {0x13, 0x13, 0x13},
0033     };
0034     u8 driving_1v8[4][3] = {
0035         {0xB3, 0xB3, 0xB3},
0036         {0x3A, 0x3A, 0x3A},
0037         {0xE6, 0xE6, 0xE6},
0038         {0x99, 0x99, 0x99},
0039     };
0040     u8 (*driving)[3], drive_sel;
0041 
0042     if (voltage == OUTPUT_3V3) {
0043         driving = driving_3v3;
0044         drive_sel = pcr->sd30_drive_sel_3v3;
0045     } else {
0046         driving = driving_1v8;
0047         drive_sel = pcr->sd30_drive_sel_1v8;
0048     }
0049 
0050     rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
0051              0xFF, driving[drive_sel][0]);
0052 
0053     rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
0054              0xFF, driving[drive_sel][1]);
0055 
0056     rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
0057              0xFF, driving[drive_sel][2]);
0058 }
0059 
0060 static void rts5261_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
0061 {
0062     /* Set relink_time to 0 */
0063     rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
0064     rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
0065     rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
0066                 RELINK_TIME_MASK, 0);
0067 
0068     if (pm_state == HOST_ENTER_S3)
0069         rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
0070                     D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
0071 
0072     if (!runtime) {
0073         rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1,
0074                 CD_RESUME_EN_MASK, 0);
0075         rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
0076         rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
0077                 FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
0078 
0079     } else {
0080         rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
0081                 FORCE_PM_CONTROL | FORCE_PM_VALUE, 0);
0082 
0083         rtsx_pci_write_register(pcr, RTS5261_FW_CTL,
0084                 RTS5261_INFORM_RTD3_COLD, RTS5261_INFORM_RTD3_COLD);
0085         rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
0086                 RTS5261_FORCE_PRSNT_LOW, RTS5261_FORCE_PRSNT_LOW);
0087 
0088     }
0089 
0090     rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL,
0091         SSC_POWER_DOWN, SSC_POWER_DOWN);
0092 }
0093 
0094 static int rts5261_enable_auto_blink(struct rtsx_pcr *pcr)
0095 {
0096     return rtsx_pci_write_register(pcr, OLT_LED_CTL,
0097         LED_SHINE_MASK, LED_SHINE_EN);
0098 }
0099 
0100 static int rts5261_disable_auto_blink(struct rtsx_pcr *pcr)
0101 {
0102     return rtsx_pci_write_register(pcr, OLT_LED_CTL,
0103         LED_SHINE_MASK, LED_SHINE_DISABLE);
0104 }
0105 
0106 static int rts5261_turn_on_led(struct rtsx_pcr *pcr)
0107 {
0108     return rtsx_pci_write_register(pcr, GPIO_CTL,
0109         0x02, 0x02);
0110 }
0111 
0112 static int rts5261_turn_off_led(struct rtsx_pcr *pcr)
0113 {
0114     return rtsx_pci_write_register(pcr, GPIO_CTL,
0115         0x02, 0x00);
0116 }
0117 
0118 /* SD Pull Control Enable:
0119  *     SD_DAT[3:0] ==> pull up
0120  *     SD_CD       ==> pull up
0121  *     SD_WP       ==> pull up
0122  *     SD_CMD      ==> pull up
0123  *     SD_CLK      ==> pull down
0124  */
0125 static const u32 rts5261_sd_pull_ctl_enable_tbl[] = {
0126     RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
0127     RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
0128     0,
0129 };
0130 
0131 /* SD Pull Control Disable:
0132  *     SD_DAT[3:0] ==> pull down
0133  *     SD_CD       ==> pull up
0134  *     SD_WP       ==> pull down
0135  *     SD_CMD      ==> pull down
0136  *     SD_CLK      ==> pull down
0137  */
0138 static const u32 rts5261_sd_pull_ctl_disable_tbl[] = {
0139     RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
0140     RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
0141     0,
0142 };
0143 
0144 static int rts5261_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
0145 {
0146     rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
0147         | SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
0148     rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
0149     rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
0150             CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
0151     rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
0152 
0153     return 0;
0154 }
0155 
0156 static int rts5261_card_power_on(struct rtsx_pcr *pcr, int card)
0157 {
0158     struct rtsx_cr_option *option = &pcr->option;
0159 
0160     if (option->ocp_en)
0161         rtsx_pci_enable_ocp(pcr);
0162 
0163     rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,
0164         CFG_SD_POW_AUTO_PD, CFG_SD_POW_AUTO_PD);
0165 
0166     rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG1,
0167             RTS5261_LDO1_TUNE_MASK, RTS5261_LDO1_33);
0168     rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
0169             RTS5261_LDO1_POWERON, RTS5261_LDO1_POWERON);
0170 
0171     rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
0172             RTS5261_LDO3318_POWERON, RTS5261_LDO3318_POWERON);
0173 
0174     msleep(20);
0175 
0176     rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
0177 
0178     /* Initialize SD_CFG1 register */
0179     rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
0180             SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1BIT);
0181 
0182     rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
0183             0xFF, SD20_RX_POS_EDGE);
0184     rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
0185     rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
0186             SD_STOP | SD_CLR_ERR);
0187 
0188     /* Reset SD_CFG3 register */
0189     rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
0190     rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
0191             SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 |
0192             SD30_CLK_STOP_CFG0, 0);
0193 
0194     if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
0195         pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
0196         rts5261_sd_set_sample_push_timing_sd30(pcr);
0197 
0198     return 0;
0199 }
0200 
0201 static int rts5261_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
0202 {
0203     int err;
0204     u16 val = 0;
0205 
0206     rtsx_pci_write_register(pcr, RTS5261_CARD_PWR_CTL,
0207             RTS5261_PUPDC, RTS5261_PUPDC);
0208 
0209     switch (voltage) {
0210     case OUTPUT_3V3:
0211         rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
0212         val |= PHY_TUNE_SDBUS_33;
0213         err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
0214         if (err < 0)
0215             return err;
0216 
0217         rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG,
0218                 RTS5261_DV3318_TUNE_MASK, RTS5261_DV3318_33);
0219         rtsx_pci_write_register(pcr, SD_PAD_CTL,
0220                 SD_IO_USING_1V8, 0);
0221         break;
0222     case OUTPUT_1V8:
0223         rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
0224         val &= ~PHY_TUNE_SDBUS_33;
0225         err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
0226         if (err < 0)
0227             return err;
0228 
0229         rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG,
0230                 RTS5261_DV3318_TUNE_MASK, RTS5261_DV3318_18);
0231         rtsx_pci_write_register(pcr, SD_PAD_CTL,
0232                 SD_IO_USING_1V8, SD_IO_USING_1V8);
0233         break;
0234     default:
0235         return -EINVAL;
0236     }
0237 
0238     /* set pad drive */
0239     rts5261_fill_driving(pcr, voltage);
0240 
0241     return 0;
0242 }
0243 
0244 static void rts5261_stop_cmd(struct rtsx_pcr *pcr)
0245 {
0246     rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
0247     rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
0248     rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0,
0249                 RTS5260_DMA_RST | RTS5260_ADMA3_RST,
0250                 RTS5260_DMA_RST | RTS5260_ADMA3_RST);
0251     rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
0252 }
0253 
0254 static void rts5261_card_before_power_off(struct rtsx_pcr *pcr)
0255 {
0256     rts5261_stop_cmd(pcr);
0257     rts5261_switch_output_voltage(pcr, OUTPUT_3V3);
0258 
0259 }
0260 
0261 static void rts5261_enable_ocp(struct rtsx_pcr *pcr)
0262 {
0263     u8 val = 0;
0264 
0265     val = SD_OCP_INT_EN | SD_DETECT_EN;
0266     rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
0267             RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN,
0268             RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN);
0269     rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
0270 
0271 }
0272 
0273 static void rts5261_disable_ocp(struct rtsx_pcr *pcr)
0274 {
0275     u8 mask = 0;
0276 
0277     mask = SD_OCP_INT_EN | SD_DETECT_EN;
0278     rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
0279     rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
0280             RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN, 0);
0281 
0282 }
0283 
0284 static int rts5261_card_power_off(struct rtsx_pcr *pcr, int card)
0285 {
0286     int err = 0;
0287 
0288     rts5261_card_before_power_off(pcr);
0289     err = rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
0290                 RTS5261_LDO_POWERON_MASK, 0);
0291 
0292     rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,
0293         CFG_SD_POW_AUTO_PD, 0);
0294     if (pcr->option.ocp_en)
0295         rtsx_pci_disable_ocp(pcr);
0296 
0297     return err;
0298 }
0299 
0300 static void rts5261_init_ocp(struct rtsx_pcr *pcr)
0301 {
0302     struct rtsx_cr_option *option = &pcr->option;
0303 
0304     if (option->ocp_en) {
0305         u8 mask, val;
0306 
0307         rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
0308             RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN,
0309             RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN);
0310 
0311         rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
0312             RTS5261_LDO1_OCP_THD_MASK, option->sd_800mA_ocp_thd);
0313 
0314         rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
0315             RTS5261_LDO1_OCP_LMT_THD_MASK,
0316             RTS5261_LDO1_LMT_THD_2000);
0317 
0318         mask = SD_OCP_GLITCH_MASK;
0319         val = pcr->hw_param.ocp_glitch;
0320         rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
0321 
0322         rts5261_enable_ocp(pcr);
0323     } else {
0324         rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
0325             RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN, 0);
0326     }
0327 }
0328 
0329 static void rts5261_clear_ocpstat(struct rtsx_pcr *pcr)
0330 {
0331     u8 mask = 0;
0332     u8 val = 0;
0333 
0334     mask = SD_OCP_INT_CLR | SD_OC_CLR;
0335     val = SD_OCP_INT_CLR | SD_OC_CLR;
0336 
0337     rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
0338 
0339     udelay(1000);
0340     rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
0341 
0342 }
0343 
0344 static void rts5261_process_ocp(struct rtsx_pcr *pcr)
0345 {
0346     if (!pcr->option.ocp_en)
0347         return;
0348 
0349     rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
0350 
0351     if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
0352         rts5261_clear_ocpstat(pcr);
0353         rts5261_card_power_off(pcr, RTSX_SD_CARD);
0354         rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
0355         pcr->ocp_stat = 0;
0356     }
0357 
0358 }
0359 
0360 static void rts5261_init_from_hw(struct rtsx_pcr *pcr)
0361 {
0362     struct pci_dev *pdev = pcr->pci;
0363     u32 lval1, lval2, i;
0364     u16 setting_reg1, setting_reg2;
0365     u8 valid, efuse_valid, tmp;
0366 
0367     rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
0368         REG_EFUSE_POR | REG_EFUSE_POWER_MASK,
0369         REG_EFUSE_POR | REG_EFUSE_POWERON);
0370     udelay(1);
0371     rtsx_pci_write_register(pcr, RTS5261_EFUSE_ADDR,
0372         RTS5261_EFUSE_ADDR_MASK, 0x00);
0373     rtsx_pci_write_register(pcr, RTS5261_EFUSE_CTL,
0374         RTS5261_EFUSE_ENABLE | RTS5261_EFUSE_MODE_MASK,
0375         RTS5261_EFUSE_ENABLE);
0376 
0377     /* Wait transfer end */
0378     for (i = 0; i < MAX_RW_REG_CNT; i++) {
0379         rtsx_pci_read_register(pcr, RTS5261_EFUSE_CTL, &tmp);
0380         if ((tmp & 0x80) == 0)
0381             break;
0382     }
0383     rtsx_pci_read_register(pcr, RTS5261_EFUSE_READ_DATA, &tmp);
0384     efuse_valid = ((tmp & 0x0C) >> 2);
0385     pcr_dbg(pcr, "Load efuse valid: 0x%x\n", efuse_valid);
0386 
0387     pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval2);
0388     pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, lval2);
0389     /* 0x816 */
0390     valid = (u8)((lval2 >> 16) & 0x03);
0391 
0392     rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
0393         REG_EFUSE_POR, 0);
0394     pcr_dbg(pcr, "Disable efuse por!\n");
0395 
0396     if (efuse_valid == 2 || efuse_valid == 3) {
0397         if (valid == 3) {
0398             /* Bypass efuse */
0399             setting_reg1 = PCR_SETTING_REG1;
0400             setting_reg2 = PCR_SETTING_REG2;
0401         } else {
0402             /* Use efuse data */
0403             setting_reg1 = PCR_SETTING_REG4;
0404             setting_reg2 = PCR_SETTING_REG5;
0405         }
0406     } else if (efuse_valid == 0) {
0407         // default
0408         setting_reg1 = PCR_SETTING_REG1;
0409         setting_reg2 = PCR_SETTING_REG2;
0410     } else {
0411         return;
0412     }
0413 
0414     pci_read_config_dword(pdev, setting_reg2, &lval2);
0415     pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg2, lval2);
0416 
0417     if (!rts5261_vendor_setting_valid(lval2)) {
0418         /* Not support MMC default */
0419         pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
0420         pcr_dbg(pcr, "skip fetch vendor setting\n");
0421         return;
0422     }
0423 
0424     if (!rts5261_reg_check_mmc_support(lval2))
0425         pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
0426 
0427     pcr->rtd3_en = rts5261_reg_to_rtd3(lval2);
0428 
0429     if (rts5261_reg_check_reverse_socket(lval2))
0430         pcr->flags |= PCR_REVERSE_SOCKET;
0431 
0432     pci_read_config_dword(pdev, setting_reg1, &lval1);
0433     pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg1, lval1);
0434 
0435     pcr->aspm_en = rts5261_reg_to_aspm(lval1);
0436     pcr->sd30_drive_sel_1v8 = rts5261_reg_to_sd30_drive_sel_1v8(lval1);
0437     pcr->sd30_drive_sel_3v3 = rts5261_reg_to_sd30_drive_sel_3v3(lval1);
0438 
0439     if (setting_reg1 == PCR_SETTING_REG1) {
0440         /* store setting */
0441         rtsx_pci_write_register(pcr, 0xFF0C, 0xFF, (u8)(lval1 & 0xFF));
0442         rtsx_pci_write_register(pcr, 0xFF0D, 0xFF, (u8)((lval1 >> 8) & 0xFF));
0443         rtsx_pci_write_register(pcr, 0xFF0E, 0xFF, (u8)((lval1 >> 16) & 0xFF));
0444         rtsx_pci_write_register(pcr, 0xFF0F, 0xFF, (u8)((lval1 >> 24) & 0xFF));
0445         rtsx_pci_write_register(pcr, 0xFF10, 0xFF, (u8)(lval2 & 0xFF));
0446         rtsx_pci_write_register(pcr, 0xFF11, 0xFF, (u8)((lval2 >> 8) & 0xFF));
0447         rtsx_pci_write_register(pcr, 0xFF12, 0xFF, (u8)((lval2 >> 16) & 0xFF));
0448 
0449         pci_write_config_dword(pdev, PCR_SETTING_REG4, lval1);
0450         lval2 = lval2 & 0x00FFFFFF;
0451         pci_write_config_dword(pdev, PCR_SETTING_REG5, lval2);
0452     }
0453 }
0454 
0455 static void rts5261_init_from_cfg(struct rtsx_pcr *pcr)
0456 {
0457     struct pci_dev *pdev = pcr->pci;
0458     int l1ss;
0459     u32 lval;
0460     struct rtsx_cr_option *option = &pcr->option;
0461 
0462     l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
0463     if (!l1ss)
0464         return;
0465 
0466     pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
0467 
0468     if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
0469         rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
0470     else
0471         rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
0472 
0473     if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
0474         rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
0475     else
0476         rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
0477 
0478     if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
0479         rtsx_set_dev_flag(pcr, PM_L1_1_EN);
0480     else
0481         rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
0482 
0483     if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
0484         rtsx_set_dev_flag(pcr, PM_L1_2_EN);
0485     else
0486         rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
0487 
0488     rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
0489     if (option->ltr_en) {
0490         u16 val;
0491 
0492         pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val);
0493         if (val & PCI_EXP_DEVCTL2_LTR_EN) {
0494             option->ltr_enabled = true;
0495             option->ltr_active = true;
0496             rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
0497         } else {
0498             option->ltr_enabled = false;
0499         }
0500     }
0501 
0502     if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
0503                 | PM_L1_1_EN | PM_L1_2_EN))
0504         option->force_clkreq_0 = false;
0505     else
0506         option->force_clkreq_0 = true;
0507 }
0508 
0509 static int rts5261_extra_init_hw(struct rtsx_pcr *pcr)
0510 {
0511     struct rtsx_cr_option *option = &pcr->option;
0512     u32 val;
0513 
0514     rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1,
0515             CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
0516 
0517     rts5261_init_from_cfg(pcr);
0518     rts5261_init_from_hw(pcr);
0519 
0520     /* power off efuse */
0521     rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
0522             REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF);
0523     rtsx_pci_write_register(pcr, L1SUB_CONFIG1,
0524             AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE);
0525     rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0);
0526 
0527     if (is_version_higher_than(pcr, PID_5261, IC_VER_B)) {
0528         val = rtsx_pci_readl(pcr, RTSX_DUM_REG);
0529         rtsx_pci_writel(pcr, RTSX_DUM_REG, val | 0x1);
0530     }
0531     rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
0532             RTS5261_AUX_CLK_16M_EN, 0);
0533 
0534     /* Release PRSNT# */
0535     rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
0536             RTS5261_FORCE_PRSNT_LOW, 0);
0537     rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
0538             FUNC_FORCE_UPME_XMT_DBG, FUNC_FORCE_UPME_XMT_DBG);
0539 
0540     rtsx_pci_write_register(pcr, PCLK_CTL,
0541             PCLK_MODE_SEL, PCLK_MODE_SEL);
0542 
0543     rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
0544     rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, CLK_PM_EN, CLK_PM_EN);
0545 
0546     /* LED shine disabled, set initial shine cycle period */
0547     rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02);
0548 
0549     /* Configure driving */
0550     rts5261_fill_driving(pcr, OUTPUT_3V3);
0551 
0552     if (pcr->flags & PCR_REVERSE_SOCKET)
0553         rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30);
0554     else
0555         rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);
0556 
0557     /*
0558      * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
0559      * to drive low, and we forcibly request clock.
0560      */
0561     if (option->force_clkreq_0)
0562         rtsx_pci_write_register(pcr, PETXCFG,
0563                  FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
0564     else
0565         rtsx_pci_write_register(pcr, PETXCFG,
0566                  FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
0567 
0568     rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB);
0569 
0570     if (pcr->rtd3_en) {
0571         rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x01);
0572         rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
0573                 FORCE_PM_CONTROL | FORCE_PM_VALUE,
0574                 FORCE_PM_CONTROL | FORCE_PM_VALUE);
0575     } else {
0576         rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
0577         rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
0578                 FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
0579     }
0580     rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, D3_DELINK_MODE_EN, 0x00);
0581 
0582     /* Clear Enter RTD3_cold Information*/
0583     rtsx_pci_write_register(pcr, RTS5261_FW_CTL,
0584         RTS5261_INFORM_RTD3_COLD, 0);
0585 
0586     return 0;
0587 }
0588 
0589 static void rts5261_enable_aspm(struct rtsx_pcr *pcr, bool enable)
0590 {
0591     u8 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
0592     u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
0593 
0594     if (pcr->aspm_enabled == enable)
0595         return;
0596 
0597     val |= (pcr->aspm_en & 0x02);
0598     rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
0599     pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
0600                        PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en);
0601     pcr->aspm_enabled = enable;
0602 }
0603 
0604 static void rts5261_disable_aspm(struct rtsx_pcr *pcr, bool enable)
0605 {
0606     u8 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
0607     u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
0608 
0609     if (pcr->aspm_enabled == enable)
0610         return;
0611 
0612     pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
0613                        PCI_EXP_LNKCTL_ASPMC, 0);
0614     rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
0615     rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
0616     udelay(10);
0617     pcr->aspm_enabled = enable;
0618 }
0619 
0620 static void rts5261_set_aspm(struct rtsx_pcr *pcr, bool enable)
0621 {
0622     if (enable)
0623         rts5261_enable_aspm(pcr, true);
0624     else
0625         rts5261_disable_aspm(pcr, false);
0626 }
0627 
0628 static void rts5261_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
0629 {
0630     struct rtsx_cr_option *option = &pcr->option;
0631     int aspm_L1_1, aspm_L1_2;
0632     u8 val = 0;
0633 
0634     aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
0635     aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
0636 
0637     if (active) {
0638         /* run, latency: 60us */
0639         if (aspm_L1_1)
0640             val = option->ltr_l1off_snooze_sspwrgate;
0641     } else {
0642         /* l1off, latency: 300us */
0643         if (aspm_L1_2)
0644             val = option->ltr_l1off_sspwrgate;
0645     }
0646 
0647     rtsx_set_l1off_sub(pcr, val);
0648 }
0649 
0650 static const struct pcr_ops rts5261_pcr_ops = {
0651     .turn_on_led = rts5261_turn_on_led,
0652     .turn_off_led = rts5261_turn_off_led,
0653     .extra_init_hw = rts5261_extra_init_hw,
0654     .enable_auto_blink = rts5261_enable_auto_blink,
0655     .disable_auto_blink = rts5261_disable_auto_blink,
0656     .card_power_on = rts5261_card_power_on,
0657     .card_power_off = rts5261_card_power_off,
0658     .switch_output_voltage = rts5261_switch_output_voltage,
0659     .force_power_down = rts5261_force_power_down,
0660     .stop_cmd = rts5261_stop_cmd,
0661     .set_aspm = rts5261_set_aspm,
0662     .set_l1off_cfg_sub_d0 = rts5261_set_l1off_cfg_sub_d0,
0663     .enable_ocp = rts5261_enable_ocp,
0664     .disable_ocp = rts5261_disable_ocp,
0665     .init_ocp = rts5261_init_ocp,
0666     .process_ocp = rts5261_process_ocp,
0667     .clear_ocpstat = rts5261_clear_ocpstat,
0668 };
0669 
0670 static inline u8 double_ssc_depth(u8 depth)
0671 {
0672     return ((depth > 1) ? (depth - 1) : depth);
0673 }
0674 
0675 int rts5261_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
0676         u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
0677 {
0678     int err, clk;
0679     u16 n;
0680     u8 clk_divider, mcu_cnt, div;
0681     static const u8 depth[] = {
0682         [RTSX_SSC_DEPTH_4M] = RTS5261_SSC_DEPTH_4M,
0683         [RTSX_SSC_DEPTH_2M] = RTS5261_SSC_DEPTH_2M,
0684         [RTSX_SSC_DEPTH_1M] = RTS5261_SSC_DEPTH_1M,
0685         [RTSX_SSC_DEPTH_500K] = RTS5261_SSC_DEPTH_512K,
0686     };
0687 
0688     if (initial_mode) {
0689         /* We use 250k(around) here, in initial stage */
0690         if (is_version_higher_than(pcr, PID_5261, IC_VER_C)) {
0691             clk_divider = SD_CLK_DIVIDE_256;
0692             card_clock = 60000000;
0693         } else {
0694             clk_divider = SD_CLK_DIVIDE_128;
0695             card_clock = 30000000;
0696         }
0697     } else {
0698         clk_divider = SD_CLK_DIVIDE_0;
0699     }
0700     err = rtsx_pci_write_register(pcr, SD_CFG1,
0701             SD_CLK_DIVIDE_MASK, clk_divider);
0702     if (err < 0)
0703         return err;
0704 
0705     card_clock /= 1000000;
0706     pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
0707 
0708     clk = card_clock;
0709     if (!initial_mode && double_clk)
0710         clk = card_clock * 2;
0711     pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
0712         clk, pcr->cur_clock);
0713 
0714     if (clk == pcr->cur_clock)
0715         return 0;
0716 
0717     if (pcr->ops->conv_clk_and_div_n)
0718         n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
0719     else
0720         n = clk - 4;
0721     if ((clk <= 4) || (n > 396))
0722         return -EINVAL;
0723 
0724     mcu_cnt = 125/clk + 3;
0725     if (mcu_cnt > 15)
0726         mcu_cnt = 15;
0727 
0728     div = CLK_DIV_1;
0729     while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) {
0730         if (pcr->ops->conv_clk_and_div_n) {
0731             int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
0732                     DIV_N_TO_CLK) * 2;
0733             n = pcr->ops->conv_clk_and_div_n(dbl_clk,
0734                     CLK_TO_DIV_N);
0735         } else {
0736             n = (n + 4) * 2 - 4;
0737         }
0738         div++;
0739     }
0740 
0741     n = (n / 2) - 1;
0742     pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
0743 
0744     ssc_depth = depth[ssc_depth];
0745     if (double_clk)
0746         ssc_depth = double_ssc_depth(ssc_depth);
0747 
0748     if (ssc_depth) {
0749         if (div == CLK_DIV_2) {
0750             if (ssc_depth > 1)
0751                 ssc_depth -= 1;
0752             else
0753                 ssc_depth = RTS5261_SSC_DEPTH_8M;
0754         } else if (div == CLK_DIV_4) {
0755             if (ssc_depth > 2)
0756                 ssc_depth -= 2;
0757             else
0758                 ssc_depth = RTS5261_SSC_DEPTH_8M;
0759         } else if (div == CLK_DIV_8) {
0760             if (ssc_depth > 3)
0761                 ssc_depth -= 3;
0762             else
0763                 ssc_depth = RTS5261_SSC_DEPTH_8M;
0764         }
0765     } else {
0766         ssc_depth = 0;
0767     }
0768     pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
0769 
0770     rtsx_pci_init_cmd(pcr);
0771     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
0772                 CLK_LOW_FREQ, CLK_LOW_FREQ);
0773     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
0774             0xFF, (div << 4) | mcu_cnt);
0775     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
0776     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
0777             SSC_DEPTH_MASK, ssc_depth);
0778     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
0779     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
0780     if (vpclk) {
0781         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
0782                 PHASE_NOT_RESET, 0);
0783         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
0784                 PHASE_NOT_RESET, 0);
0785         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
0786                 PHASE_NOT_RESET, PHASE_NOT_RESET);
0787         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
0788                 PHASE_NOT_RESET, PHASE_NOT_RESET);
0789     }
0790 
0791     err = rtsx_pci_send_cmd(pcr, 2000);
0792     if (err < 0)
0793         return err;
0794 
0795     /* Wait SSC clock stable */
0796     udelay(SSC_CLOCK_STABLE_WAIT);
0797     err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
0798     if (err < 0)
0799         return err;
0800 
0801     pcr->cur_clock = clk;
0802     return 0;
0803 
0804 }
0805 
0806 void rts5261_init_params(struct rtsx_pcr *pcr)
0807 {
0808     struct rtsx_cr_option *option = &pcr->option;
0809     struct rtsx_hw_param *hw_param = &pcr->hw_param;
0810     u8 val;
0811 
0812     pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
0813     rtsx_pci_read_register(pcr, RTS5261_FW_STATUS, &val);
0814     if (!(val & RTS5261_EXPRESS_LINK_FAIL_MASK))
0815         pcr->extra_caps |= EXTRA_CAPS_SD_EXPRESS;
0816     pcr->num_slots = 1;
0817     pcr->ops = &rts5261_pcr_ops;
0818 
0819     pcr->flags = 0;
0820     pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
0821     pcr->sd30_drive_sel_1v8 = 0x00;
0822     pcr->sd30_drive_sel_3v3 = 0x00;
0823     pcr->aspm_en = ASPM_L1_EN;
0824     pcr->aspm_mode = ASPM_MODE_REG;
0825     pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 11);
0826     pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
0827 
0828     pcr->ic_version = rts5261_get_ic_version(pcr);
0829     pcr->sd_pull_ctl_enable_tbl = rts5261_sd_pull_ctl_enable_tbl;
0830     pcr->sd_pull_ctl_disable_tbl = rts5261_sd_pull_ctl_disable_tbl;
0831 
0832     pcr->reg_pm_ctrl3 = RTS5261_AUTOLOAD_CFG3;
0833 
0834     option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
0835                 | LTR_L1SS_PWR_GATE_EN);
0836     option->ltr_en = true;
0837 
0838     /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
0839     option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
0840     option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
0841     option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
0842     option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
0843     option->ltr_l1off_sspwrgate = 0x7F;
0844     option->ltr_l1off_snooze_sspwrgate = 0x78;
0845 
0846     option->ocp_en = 1;
0847     hw_param->interrupt_en |= SD_OC_INT_EN;
0848     hw_param->ocp_glitch =  SD_OCP_GLITCH_800U;
0849     option->sd_800mA_ocp_thd =  RTS5261_LDO1_OCP_THD_1040;
0850 }
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