0001 #ifndef __RTS5260_H__
0002 #define __RTS5260_H__
0003
0004 #define RTS5260_DVCC_CTRL 0xFF73
0005 #define RTS5260_DVCC_OCP_EN (0x01 << 7)
0006 #define RTS5260_DVCC_OCP_THD_MASK (0x07 << 4)
0007 #define RTS5260_DVCC_POWERON (0x01 << 3)
0008 #define RTS5260_DVCC_OCP_CL_EN (0x01 << 2)
0009
0010 #define RTS5260_DVIO_CTRL 0xFF75
0011 #define RTS5260_DVIO_OCP_EN (0x01 << 7)
0012 #define RTS5260_DVIO_OCP_THD_MASK (0x07 << 4)
0013 #define RTS5260_DVIO_POWERON (0x01 << 3)
0014 #define RTS5260_DVIO_OCP_CL_EN (0x01 << 2)
0015
0016 #define RTS5260_DV331812_CFG 0xFF71
0017 #define RTS5260_DV331812_OCP_EN (0x01 << 7)
0018 #define RTS5260_DV331812_OCP_THD_MASK (0x07 << 4)
0019 #define RTS5260_DV331812_POWERON (0x01 << 3)
0020 #define RTS5260_DV331812_SEL (0x01 << 2)
0021 #define RTS5260_DV331812_VDD1 (0x01 << 2)
0022 #define RTS5260_DV331812_VDD2 (0x00 << 2)
0023
0024 #define RTS5260_DV331812_OCP_THD_120 (0x00 << 4)
0025 #define RTS5260_DV331812_OCP_THD_140 (0x01 << 4)
0026 #define RTS5260_DV331812_OCP_THD_160 (0x02 << 4)
0027 #define RTS5260_DV331812_OCP_THD_180 (0x03 << 4)
0028 #define RTS5260_DV331812_OCP_THD_210 (0x04 << 4)
0029 #define RTS5260_DV331812_OCP_THD_240 (0x05 << 4)
0030 #define RTS5260_DV331812_OCP_THD_270 (0x06 << 4)
0031 #define RTS5260_DV331812_OCP_THD_300 (0x07 << 4)
0032
0033 #define RTS5260_DVIO_OCP_THD_250 (0x00 << 4)
0034 #define RTS5260_DVIO_OCP_THD_300 (0x01 << 4)
0035 #define RTS5260_DVIO_OCP_THD_350 (0x02 << 4)
0036 #define RTS5260_DVIO_OCP_THD_400 (0x03 << 4)
0037 #define RTS5260_DVIO_OCP_THD_450 (0x04 << 4)
0038 #define RTS5260_DVIO_OCP_THD_500 (0x05 << 4)
0039 #define RTS5260_DVIO_OCP_THD_550 (0x06 << 4)
0040 #define RTS5260_DVIO_OCP_THD_600 (0x07 << 4)
0041
0042 #define RTS5260_DVCC_OCP_THD_550 (0x00 << 4)
0043 #define RTS5260_DVCC_OCP_THD_970 (0x05 << 4)
0044
0045 #endif
