misc/cardreader/rts5260.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /* Driver for Realtek PCI-Express card reader
0003  *
0004  * Copyright(c) 2016-2017 Realtek Semiconductor Corp. All rights reserved.
0005  *
0006  * Author:
0007  *   Steven FENG <steven_feng@realsil.com.cn>
0008  *   Rui FENG <rui_feng@realsil.com.cn>
0009  *   Wei WANG <wei_wang@realsil.com.cn>
0010  */
0011
0012 #include <linux/module.h>
0013 #include <linux/delay.h>
0014 #include <linux/rtsx_pci.h>
0015
0016 #include "rts5260.h"
0017 #include "rtsx_pcr.h"
0018
0019 static u8 rts5260_get_ic_version(struct rtsx_pcr *pcr)
0020 {
0021     u8 val;
0022
0023     rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
0024     return val & IC_VERSION_MASK;
0025 }
0026
0027 static void rts5260_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
0028 {
0029     u8 driving_3v3[4][3] = {
0030         {0x11, 0x11, 0x11},
0031         {0x22, 0x22, 0x22},
0032         {0x55, 0x55, 0x55},
0033         {0x33, 0x33, 0x33},
0034     };
0035     u8 driving_1v8[4][3] = {
0036         {0x35, 0x33, 0x33},
0037         {0x8A, 0x88, 0x88},
0038         {0xBD, 0xBB, 0xBB},
0039         {0x9B, 0x99, 0x99},
0040     };
0041     u8 (*driving)[3], drive_sel;
0042
0043     if (voltage == OUTPUT_3V3) {
0044         driving = driving_3v3;
0045         drive_sel = pcr->sd30_drive_sel_3v3;
0046     } else {
0047         driving = driving_1v8;
0048         drive_sel = pcr->sd30_drive_sel_1v8;
0049     }
0050
0051     rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
0052              0xFF, driving[drive_sel][0]);
0053
0054     rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
0055              0xFF, driving[drive_sel][1]);
0056
0057     rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
0058              0xFF, driving[drive_sel][2]);
0059 }
0060
0061 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
0062 {
0063     struct pci_dev *pdev = pcr->pci;
0064     u32 reg;
0065
0066     pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
0067     pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
0068
0069     if (!rtsx_vendor_setting_valid(reg)) {
0070         pcr_dbg(pcr, "skip fetch vendor setting\n");
0071         return;
0072     }
0073
0074     pcr->aspm_en = rtsx_reg_to_aspm(reg);
0075     pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
0076     pcr->card_drive_sel &= 0x3F;
0077     pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
0078
0079     pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
0080     pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
0081     if (rtsx_check_mmc_support(reg))
0082         pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
0083     pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
0084     if (rtsx_reg_check_reverse_socket(reg))
0085         pcr->flags |= PCR_REVERSE_SOCKET;
0086 }
0087
0088 static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
0089 {
0090     return rtsx_pci_write_register(pcr, OLT_LED_CTL,
0091         LED_SHINE_MASK, LED_SHINE_EN);
0092 }
0093
0094 static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
0095 {
0096     return rtsx_pci_write_register(pcr, OLT_LED_CTL,
0097         LED_SHINE_MASK, LED_SHINE_DISABLE);
0098 }
0099
0100 static int rts5260_turn_on_led(struct rtsx_pcr *pcr)
0101 {
0102     return rtsx_pci_write_register(pcr, RTS5260_REG_GPIO_CTL0,
0103         RTS5260_REG_GPIO_MASK, RTS5260_REG_GPIO_ON);
0104 }
0105
0106 static int rts5260_turn_off_led(struct rtsx_pcr *pcr)
0107 {
0108     return rtsx_pci_write_register(pcr, RTS5260_REG_GPIO_CTL0,
0109         RTS5260_REG_GPIO_MASK, RTS5260_REG_GPIO_OFF);
0110 }
0111
0112 /* SD Pull Control Enable:
0113  *     SD_DAT[3:0] ==> pull up
0114  *     SD_CD       ==> pull up
0115  *     SD_WP       ==> pull up
0116  *     SD_CMD      ==> pull up
0117  *     SD_CLK      ==> pull down
0118  */
0119 static const u32 rts5260_sd_pull_ctl_enable_tbl[] = {
0120     RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
0121     RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
0122     RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
0123     RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
0124     0,
0125 };
0126
0127 /* SD Pull Control Disable:
0128  *     SD_DAT[3:0] ==> pull down
0129  *     SD_CD       ==> pull up
0130  *     SD_WP       ==> pull down
0131  *     SD_CMD      ==> pull down
0132  *     SD_CLK      ==> pull down
0133  */
0134 static const u32 rts5260_sd_pull_ctl_disable_tbl[] = {
0135     RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
0136     RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
0137     RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
0138     RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
0139     0,
0140 };
0141
0142 /* MS Pull Control Enable:
0143  *     MS CD       ==> pull up
0144  *     others      ==> pull down
0145  */
0146 static const u32 rts5260_ms_pull_ctl_enable_tbl[] = {
0147     RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
0148     RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
0149     RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
0150     0,
0151 };
0152
0153 /* MS Pull Control Disable:
0154  *     MS CD       ==> pull up
0155  *     others      ==> pull down
0156  */
0157 static const u32 rts5260_ms_pull_ctl_disable_tbl[] = {
0158     RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
0159     RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
0160     RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
0161     0,
0162 };
0163
0164 static int sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
0165 {
0166     rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
0167         | SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
0168     rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
0169     rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
0170             CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
0171     rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
0172
0173     return 0;
0174 }
0175
0176 static int rts5260_card_power_on(struct rtsx_pcr *pcr, int card)
0177 {
0178     struct rtsx_cr_option *option = &pcr->option;
0179
0180     if (option->ocp_en)
0181         rtsx_pci_enable_ocp(pcr);
0182
0183
0184     rtsx_pci_write_register(pcr, LDO_CONFIG2, DV331812_VDD1, DV331812_VDD1);
0185     rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
0186              RTS5260_DVCC_TUNE_MASK, RTS5260_DVCC_33);
0187
0188     rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_POW_SDVDD1_MASK,
0189             LDO_POW_SDVDD1_ON);
0190
0191     rtsx_pci_write_register(pcr, LDO_CONFIG2,
0192              DV331812_POWERON, DV331812_POWERON);
0193     msleep(20);
0194
0195     if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
0196         pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
0197         sd_set_sample_push_timing_sd30(pcr);
0198
0199     /* Initialize SD_CFG1 register */
0200     rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
0201                 SD_CLK_DIVIDE_128 | SD_20_MODE);
0202
0203     rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
0204                 0xFF, SD20_RX_POS_EDGE);
0205     rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
0206     rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
0207                 SD_STOP | SD_CLR_ERR);
0208
0209     /* Reset SD_CFG3 register */
0210     rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
0211     rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
0212             SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 |
0213             SD30_CLK_STOP_CFG0, 0);
0214
0215     rtsx_pci_write_register(pcr, REG_PRE_RW_MODE, EN_INFINITE_MODE, 0);
0216
0217     return 0;
0218 }
0219
0220 static int rts5260_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
0221 {
0222     switch (voltage) {
0223     case OUTPUT_3V3:
0224         rtsx_pci_write_register(pcr, LDO_CONFIG2,
0225                     DV331812_VDD1, DV331812_VDD1);
0226         rtsx_pci_write_register(pcr, LDO_DV18_CFG,
0227                     DV331812_MASK, DV331812_33);
0228         rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);
0229         break;
0230     case OUTPUT_1V8:
0231         rtsx_pci_write_register(pcr, LDO_CONFIG2,
0232                     DV331812_VDD1, DV331812_VDD1);
0233         rtsx_pci_write_register(pcr, LDO_DV18_CFG,
0234                     DV331812_MASK, DV331812_17);
0235         rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,
0236                     SD_IO_USING_1V8);
0237         break;
0238     default:
0239         return -EINVAL;
0240     }
0241
0242     /* set pad drive */
0243     rts5260_fill_driving(pcr, voltage);
0244
0245     return 0;
0246 }
0247
0248 static void rts5260_stop_cmd(struct rtsx_pcr *pcr)
0249 {
0250     rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
0251     rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
0252     rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0,
0253                 RTS5260_DMA_RST | RTS5260_ADMA3_RST,
0254                 RTS5260_DMA_RST | RTS5260_ADMA3_RST);
0255     rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
0256 }
0257
0258 static void rts5260_card_before_power_off(struct rtsx_pcr *pcr)
0259 {
0260     rts5260_stop_cmd(pcr);
0261     rts5260_switch_output_voltage(pcr, OUTPUT_3V3);
0262
0263 }
0264
0265 static int rts5260_card_power_off(struct rtsx_pcr *pcr, int card)
0266 {
0267     int err = 0;
0268
0269     rts5260_card_before_power_off(pcr);
0270     err = rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
0271              LDO_POW_SDVDD1_MASK, LDO_POW_SDVDD1_OFF);
0272     err = rtsx_pci_write_register(pcr, LDO_CONFIG2,
0273              DV331812_POWERON, DV331812_POWEROFF);
0274     if (pcr->option.ocp_en)
0275         rtsx_pci_disable_ocp(pcr);
0276
0277     return err;
0278 }
0279
0280 static void rts5260_init_ocp(struct rtsx_pcr *pcr)
0281 {
0282     struct rtsx_cr_option *option = &pcr->option;
0283
0284     if (option->ocp_en) {
0285         u8 mask, val;
0286
0287
0288         rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
0289                 RTS5260_DVCC_OCP_THD_MASK,
0290                 option->sd_800mA_ocp_thd);
0291
0292         rtsx_pci_write_register(pcr, RTS5260_DV331812_CFG,
0293                 RTS5260_DV331812_OCP_THD_MASK,
0294                 RTS5260_DV331812_OCP_THD_270);
0295
0296         mask = SD_OCP_GLITCH_MASK;
0297         val = pcr->hw_param.ocp_glitch;
0298         rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
0299         rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
0300                     RTS5260_DVCC_OCP_EN |
0301                     RTS5260_DVCC_OCP_CL_EN,
0302                     RTS5260_DVCC_OCP_EN |
0303                     RTS5260_DVCC_OCP_CL_EN);
0304
0305         rtsx_pci_enable_ocp(pcr);
0306     } else {
0307         rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
0308                     RTS5260_DVCC_OCP_EN |
0309                     RTS5260_DVCC_OCP_CL_EN, 0);
0310     }
0311 }
0312
0313 static void rts5260_enable_ocp(struct rtsx_pcr *pcr)
0314 {
0315     u8 val = 0;
0316
0317     val = SD_OCP_INT_EN | SD_DETECT_EN;
0318     rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
0319
0320 }
0321
0322 static void rts5260_disable_ocp(struct rtsx_pcr *pcr)
0323 {
0324     u8 mask = 0;
0325
0326     mask = SD_OCP_INT_EN | SD_DETECT_EN;
0327     rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
0328
0329 }
0330
0331
0332 static int rts5260_get_ocpstat(struct rtsx_pcr *pcr, u8 *val)
0333 {
0334     return rtsx_pci_read_register(pcr, REG_OCPSTAT, val);
0335 }
0336
0337 static int rts5260_get_ocpstat2(struct rtsx_pcr *pcr, u8 *val)
0338 {
0339     return rtsx_pci_read_register(pcr, REG_DV3318_OCPSTAT, val);
0340 }
0341
0342 static void rts5260_clear_ocpstat(struct rtsx_pcr *pcr)
0343 {
0344     u8 mask = 0;
0345     u8 val = 0;
0346
0347     mask = SD_OCP_INT_CLR | SD_OC_CLR;
0348     val = SD_OCP_INT_CLR | SD_OC_CLR;
0349
0350     rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
0351     rtsx_pci_write_register(pcr, REG_DV3318_OCPCTL,
0352                 DV3318_OCP_INT_CLR | DV3318_OCP_CLR,
0353                 DV3318_OCP_INT_CLR | DV3318_OCP_CLR);
0354     udelay(10);
0355     rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
0356     rtsx_pci_write_register(pcr, REG_DV3318_OCPCTL,
0357                 DV3318_OCP_INT_CLR | DV3318_OCP_CLR, 0);
0358 }
0359
0360 static void rts5260_process_ocp(struct rtsx_pcr *pcr)
0361 {
0362     if (!pcr->option.ocp_en)
0363         return;
0364
0365     rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
0366     rts5260_get_ocpstat2(pcr, &pcr->ocp_stat2);
0367
0368     if ((pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) ||
0369         (pcr->ocp_stat2 & (DV3318_OCP_NOW | DV3318_OCP_EVER))) {
0370         rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
0371         rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
0372         rtsx_pci_clear_ocpstat(pcr);
0373         pcr->ocp_stat = 0;
0374         pcr->ocp_stat2 = 0;
0375     }
0376
0377 }
0378
0379 static int rts5260_init_hw(struct rtsx_pcr *pcr)
0380 {
0381     int err;
0382
0383     rtsx_pci_init_cmd(pcr);
0384
0385     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG1,
0386              AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE);
0387     /* Rest L1SUB Config */
0388     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
0389     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CLK_FORCE_CTL,
0390              CLK_PM_EN, CLK_PM_EN);
0391     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWD_SUSPEND_EN, 0xFF, 0xFF);
0392     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
0393              PWR_GATE_EN, PWR_GATE_EN);
0394     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, REG_VREF,
0395              PWD_SUSPND_EN, PWD_SUSPND_EN);
0396     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RBCTL,
0397              U_AUTO_DMA_EN_MASK, U_AUTO_DMA_DISABLE);
0398
0399     if (pcr->flags & PCR_REVERSE_SOCKET)
0400         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
0401     else
0402         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
0403
0404     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG,
0405              OBFF_EN_MASK, OBFF_DISABLE);
0406
0407     err = rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
0408     if (err < 0)
0409         return err;
0410
0411     rtsx_pci_init_ocp(pcr);
0412
0413     return 0;
0414 }
0415
0416 static void rts5260_pwr_saving_setting(struct rtsx_pcr *pcr)
0417 {
0418     int lss_l1_1, lss_l1_2;
0419
0420     lss_l1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN)
0421             | rtsx_check_dev_flag(pcr, PM_L1_1_EN);
0422     lss_l1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN)
0423             | rtsx_check_dev_flag(pcr, PM_L1_2_EN);
0424
0425     rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
0426     if (lss_l1_2) {
0427         pcr_dbg(pcr, "Set parameters for L1.2.");
0428         rtsx_pci_write_register(pcr, PWR_GLOBAL_CTRL,
0429                     0xFF, PCIE_L1_2_EN);
0430         rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
0431                     RTS5260_DVCC_OCP_EN |
0432                     RTS5260_DVCC_OCP_CL_EN,
0433                     RTS5260_DVCC_OCP_EN |
0434                     RTS5260_DVCC_OCP_CL_EN);
0435
0436         rtsx_pci_write_register(pcr, PWR_FE_CTL,
0437                     0xFF, PCIE_L1_2_PD_FE_EN);
0438     } else if (lss_l1_1) {
0439         pcr_dbg(pcr, "Set parameters for L1.1.");
0440         rtsx_pci_write_register(pcr, PWR_GLOBAL_CTRL,
0441                     0xFF, PCIE_L1_1_EN);
0442         rtsx_pci_write_register(pcr, PWR_FE_CTL,
0443                     0xFF, PCIE_L1_1_PD_FE_EN);
0444     } else {
0445         pcr_dbg(pcr, "Set parameters for L1.");
0446         rtsx_pci_write_register(pcr, PWR_GLOBAL_CTRL,
0447                     0xFF, PCIE_L1_0_EN);
0448         rtsx_pci_write_register(pcr, PWR_FE_CTL,
0449                     0xFF, PCIE_L1_0_PD_FE_EN);
0450     }
0451
0452     rtsx_pci_write_register(pcr, CFG_L1_0_PCIE_DPHY_RET_VALUE,
0453                 0xFF, CFG_L1_0_RET_VALUE_DEFAULT);
0454     rtsx_pci_write_register(pcr, CFG_L1_0_PCIE_MAC_RET_VALUE,
0455                 0xFF, CFG_L1_0_RET_VALUE_DEFAULT);
0456     rtsx_pci_write_register(pcr, CFG_L1_0_CRC_SD30_RET_VALUE,
0457                 0xFF, CFG_L1_0_RET_VALUE_DEFAULT);
0458     rtsx_pci_write_register(pcr, CFG_L1_0_CRC_SD40_RET_VALUE,
0459                 0xFF, CFG_L1_0_RET_VALUE_DEFAULT);
0460     rtsx_pci_write_register(pcr, CFG_L1_0_SYS_RET_VALUE,
0461                 0xFF, CFG_L1_0_RET_VALUE_DEFAULT);
0462     /*Option cut APHY*/
0463     rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_0,
0464                 0xFF, CFG_PCIE_APHY_OFF_0_DEFAULT);
0465     rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_1,
0466                 0xFF, CFG_PCIE_APHY_OFF_1_DEFAULT);
0467     rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_2,
0468                 0xFF, CFG_PCIE_APHY_OFF_2_DEFAULT);
0469     rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_3,
0470                 0xFF, CFG_PCIE_APHY_OFF_3_DEFAULT);
0471     /*CDR DEC*/
0472     rtsx_pci_write_register(pcr, PWC_CDR, 0xFF, PWC_CDR_DEFAULT);
0473     /*PWMPFM*/
0474     rtsx_pci_write_register(pcr, CFG_LP_FPWM_VALUE,
0475                 0xFF, CFG_LP_FPWM_VALUE_DEFAULT);
0476     /*No Power Saving WA*/
0477     rtsx_pci_write_register(pcr, CFG_L1_0_CRC_MISC_RET_VALUE,
0478                 0xFF, CFG_L1_0_CRC_MISC_RET_VALUE_DEFAULT);
0479 }
0480
0481 static void rts5260_init_from_cfg(struct rtsx_pcr *pcr)
0482 {
0483     struct pci_dev *pdev = pcr->pci;
0484     int l1ss;
0485     struct rtsx_cr_option *option = &pcr->option;
0486     u32 lval;
0487
0488     l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
0489     if (!l1ss)
0490         return;
0491
0492     pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
0493
0494     if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
0495         rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
0496
0497     if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
0498         rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
0499
0500     if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
0501         rtsx_set_dev_flag(pcr, PM_L1_1_EN);
0502
0503     if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
0504         rtsx_set_dev_flag(pcr, PM_L1_2_EN);
0505
0506     rts5260_pwr_saving_setting(pcr);
0507
0508     if (option->ltr_en) {
0509         u16 val;
0510
0511         pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val);
0512         if (val & PCI_EXP_DEVCTL2_LTR_EN) {
0513             option->ltr_enabled = true;
0514             option->ltr_active = true;
0515             rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
0516         } else {
0517             option->ltr_enabled = false;
0518         }
0519     }
0520
0521     if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
0522                 | PM_L1_1_EN | PM_L1_2_EN))
0523         option->force_clkreq_0 = false;
0524     else
0525         option->force_clkreq_0 = true;
0526 }
0527
0528 static int rts5260_extra_init_hw(struct rtsx_pcr *pcr)
0529 {
0530     struct rtsx_cr_option *option = &pcr->option;
0531
0532     /* Set mcu_cnt to 7 to ensure data can be sampled properly */
0533     rtsx_pci_write_register(pcr, 0xFC03, 0x7F, 0x07);
0534     rtsx_pci_write_register(pcr, SSC_DIV_N_0, 0xFF, 0x5D);
0535
0536     rts5260_init_from_cfg(pcr);
0537
0538     /* force no MDIO*/
0539     rtsx_pci_write_register(pcr, RTS5260_AUTOLOAD_CFG4,
0540                 0xFF, RTS5260_MIMO_DISABLE);
0541     /*Modify SDVCC Tune Default Parameters!*/
0542     rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
0543                 RTS5260_DVCC_TUNE_MASK, RTS5260_DVCC_33);
0544
0545     rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
0546
0547     rts5260_init_hw(pcr);
0548
0549     /*
0550      * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
0551      * to drive low, and we forcibly request clock.
0552      */
0553     if (option->force_clkreq_0)
0554         rtsx_pci_write_register(pcr, PETXCFG,
0555                  FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
0556     else
0557         rtsx_pci_write_register(pcr, PETXCFG,
0558                  FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
0559
0560     rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
0561
0562     return 0;
0563 }
0564
0565 static void rts5260_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
0566 {
0567     struct rtsx_cr_option *option = &pcr->option;
0568     u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);
0569     int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST);
0570     int aspm_L1_1, aspm_L1_2;
0571     u8 val = 0;
0572
0573     aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
0574     aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
0575
0576     if (active) {
0577         /* run, latency: 60us */
0578         if (aspm_L1_1)
0579             val = option->ltr_l1off_snooze_sspwrgate;
0580     } else {
0581         /* l1off, latency: 300us */
0582         if (aspm_L1_2)
0583             val = option->ltr_l1off_sspwrgate;
0584     }
0585
0586     if (aspm_L1_1 || aspm_L1_2) {
0587         if (rtsx_check_dev_flag(pcr,
0588                     LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) {
0589             if (card_exist)
0590                 val &= ~L1OFF_MBIAS2_EN_5250;
0591             else
0592                 val |= L1OFF_MBIAS2_EN_5250;
0593         }
0594     }
0595     rtsx_set_l1off_sub(pcr, val);
0596 }
0597
0598 static const struct pcr_ops rts5260_pcr_ops = {
0599     .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
0600     .turn_on_led = rts5260_turn_on_led,
0601     .turn_off_led = rts5260_turn_off_led,
0602     .extra_init_hw = rts5260_extra_init_hw,
0603     .enable_auto_blink = rtsx_base_enable_auto_blink,
0604     .disable_auto_blink = rtsx_base_disable_auto_blink,
0605     .card_power_on = rts5260_card_power_on,
0606     .card_power_off = rts5260_card_power_off,
0607     .switch_output_voltage = rts5260_switch_output_voltage,
0608     .stop_cmd = rts5260_stop_cmd,
0609     .set_l1off_cfg_sub_d0 = rts5260_set_l1off_cfg_sub_d0,
0610     .enable_ocp = rts5260_enable_ocp,
0611     .disable_ocp = rts5260_disable_ocp,
0612     .init_ocp = rts5260_init_ocp,
0613     .process_ocp = rts5260_process_ocp,
0614     .get_ocpstat = rts5260_get_ocpstat,
0615     .clear_ocpstat = rts5260_clear_ocpstat,
0616 };
0617
0618 void rts5260_init_params(struct rtsx_pcr *pcr)
0619 {
0620     struct rtsx_cr_option *option = &pcr->option;
0621     struct rtsx_hw_param *hw_param = &pcr->hw_param;
0622
0623     pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
0624     pcr->num_slots = 2;
0625
0626     pcr->flags = 0;
0627     pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
0628     pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
0629     pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
0630     pcr->aspm_en = ASPM_L1_EN;
0631     pcr->aspm_mode = ASPM_MODE_REG;
0632     pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);
0633     pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
0634
0635     pcr->ic_version = rts5260_get_ic_version(pcr);
0636     pcr->sd_pull_ctl_enable_tbl = rts5260_sd_pull_ctl_enable_tbl;
0637     pcr->sd_pull_ctl_disable_tbl = rts5260_sd_pull_ctl_disable_tbl;
0638     pcr->ms_pull_ctl_enable_tbl = rts5260_ms_pull_ctl_enable_tbl;
0639     pcr->ms_pull_ctl_disable_tbl = rts5260_ms_pull_ctl_disable_tbl;
0640
0641     pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
0642
0643     pcr->ops = &rts5260_pcr_ops;
0644
0645     option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
0646                 | LTR_L1SS_PWR_GATE_EN);
0647     option->ltr_en = true;
0648
0649     /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
0650     option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
0651     option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
0652     option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
0653     option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
0654     option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
0655     option->ltr_l1off_snooze_sspwrgate =
0656         LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
0657
0658     option->ocp_en = 1;
0659     if (option->ocp_en)
0660         hw_param->interrupt_en |= SD_OC_INT_EN;
0661     hw_param->ocp_glitch =  SD_OCP_GLITCH_100U | SDVIO_OCP_GLITCH_800U;
0662     option->sd_400mA_ocp_thd = RTS5260_DVCC_OCP_THD_550;
0663     option->sd_800mA_ocp_thd = RTS5260_DVCC_OCP_THD_970;
0664 }