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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /* Driver for Realtek PCI-Express card reader
0003  *
0004  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
0005  *
0006  * Author:
0007  *   Wei WANG <wei_wang@realsil.com.cn>
0008  */
0009 
0010 #include <linux/module.h>
0011 #include <linux/delay.h>
0012 #include <linux/rtsx_pci.h>
0013 
0014 #include "rtsx_pcr.h"
0015 
0016 static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
0017 {
0018     u8 val;
0019 
0020     rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
0021     return val & 0x0F;
0022 }
0023 
0024 static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
0025 {
0026     u8 driving_3v3[4][3] = {
0027         {0x11, 0x11, 0x18},
0028         {0x55, 0x55, 0x5C},
0029         {0xFF, 0xFF, 0xFF},
0030         {0x96, 0x96, 0x96},
0031     };
0032     u8 driving_1v8[4][3] = {
0033         {0xC4, 0xC4, 0xC4},
0034         {0x3C, 0x3C, 0x3C},
0035         {0xFE, 0xFE, 0xFE},
0036         {0xB3, 0xB3, 0xB3},
0037     };
0038     u8 (*driving)[3], drive_sel;
0039 
0040     if (voltage == OUTPUT_3V3) {
0041         driving = driving_3v3;
0042         drive_sel = pcr->sd30_drive_sel_3v3;
0043     } else {
0044         driving = driving_1v8;
0045         drive_sel = pcr->sd30_drive_sel_1v8;
0046     }
0047 
0048     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
0049             0xFF, driving[drive_sel][0]);
0050     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
0051             0xFF, driving[drive_sel][1]);
0052     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
0053             0xFF, driving[drive_sel][2]);
0054 }
0055 
0056 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
0057 {
0058     struct pci_dev *pdev = pcr->pci;
0059     u32 reg;
0060 
0061     pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
0062     pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
0063 
0064     if (!rtsx_vendor_setting_valid(reg)) {
0065         pcr_dbg(pcr, "skip fetch vendor setting\n");
0066         return;
0067     }
0068 
0069     pcr->aspm_en = rtsx_reg_to_aspm(reg);
0070     pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
0071     pcr->card_drive_sel &= 0x3F;
0072     pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
0073 
0074     pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
0075     pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
0076 
0077     if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A))
0078         pcr->rtd3_en = rtsx_reg_to_rtd3_uhsii(reg);
0079 
0080     if (rtsx_check_mmc_support(reg))
0081         pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
0082     pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
0083     if (rtsx_reg_check_reverse_socket(reg))
0084         pcr->flags |= PCR_REVERSE_SOCKET;
0085 }
0086 
0087 static void rts5249_init_from_cfg(struct rtsx_pcr *pcr)
0088 {
0089     struct pci_dev *pdev = pcr->pci;
0090     int l1ss;
0091     struct rtsx_cr_option *option = &(pcr->option);
0092     u32 lval;
0093 
0094     l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
0095     if (!l1ss)
0096         return;
0097 
0098     pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
0099 
0100     if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
0101         if (0 == (lval & 0x0F))
0102             rtsx_pci_enable_oobs_polling(pcr);
0103         else
0104             rtsx_pci_disable_oobs_polling(pcr);
0105     }
0106 
0107 
0108     if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
0109         rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
0110 
0111     if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
0112         rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
0113 
0114     if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
0115         rtsx_set_dev_flag(pcr, PM_L1_1_EN);
0116 
0117     if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
0118         rtsx_set_dev_flag(pcr, PM_L1_2_EN);
0119 
0120     if (option->ltr_en) {
0121         u16 val;
0122 
0123         pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val);
0124         if (val & PCI_EXP_DEVCTL2_LTR_EN) {
0125             option->ltr_enabled = true;
0126             option->ltr_active = true;
0127             rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
0128         } else {
0129             option->ltr_enabled = false;
0130         }
0131     }
0132 }
0133 
0134 static int rts5249_init_from_hw(struct rtsx_pcr *pcr)
0135 {
0136     struct rtsx_cr_option *option = &(pcr->option);
0137 
0138     if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
0139                 | PM_L1_1_EN | PM_L1_2_EN))
0140         option->force_clkreq_0 = false;
0141     else
0142         option->force_clkreq_0 = true;
0143 
0144     return 0;
0145 }
0146 
0147 static void rts52xa_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
0148 {
0149     /* Set relink_time to 0 */
0150     rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
0151     rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
0152     rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
0153                 RELINK_TIME_MASK, 0);
0154 
0155     rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
0156             D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
0157 
0158     if (!runtime) {
0159         rtsx_pci_write_register(pcr, RTS524A_AUTOLOAD_CFG1,
0160                 CD_RESUME_EN_MASK, 0);
0161         rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x00);
0162         rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x20);
0163     }
0164 
0165     rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN);
0166 }
0167 
0168 static void rts52xa_save_content_from_efuse(struct rtsx_pcr *pcr)
0169 {
0170     u8 cnt, sv;
0171     u16 j = 0;
0172     u8 tmp;
0173     u8 val;
0174     int i;
0175 
0176     rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
0177                 REG_EFUSE_BYPASS | REG_EFUSE_POR, REG_EFUSE_POR);
0178     udelay(1);
0179 
0180     pcr_dbg(pcr, "Enable efuse por!");
0181     pcr_dbg(pcr, "save efuse to autoload");
0182 
0183     rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, REG_EFUSE_ADD_MASK, 0x00);
0184     rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
0185                 REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
0186     /* Wait transfer end */
0187     for (j = 0; j < 1024; j++) {
0188         rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
0189         if ((tmp & 0x80) == 0)
0190             break;
0191     }
0192     rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
0193     cnt = val & 0x0F;
0194     sv = val & 0x10;
0195 
0196     if (sv) {
0197         for (i = 0; i < 4; i++) {
0198             rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
0199                 REG_EFUSE_ADD_MASK, 0x04 + i);
0200             rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
0201                 REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
0202             /* Wait transfer end */
0203             for (j = 0; j < 1024; j++) {
0204                 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
0205                 if ((tmp & 0x80) == 0)
0206                     break;
0207             }
0208             rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
0209             rtsx_pci_write_register(pcr, 0xFF04 + i, 0xFF, val);
0210         }
0211     } else {
0212         rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr));
0213         rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8));
0214         rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr));
0215         rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8));
0216     }
0217 
0218     for (i = 0; i < cnt * 4; i++) {
0219         if (sv)
0220             rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
0221                 REG_EFUSE_ADD_MASK, 0x08 + i);
0222         else
0223             rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD,
0224                 REG_EFUSE_ADD_MASK, 0x04 + i);
0225         rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL,
0226                 REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE);
0227         /* Wait transfer end */
0228         for (j = 0; j < 1024; j++) {
0229             rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp);
0230             if ((tmp & 0x80) == 0)
0231                 break;
0232         }
0233         rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val);
0234         rtsx_pci_write_register(pcr, 0xFF08 + i, 0xFF, val);
0235     }
0236     rtsx_pci_write_register(pcr, 0xFF00, 0xFF, (cnt & 0x7F) | 0x80);
0237     rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
0238         REG_EFUSE_BYPASS | REG_EFUSE_POR, REG_EFUSE_BYPASS);
0239     pcr_dbg(pcr, "Disable efuse por!");
0240 }
0241 
0242 static void rts52xa_save_content_to_autoload_space(struct rtsx_pcr *pcr)
0243 {
0244     u8 val;
0245 
0246     rtsx_pci_read_register(pcr, RESET_LOAD_REG, &val);
0247     if (val & 0x02) {
0248         rtsx_pci_read_register(pcr, RTS525A_BIOS_CFG, &val);
0249         if (val & RTS525A_LOAD_BIOS_FLAG) {
0250             rtsx_pci_write_register(pcr, RTS525A_BIOS_CFG,
0251                 RTS525A_LOAD_BIOS_FLAG, RTS525A_CLEAR_BIOS_FLAG);
0252 
0253             rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
0254                 REG_EFUSE_POWER_MASK, REG_EFUSE_POWERON);
0255 
0256             pcr_dbg(pcr, "Power ON efuse!");
0257             mdelay(1);
0258             rts52xa_save_content_from_efuse(pcr);
0259         } else {
0260             rtsx_pci_read_register(pcr, RTS524A_PME_FORCE_CTL, &val);
0261             if (!(val & 0x08))
0262                 rts52xa_save_content_from_efuse(pcr);
0263         }
0264     } else {
0265         pcr_dbg(pcr, "Load from autoload");
0266         rtsx_pci_write_register(pcr, 0xFF00, 0xFF, 0x80);
0267         rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr));
0268         rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8));
0269         rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr));
0270         rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8));
0271     }
0272 }
0273 
0274 static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
0275 {
0276     struct rtsx_cr_option *option = &(pcr->option);
0277 
0278     rts5249_init_from_cfg(pcr);
0279     rts5249_init_from_hw(pcr);
0280 
0281     rtsx_pci_init_cmd(pcr);
0282 
0283     if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A))
0284         rts52xa_save_content_to_autoload_space(pcr);
0285 
0286     /* Rest L1SUB Config */
0287     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
0288     /* Configure GPIO as output */
0289     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
0290     /* Reset ASPM state to default value */
0291     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
0292     /* Switch LDO3318 source from DV33 to card_3v3 */
0293     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
0294     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
0295     /* LED shine disabled, set initial shine cycle period */
0296     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
0297     /* Configure driving */
0298     rts5249_fill_driving(pcr, OUTPUT_3V3);
0299     if (pcr->flags & PCR_REVERSE_SOCKET)
0300         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
0301     else
0302         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
0303 
0304     rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
0305 
0306     if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
0307         rtsx_pci_write_register(pcr, REG_VREF, PWD_SUSPND_EN, PWD_SUSPND_EN);
0308         rtsx_pci_write_register(pcr, RTS524A_AUTOLOAD_CFG1,
0309             CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
0310     }
0311 
0312     if (pcr->rtd3_en) {
0313         if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
0314             rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x01);
0315             rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x30);
0316         } else {
0317             rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x01);
0318             rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x33);
0319         }
0320     } else {
0321         if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
0322             rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x00);
0323             rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x20);
0324         } else {
0325             rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x30);
0326             rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x00);
0327         }
0328     }
0329 
0330 
0331     /*
0332      * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
0333      * to drive low, and we forcibly request clock.
0334      */
0335     if (option->force_clkreq_0)
0336         rtsx_pci_write_register(pcr, PETXCFG,
0337             FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
0338     else
0339         rtsx_pci_write_register(pcr, PETXCFG,
0340             FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
0341 
0342     rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
0343     if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) {
0344         rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL,
0345                 REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF);
0346         pcr_dbg(pcr, "Power OFF efuse!");
0347     }
0348 
0349     return 0;
0350 }
0351 
0352 static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
0353 {
0354     int err;
0355 
0356     err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
0357     if (err < 0)
0358         return err;
0359 
0360     err = rtsx_pci_write_phy_register(pcr, PHY_REV,
0361             PHY_REV_RESV | PHY_REV_RXIDLE_LATCHED |
0362             PHY_REV_P1_EN | PHY_REV_RXIDLE_EN |
0363             PHY_REV_CLKREQ_TX_EN | PHY_REV_RX_PWST |
0364             PHY_REV_CLKREQ_DT_1_0 | PHY_REV_STOP_CLKRD |
0365             PHY_REV_STOP_CLKWR);
0366     if (err < 0)
0367         return err;
0368 
0369     msleep(1);
0370 
0371     err = rtsx_pci_write_phy_register(pcr, PHY_BPCR,
0372             PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL |
0373             PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN);
0374     if (err < 0)
0375         return err;
0376 
0377     err = rtsx_pci_write_phy_register(pcr, PHY_PCR,
0378             PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
0379             PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 |
0380             PHY_PCR_RSSI_EN | PHY_PCR_RX10K);
0381     if (err < 0)
0382         return err;
0383 
0384     err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
0385             PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR |
0386             PHY_RCR2_CDR_SR_2 | PHY_RCR2_FREQSEL_12 |
0387             PHY_RCR2_CDR_SC_12P | PHY_RCR2_CALIB_LATE);
0388     if (err < 0)
0389         return err;
0390 
0391     err = rtsx_pci_write_phy_register(pcr, PHY_FLD4,
0392             PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF |
0393             PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA |
0394             PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER |
0395             PHY_FLD4_BER_CHK_EN);
0396     if (err < 0)
0397         return err;
0398     err = rtsx_pci_write_phy_register(pcr, PHY_RDR,
0399             PHY_RDR_RXDSEL_1_9 | PHY_SSC_AUTO_PWD);
0400     if (err < 0)
0401         return err;
0402     err = rtsx_pci_write_phy_register(pcr, PHY_RCR1,
0403             PHY_RCR1_ADP_TIME_4 | PHY_RCR1_VCO_COARSE);
0404     if (err < 0)
0405         return err;
0406     err = rtsx_pci_write_phy_register(pcr, PHY_FLD3,
0407             PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 |
0408             PHY_FLD3_RXDELINK);
0409     if (err < 0)
0410         return err;
0411 
0412     return rtsx_pci_write_phy_register(pcr, PHY_TUNE,
0413             PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 |
0414             PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 |
0415             PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12);
0416 }
0417 
0418 static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr)
0419 {
0420     return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
0421 }
0422 
0423 static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr)
0424 {
0425     return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
0426 }
0427 
0428 static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
0429 {
0430     return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
0431 }
0432 
0433 static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
0434 {
0435     return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
0436 }
0437 
0438 static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card)
0439 {
0440     int err;
0441     struct rtsx_cr_option *option = &pcr->option;
0442 
0443     if (option->ocp_en)
0444         rtsx_pci_enable_ocp(pcr);
0445 
0446     rtsx_pci_init_cmd(pcr);
0447     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
0448             SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
0449     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
0450             LDO3318_PWR_MASK, 0x02);
0451     err = rtsx_pci_send_cmd(pcr, 100);
0452     if (err < 0)
0453         return err;
0454 
0455     msleep(5);
0456 
0457     rtsx_pci_init_cmd(pcr);
0458     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
0459             SD_POWER_MASK, SD_VCC_POWER_ON);
0460     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
0461             LDO3318_PWR_MASK, 0x06);
0462     return rtsx_pci_send_cmd(pcr, 100);
0463 }
0464 
0465 static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card)
0466 {
0467     struct rtsx_cr_option *option = &pcr->option;
0468 
0469     if (option->ocp_en)
0470         rtsx_pci_disable_ocp(pcr);
0471 
0472     rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK, SD_POWER_OFF);
0473 
0474     rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0x00);
0475     return 0;
0476 }
0477 
0478 static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
0479 {
0480     int err;
0481     u16 append;
0482 
0483     switch (voltage) {
0484     case OUTPUT_3V3:
0485         err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
0486             PHY_TUNE_VOLTAGE_3V3);
0487         if (err < 0)
0488             return err;
0489         break;
0490     case OUTPUT_1V8:
0491         append = PHY_TUNE_D18_1V8;
0492         if (CHK_PCI_PID(pcr, 0x5249)) {
0493             err = rtsx_pci_update_phy(pcr, PHY_BACR,
0494                 PHY_BACR_BASIC_MASK, 0);
0495             if (err < 0)
0496                 return err;
0497             append = PHY_TUNE_D18_1V7;
0498         }
0499 
0500         err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
0501             append);
0502         if (err < 0)
0503             return err;
0504         break;
0505     default:
0506         pcr_dbg(pcr, "unknown output voltage %d\n", voltage);
0507         return -EINVAL;
0508     }
0509 
0510     /* set pad drive */
0511     rtsx_pci_init_cmd(pcr);
0512     rts5249_fill_driving(pcr, voltage);
0513     return rtsx_pci_send_cmd(pcr, 100);
0514 }
0515 
0516 static const struct pcr_ops rts5249_pcr_ops = {
0517     .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
0518     .extra_init_hw = rts5249_extra_init_hw,
0519     .optimize_phy = rts5249_optimize_phy,
0520     .turn_on_led = rtsx_base_turn_on_led,
0521     .turn_off_led = rtsx_base_turn_off_led,
0522     .enable_auto_blink = rtsx_base_enable_auto_blink,
0523     .disable_auto_blink = rtsx_base_disable_auto_blink,
0524     .card_power_on = rtsx_base_card_power_on,
0525     .card_power_off = rtsx_base_card_power_off,
0526     .switch_output_voltage = rtsx_base_switch_output_voltage,
0527 };
0528 
0529 /* SD Pull Control Enable:
0530  *     SD_DAT[3:0] ==> pull up
0531  *     SD_CD       ==> pull up
0532  *     SD_WP       ==> pull up
0533  *     SD_CMD      ==> pull up
0534  *     SD_CLK      ==> pull down
0535  */
0536 static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
0537     RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
0538     RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
0539     RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
0540     RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
0541     0,
0542 };
0543 
0544 /* SD Pull Control Disable:
0545  *     SD_DAT[3:0] ==> pull down
0546  *     SD_CD       ==> pull up
0547  *     SD_WP       ==> pull down
0548  *     SD_CMD      ==> pull down
0549  *     SD_CLK      ==> pull down
0550  */
0551 static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
0552     RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
0553     RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
0554     RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
0555     RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
0556     0,
0557 };
0558 
0559 /* MS Pull Control Enable:
0560  *     MS CD       ==> pull up
0561  *     others      ==> pull down
0562  */
0563 static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
0564     RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
0565     RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
0566     RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
0567     0,
0568 };
0569 
0570 /* MS Pull Control Disable:
0571  *     MS CD       ==> pull up
0572  *     others      ==> pull down
0573  */
0574 static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
0575     RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
0576     RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
0577     RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
0578     0,
0579 };
0580 
0581 void rts5249_init_params(struct rtsx_pcr *pcr)
0582 {
0583     struct rtsx_cr_option *option = &(pcr->option);
0584 
0585     pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
0586     pcr->num_slots = 2;
0587     pcr->ops = &rts5249_pcr_ops;
0588 
0589     pcr->flags = 0;
0590     pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
0591     pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
0592     pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
0593     pcr->aspm_en = ASPM_L1_EN;
0594     pcr->aspm_mode = ASPM_MODE_CFG;
0595     pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
0596     pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
0597 
0598     pcr->ic_version = rts5249_get_ic_version(pcr);
0599     pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
0600     pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
0601     pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
0602     pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
0603 
0604     pcr->reg_pm_ctrl3 = PM_CTRL3;
0605 
0606     option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
0607                 | LTR_L1SS_PWR_GATE_EN);
0608     option->ltr_en = true;
0609 
0610     /* Init latency of active, idle, L1OFF to 60us, 300us, 3ms */
0611     option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
0612     option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
0613     option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
0614     option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
0615     option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5249_DEF;
0616     option->ltr_l1off_snooze_sspwrgate =
0617         LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF;
0618 }
0619 
0620 static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val)
0621 {
0622     addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
0623 
0624     return __rtsx_pci_write_phy_register(pcr, addr, val);
0625 }
0626 
0627 static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val)
0628 {
0629     addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
0630 
0631     return __rtsx_pci_read_phy_register(pcr, addr, val);
0632 }
0633 
0634 static int rts524a_optimize_phy(struct rtsx_pcr *pcr)
0635 {
0636     int err;
0637 
0638     err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
0639         D3_DELINK_MODE_EN, 0x00);
0640     if (err < 0)
0641         return err;
0642 
0643     rtsx_pci_write_phy_register(pcr, PHY_PCR,
0644         PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
0645         PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN);
0646     rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
0647         PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
0648 
0649     if (is_version(pcr, 0x524A, IC_VER_A)) {
0650         rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
0651             PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
0652         rtsx_pci_write_phy_register(pcr, PHY_SSCCR2,
0653             PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 |
0654             PHY_SSCCR2_TIME2_WIDTH);
0655         rtsx_pci_write_phy_register(pcr, PHY_ANA1A,
0656             PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST |
0657             PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV);
0658         rtsx_pci_write_phy_register(pcr, PHY_ANA1D,
0659             PHY_ANA1D_DEBUG_ADDR);
0660         rtsx_pci_write_phy_register(pcr, PHY_DIG1E,
0661             PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 |
0662             PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST |
0663             PHY_DIG1E_RCLK_TX_EN_KEEP |
0664             PHY_DIG1E_RCLK_TX_TERM_KEEP |
0665             PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP |
0666             PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP |
0667             PHY_DIG1E_RX_EN_KEEP);
0668     }
0669 
0670     rtsx_pci_write_phy_register(pcr, PHY_ANA08,
0671         PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN |
0672         PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI);
0673 
0674     return 0;
0675 }
0676 
0677 static int rts524a_extra_init_hw(struct rtsx_pcr *pcr)
0678 {
0679     rts5249_extra_init_hw(pcr);
0680 
0681     rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
0682         FORCE_ASPM_L1_EN, FORCE_ASPM_L1_EN);
0683     rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
0684     rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN,
0685         LDO_VCC_LMT_EN);
0686     rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
0687     if (is_version(pcr, 0x524A, IC_VER_A)) {
0688         rtsx_pci_write_register(pcr, LDO_DV18_CFG,
0689             LDO_DV18_SR_MASK, LDO_DV18_SR_DF);
0690         rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
0691             LDO_VCC_REF_TUNE_MASK, LDO_VCC_REF_1V2);
0692         rtsx_pci_write_register(pcr, LDO_VIO_CFG,
0693             LDO_VIO_REF_TUNE_MASK, LDO_VIO_REF_1V2);
0694         rtsx_pci_write_register(pcr, LDO_VIO_CFG,
0695             LDO_VIO_SR_MASK, LDO_VIO_SR_DF);
0696         rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
0697             LDO_REF12_TUNE_MASK, LDO_REF12_TUNE_DF);
0698         rtsx_pci_write_register(pcr, SD40_LDO_CTL1,
0699             SD40_VIO_TUNE_MASK, SD40_VIO_TUNE_1V7);
0700     }
0701 
0702     return 0;
0703 }
0704 
0705 static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
0706 {
0707     struct rtsx_cr_option *option = &(pcr->option);
0708 
0709     u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);
0710     int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST);
0711     int aspm_L1_1, aspm_L1_2;
0712     u8 val = 0;
0713 
0714     aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
0715     aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
0716 
0717     if (active) {
0718         /* Run, latency: 60us */
0719         if (aspm_L1_1)
0720             val = option->ltr_l1off_snooze_sspwrgate;
0721     } else {
0722         /* L1off, latency: 300us */
0723         if (aspm_L1_2)
0724             val = option->ltr_l1off_sspwrgate;
0725     }
0726 
0727     if (aspm_L1_1 || aspm_L1_2) {
0728         if (rtsx_check_dev_flag(pcr,
0729                     LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) {
0730             if (card_exist)
0731                 val &= ~L1OFF_MBIAS2_EN_5250;
0732             else
0733                 val |= L1OFF_MBIAS2_EN_5250;
0734         }
0735     }
0736     rtsx_set_l1off_sub(pcr, val);
0737 }
0738 
0739 static const struct pcr_ops rts524a_pcr_ops = {
0740     .write_phy = rts524a_write_phy,
0741     .read_phy = rts524a_read_phy,
0742     .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
0743     .extra_init_hw = rts524a_extra_init_hw,
0744     .optimize_phy = rts524a_optimize_phy,
0745     .turn_on_led = rtsx_base_turn_on_led,
0746     .turn_off_led = rtsx_base_turn_off_led,
0747     .enable_auto_blink = rtsx_base_enable_auto_blink,
0748     .disable_auto_blink = rtsx_base_disable_auto_blink,
0749     .card_power_on = rtsx_base_card_power_on,
0750     .card_power_off = rtsx_base_card_power_off,
0751     .switch_output_voltage = rtsx_base_switch_output_voltage,
0752     .force_power_down = rts52xa_force_power_down,
0753     .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
0754 };
0755 
0756 void rts524a_init_params(struct rtsx_pcr *pcr)
0757 {
0758     rts5249_init_params(pcr);
0759     pcr->aspm_mode = ASPM_MODE_REG;
0760     pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);
0761     pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
0762     pcr->option.ltr_l1off_snooze_sspwrgate =
0763         LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
0764 
0765     pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
0766     pcr->ops = &rts524a_pcr_ops;
0767 
0768     pcr->option.ocp_en = 1;
0769     if (pcr->option.ocp_en)
0770         pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
0771     pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
0772     pcr->option.sd_800mA_ocp_thd = RTS524A_OCP_THD_800;
0773 
0774 }
0775 
0776 static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card)
0777 {
0778     rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
0779         LDO_VCC_TUNE_MASK, LDO_VCC_3V3);
0780     return rtsx_base_card_power_on(pcr, card);
0781 }
0782 
0783 static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
0784 {
0785     switch (voltage) {
0786     case OUTPUT_3V3:
0787         rtsx_pci_write_register(pcr, LDO_CONFIG2,
0788             LDO_D3318_MASK, LDO_D3318_33V);
0789         rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);
0790         break;
0791     case OUTPUT_1V8:
0792         rtsx_pci_write_register(pcr, LDO_CONFIG2,
0793             LDO_D3318_MASK, LDO_D3318_18V);
0794         rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,
0795             SD_IO_USING_1V8);
0796         break;
0797     default:
0798         return -EINVAL;
0799     }
0800 
0801     rtsx_pci_init_cmd(pcr);
0802     rts5249_fill_driving(pcr, voltage);
0803     return rtsx_pci_send_cmd(pcr, 100);
0804 }
0805 
0806 static int rts525a_optimize_phy(struct rtsx_pcr *pcr)
0807 {
0808     int err;
0809 
0810     err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
0811         D3_DELINK_MODE_EN, 0x00);
0812     if (err < 0)
0813         return err;
0814 
0815     rtsx_pci_write_phy_register(pcr, _PHY_FLD0,
0816         _PHY_FLD0_CLK_REQ_20C | _PHY_FLD0_RX_IDLE_EN |
0817         _PHY_FLD0_BIT_ERR_RSTN | _PHY_FLD0_BER_COUNT |
0818         _PHY_FLD0_BER_TIMER | _PHY_FLD0_CHECK_EN);
0819 
0820     rtsx_pci_write_phy_register(pcr, _PHY_ANA03,
0821         _PHY_ANA03_TIMER_MAX | _PHY_ANA03_OOBS_DEB_EN |
0822         _PHY_CMU_DEBUG_EN);
0823 
0824     if (is_version(pcr, 0x525A, IC_VER_A))
0825         rtsx_pci_write_phy_register(pcr, _PHY_REV0,
0826             _PHY_REV0_FILTER_OUT | _PHY_REV0_CDR_BYPASS_PFD |
0827             _PHY_REV0_CDR_RX_IDLE_BYPASS);
0828 
0829     return 0;
0830 }
0831 
0832 static int rts525a_extra_init_hw(struct rtsx_pcr *pcr)
0833 {
0834     rts5249_extra_init_hw(pcr);
0835 
0836     rtsx_pci_write_register(pcr, RTS5250_CLK_CFG3, RTS525A_CFG_MEM_PD, RTS525A_CFG_MEM_PD);
0837 
0838     rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
0839     if (is_version(pcr, 0x525A, IC_VER_A)) {
0840         rtsx_pci_write_register(pcr, L1SUB_CONFIG2,
0841             L1SUB_AUTO_CFG, L1SUB_AUTO_CFG);
0842         rtsx_pci_write_register(pcr, RREF_CFG,
0843             RREF_VBGSEL_MASK, RREF_VBGSEL_1V25);
0844         rtsx_pci_write_register(pcr, LDO_VIO_CFG,
0845             LDO_VIO_TUNE_MASK, LDO_VIO_1V7);
0846         rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
0847             LDO_D12_TUNE_MASK, LDO_D12_TUNE_DF);
0848         rtsx_pci_write_register(pcr, LDO_AV12S_CFG,
0849             LDO_AV12S_TUNE_MASK, LDO_AV12S_TUNE_DF);
0850         rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
0851             LDO_VCC_LMTVTH_MASK, LDO_VCC_LMTVTH_2A);
0852         rtsx_pci_write_register(pcr, OOBS_CONFIG,
0853             OOBS_AUTOK_DIS | OOBS_VAL_MASK, 0x89);
0854     }
0855 
0856     return 0;
0857 }
0858 
0859 static const struct pcr_ops rts525a_pcr_ops = {
0860     .fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
0861     .extra_init_hw = rts525a_extra_init_hw,
0862     .optimize_phy = rts525a_optimize_phy,
0863     .turn_on_led = rtsx_base_turn_on_led,
0864     .turn_off_led = rtsx_base_turn_off_led,
0865     .enable_auto_blink = rtsx_base_enable_auto_blink,
0866     .disable_auto_blink = rtsx_base_disable_auto_blink,
0867     .card_power_on = rts525a_card_power_on,
0868     .card_power_off = rtsx_base_card_power_off,
0869     .switch_output_voltage = rts525a_switch_output_voltage,
0870     .force_power_down = rts52xa_force_power_down,
0871     .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
0872 };
0873 
0874 void rts525a_init_params(struct rtsx_pcr *pcr)
0875 {
0876     rts5249_init_params(pcr);
0877     pcr->aspm_mode = ASPM_MODE_REG;
0878     pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11);
0879     pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
0880     pcr->option.ltr_l1off_snooze_sspwrgate =
0881         LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
0882 
0883     pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
0884     pcr->ops = &rts525a_pcr_ops;
0885 
0886     pcr->option.ocp_en = 1;
0887     if (pcr->option.ocp_en)
0888         pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
0889     pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
0890     pcr->option.sd_800mA_ocp_thd = RTS525A_OCP_THD_800;
0891 }
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