misc/cardreader/rts5228.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Driver for Realtek PCI-Express card reader
0003  *
0004  * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
0005  *
0006  * Author:
0007  *   Ricky WU <ricky_wu@realtek.com>
0008  *   Rui FENG <rui_feng@realsil.com.cn>
0009  *   Wei WANG <wei_wang@realsil.com.cn>
0010  */
0011 #ifndef RTS5228_H
0012 #define RTS5228_H
0013
0014
0015 #define RTS5228_AUTOLOAD_CFG0           0xFF7B
0016 #define RTS5228_AUTOLOAD_CFG1           0xFF7C
0017 #define RTS5228_AUTOLOAD_CFG2           0xFF7D
0018 #define RTS5228_AUTOLOAD_CFG3           0xFF7E
0019 #define RTS5228_AUTOLOAD_CFG4           0xFF7F
0020
0021 #define RTS5228_REG_VREF            0xFE97
0022 #define RTS5228_PWD_SUSPND_EN           (1 << 4)
0023
0024 #define RTS5228_PAD_H3L1            0xFF79
0025 #define PAD_GPIO_H3L1           (1 << 3)
0026
0027 /* SSC_CTL2 0xFC12 */
0028 #define RTS5228_SSC_DEPTH_MASK      0x07
0029 #define RTS5228_SSC_DEPTH_DISALBE   0x00
0030 #define RTS5228_SSC_DEPTH_8M        0x01
0031 #define RTS5228_SSC_DEPTH_4M        0x02
0032 #define RTS5228_SSC_DEPTH_2M        0x03
0033 #define RTS5228_SSC_DEPTH_1M        0x04
0034 #define RTS5228_SSC_DEPTH_512K      0x05
0035 #define RTS5228_SSC_DEPTH_256K      0x06
0036 #define RTS5228_SSC_DEPTH_128K      0x07
0037
0038 /* DMACTL 0xFE2C */
0039 #define RTS5228_DMA_PACK_SIZE_MASK      0xF0
0040
0041 #define RTS5228_REG_LDO12_CFG           0xFF6E
0042 #define RTS5228_LDO12_VO_TUNE_MASK      (0x07<<1)
0043 #define RTS5228_LDO12_100               (0x00<<1)
0044 #define RTS5228_LDO12_105               (0x01<<1)
0045 #define RTS5228_LDO12_110               (0x02<<1)
0046 #define RTS5228_LDO12_115               (0x03<<1)
0047 #define RTS5228_LDO12_120               (0x04<<1)
0048 #define RTS5228_LDO12_125               (0x05<<1)
0049 #define RTS5228_LDO12_130               (0x06<<1)
0050 #define RTS5228_LDO12_135               (0x07<<1)
0051 #define RTS5228_REG_PWD_LDO12           (0x01<<0)
0052
0053 #define RTS5228_REG_LDO12_L12   0xFF6F
0054 #define RTS5228_LDO12_L12_MASK          (0x07<<4)
0055 #define RTS5228_LDO12_L12_120           (0x04<<4)
0056
0057 /* LDO control register */
0058 #define RTS5228_CARD_PWR_CTL            0xFD50
0059 #define RTS5228_PUPDC                   (0x01<<5)
0060
0061 #define RTS5228_LDO1233318_POW_CTL      0xFF70
0062 #define RTS5228_LDO3318_POWERON         (0x01<<3)
0063 #define RTS5228_LDO1_POWEROFF           (0x00<<0)
0064 #define RTS5228_LDO1_SOFTSTART          (0x01<<0)
0065 #define RTS5228_LDO1_FULLON             (0x03<<0)
0066 #define RTS5228_LDO1_POWERON_MASK       (0x03<<0)
0067 #define RTS5228_LDO_POWERON_MASK        (0x0F<<0)
0068
0069 #define RTS5228_DV3318_CFG              0xFF71
0070 #define RTS5228_DV3318_TUNE_MASK        (0x07<<4)
0071 #define RTS5228_DV3318_17               (0x00<<4)
0072 #define RTS5228_DV3318_1V75             (0x01<<4)
0073 #define RTS5228_DV3318_18               (0x02<<4)
0074 #define RTS5228_DV3318_1V85             (0x03<<4)
0075 #define RTS5228_DV3318_19               (0x04<<4)
0076 #define RTS5228_DV3318_33               (0x07<<4)
0077 #define RTS5228_DV3318_SR_MASK          (0x03<<2)
0078 #define RTS5228_DV3318_SR_0             (0x00<<2)
0079 #define RTS5228_DV3318_SR_250           (0x01<<2)
0080 #define RTS5228_DV3318_SR_500           (0x02<<2)
0081 #define RTS5228_DV3318_SR_1000          (0x03<<2)
0082
0083 #define RTS5228_LDO1_CFG0               0xFF72
0084 #define RTS5228_LDO1_OCP_THD_MASK       (0x07<<5)
0085 #define RTS5228_LDO1_OCP_EN             (0x01<<4)
0086 #define RTS5228_LDO1_OCP_LMT_THD_MASK   (0x03<<2)
0087 #define RTS5228_LDO1_OCP_LMT_EN         (0x01<<1)
0088
0089 #define RTS5228_LDO1_OCP_THD_730        (0x00<<5)
0090 #define RTS5228_LDO1_OCP_THD_780        (0x01<<5)
0091 #define RTS5228_LDO1_OCP_THD_860        (0x02<<5)
0092 #define RTS5228_LDO1_OCP_THD_930        (0x03<<5)
0093 #define RTS5228_LDO1_OCP_THD_1000       (0x04<<5)
0094 #define RTS5228_LDO1_OCP_THD_1070       (0x05<<5)
0095 #define RTS5228_LDO1_OCP_THD_1140       (0x06<<5)
0096 #define RTS5228_LDO1_OCP_THD_1220       (0x07<<5)
0097
0098 #define RTS5228_LDO1_LMT_THD_450        (0x00<<2)
0099 #define RTS5228_LDO1_LMT_THD_1000       (0x01<<2)
0100 #define RTS5228_LDO1_LMT_THD_1500       (0x02<<2)
0101 #define RTS5228_LDO1_LMT_THD_2000       (0x03<<2)
0102
0103 #define RTS5228_LDO1_CFG1               0xFF73
0104 #define RTS5228_LDO1_SR_TIME_MASK       (0x03<<6)
0105 #define RTS5228_LDO1_SR_0_0             (0x00<<6)
0106 #define RTS5228_LDO1_SR_0_25            (0x01<<6)
0107 #define RTS5228_LDO1_SR_0_5             (0x02<<6)
0108 #define RTS5228_LDO1_SR_1_0             (0x03<<6)
0109 #define RTS5228_LDO1_TUNE_MASK          (0x07<<1)
0110 #define RTS5228_LDO1_18                 (0x05<<1)
0111 #define RTS5228_LDO1_33                 (0x07<<1)
0112 #define RTS5228_LDO1_PWD_MASK           (0x01<<0)
0113
0114 #define RTS5228_AUXCLK_GAT_CTL          0xFF74
0115
0116 #define RTS5228_REG_RREF_CTL_0          0xFF75
0117 #define RTS5228_FORCE_RREF_EXTL         (0x01<<7)
0118 #define RTS5228_REG_BG33_MASK           (0x07<<0)
0119 #define RTS5228_RREF_12_1V              (0x04<<0)
0120 #define RTS5228_RREF_12_3V              (0x05<<0)
0121
0122 #define RTS5228_REG_RREF_CTL_1          0xFF76
0123
0124 #define RTS5228_REG_RREF_CTL_2          0xFF77
0125 #define RTS5228_TEST_INTL_RREF          (0x01<<7)
0126 #define RTS5228_DGLCH_TIME_MASK         (0x03<<5)
0127 #define RTS5228_DGLCH_TIME_50           (0x00<<5)
0128 #define RTS5228_DGLCH_TIME_75           (0x01<<5)
0129 #define RTS5228_DGLCH_TIME_100          (0x02<<5)
0130 #define RTS5228_DGLCH_TIME_125          (0x03<<5)
0131 #define RTS5228_REG_REXT_TUNE_MASK      (0x1F<<0)
0132
0133 #define RTS5228_REG_PME_FORCE_CTL       0xFF78
0134 #define FORCE_PM_CONTROL        0x20
0135 #define FORCE_PM_VALUE          0x10
0136
0137
0138 /* Single LUN, support SD */
0139 #define DEFAULT_SINGLE      0
0140 #define SD_LUN              1
0141
0142
0143 /* For Change_FPGA_SSCClock Function */
0144 #define MULTIPLY_BY_1    0x00
0145 #define MULTIPLY_BY_2    0x01
0146 #define MULTIPLY_BY_3    0x02
0147 #define MULTIPLY_BY_4    0x03
0148 #define MULTIPLY_BY_5    0x04
0149 #define MULTIPLY_BY_6    0x05
0150 #define MULTIPLY_BY_7    0x06
0151 #define MULTIPLY_BY_8    0x07
0152 #define MULTIPLY_BY_9    0x08
0153 #define MULTIPLY_BY_10   0x09
0154
0155 #define DIVIDE_BY_2      0x01
0156 #define DIVIDE_BY_3      0x02
0157 #define DIVIDE_BY_4      0x03
0158 #define DIVIDE_BY_5      0x04
0159 #define DIVIDE_BY_6      0x05
0160 #define DIVIDE_BY_7      0x06
0161 #define DIVIDE_BY_8      0x07
0162 #define DIVIDE_BY_9      0x08
0163 #define DIVIDE_BY_10     0x09
0164
0165 int rts5228_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
0166         u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
0167
0168 #endif /* RTS5228_H */