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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /* Driver for Realtek PCI-Express card reader
0003  *
0004  * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
0005  *
0006  * Author:
0007  *   Ricky WU <ricky_wu@realtek.com>
0008  *   Rui FENG <rui_feng@realsil.com.cn>
0009  *   Wei WANG <wei_wang@realsil.com.cn>
0010  */
0011 
0012 #include <linux/module.h>
0013 #include <linux/delay.h>
0014 #include <linux/rtsx_pci.h>
0015 
0016 #include "rts5228.h"
0017 #include "rtsx_pcr.h"
0018 
0019 static u8 rts5228_get_ic_version(struct rtsx_pcr *pcr)
0020 {
0021     u8 val;
0022 
0023     rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
0024     return val & IC_VERSION_MASK;
0025 }
0026 
0027 static void rts5228_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
0028 {
0029     u8 driving_3v3[4][3] = {
0030         {0x13, 0x13, 0x13},
0031         {0x96, 0x96, 0x96},
0032         {0x7F, 0x7F, 0x7F},
0033         {0x96, 0x96, 0x96},
0034     };
0035     u8 driving_1v8[4][3] = {
0036         {0x99, 0x99, 0x99},
0037         {0xB5, 0xB5, 0xB5},
0038         {0xE6, 0x7E, 0xFE},
0039         {0x6B, 0x6B, 0x6B},
0040     };
0041     u8 (*driving)[3], drive_sel;
0042 
0043     if (voltage == OUTPUT_3V3) {
0044         driving = driving_3v3;
0045         drive_sel = pcr->sd30_drive_sel_3v3;
0046     } else {
0047         driving = driving_1v8;
0048         drive_sel = pcr->sd30_drive_sel_1v8;
0049     }
0050 
0051     rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
0052              0xFF, driving[drive_sel][0]);
0053 
0054     rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
0055              0xFF, driving[drive_sel][1]);
0056 
0057     rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
0058              0xFF, driving[drive_sel][2]);
0059 }
0060 
0061 static void rtsx5228_fetch_vendor_settings(struct rtsx_pcr *pcr)
0062 {
0063     struct pci_dev *pdev = pcr->pci;
0064     u32 reg;
0065 
0066     /* 0x724~0x727 */
0067     pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
0068     pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
0069 
0070     if (!rtsx_vendor_setting_valid(reg)) {
0071         pcr_dbg(pcr, "skip fetch vendor setting\n");
0072         return;
0073     }
0074     pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
0075     pcr->aspm_en = rtsx_reg_to_aspm(reg);
0076 
0077     /* 0x814~0x817 */
0078     pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
0079     pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
0080 
0081     pcr->rtd3_en = rtsx_reg_to_rtd3(reg);
0082     if (rtsx_check_mmc_support(reg))
0083         pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
0084     pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
0085     if (rtsx_reg_check_reverse_socket(reg))
0086         pcr->flags |= PCR_REVERSE_SOCKET;
0087 }
0088 
0089 static int rts5228_optimize_phy(struct rtsx_pcr *pcr)
0090 {
0091     return rtsx_pci_write_phy_register(pcr, 0x07, 0x8F40);
0092 }
0093 
0094 static void rts5228_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
0095 {
0096     /* Set relink_time to 0 */
0097     rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
0098     rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
0099     rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
0100                 RELINK_TIME_MASK, 0);
0101 
0102     rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
0103             D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
0104 
0105     if (!runtime) {
0106         rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1,
0107                 CD_RESUME_EN_MASK, 0);
0108         rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
0109         rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL,
0110                 FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
0111     }
0112 
0113     rtsx_pci_write_register(pcr, FPDCTL,
0114         SSC_POWER_DOWN, SSC_POWER_DOWN);
0115 }
0116 
0117 static int rts5228_enable_auto_blink(struct rtsx_pcr *pcr)
0118 {
0119     return rtsx_pci_write_register(pcr, OLT_LED_CTL,
0120         LED_SHINE_MASK, LED_SHINE_EN);
0121 }
0122 
0123 static int rts5228_disable_auto_blink(struct rtsx_pcr *pcr)
0124 {
0125     return rtsx_pci_write_register(pcr, OLT_LED_CTL,
0126         LED_SHINE_MASK, LED_SHINE_DISABLE);
0127 }
0128 
0129 static int rts5228_turn_on_led(struct rtsx_pcr *pcr)
0130 {
0131     return rtsx_pci_write_register(pcr, GPIO_CTL,
0132         0x02, 0x02);
0133 }
0134 
0135 static int rts5228_turn_off_led(struct rtsx_pcr *pcr)
0136 {
0137     return rtsx_pci_write_register(pcr, GPIO_CTL,
0138         0x02, 0x00);
0139 }
0140 
0141 /* SD Pull Control Enable:
0142  *     SD_DAT[3:0] ==> pull up
0143  *     SD_CD       ==> pull up
0144  *     SD_WP       ==> pull up
0145  *     SD_CMD      ==> pull up
0146  *     SD_CLK      ==> pull down
0147  */
0148 static const u32 rts5228_sd_pull_ctl_enable_tbl[] = {
0149     RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
0150     RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
0151     0,
0152 };
0153 
0154 /* SD Pull Control Disable:
0155  *     SD_DAT[3:0] ==> pull down
0156  *     SD_CD       ==> pull up
0157  *     SD_WP       ==> pull down
0158  *     SD_CMD      ==> pull down
0159  *     SD_CLK      ==> pull down
0160  */
0161 static const u32 rts5228_sd_pull_ctl_disable_tbl[] = {
0162     RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
0163     RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
0164     0,
0165 };
0166 
0167 static int rts5228_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
0168 {
0169     rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
0170         | SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
0171     rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
0172     rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
0173             CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
0174     rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
0175 
0176     return 0;
0177 }
0178 
0179 static int rts5228_card_power_on(struct rtsx_pcr *pcr, int card)
0180 {
0181     struct rtsx_cr_option *option = &pcr->option;
0182 
0183     if (option->ocp_en)
0184         rtsx_pci_enable_ocp(pcr);
0185 
0186     rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,
0187             CFG_SD_POW_AUTO_PD, CFG_SD_POW_AUTO_PD);
0188 
0189     rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG1,
0190             RTS5228_LDO1_TUNE_MASK, RTS5228_LDO1_33);
0191 
0192     rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
0193             RTS5228_LDO1_POWERON_MASK, RTS5228_LDO1_SOFTSTART);
0194     mdelay(2);
0195     rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
0196             RTS5228_LDO1_POWERON_MASK, RTS5228_LDO1_FULLON);
0197 
0198 
0199     rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
0200             RTS5228_LDO3318_POWERON, RTS5228_LDO3318_POWERON);
0201 
0202     msleep(20);
0203 
0204     rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
0205 
0206     /* Initialize SD_CFG1 register */
0207     rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
0208             SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1BIT);
0209 
0210     rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
0211             0xFF, SD20_RX_POS_EDGE);
0212     rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
0213     rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
0214             SD_STOP | SD_CLR_ERR);
0215 
0216     /* Reset SD_CFG3 register */
0217     rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
0218     rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
0219             SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 |
0220             SD30_CLK_STOP_CFG0, 0);
0221 
0222     if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
0223         pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
0224         rts5228_sd_set_sample_push_timing_sd30(pcr);
0225 
0226     return 0;
0227 }
0228 
0229 static int rts5228_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
0230 {
0231     int err;
0232     u16 val = 0;
0233 
0234     rtsx_pci_write_register(pcr, RTS5228_CARD_PWR_CTL,
0235             RTS5228_PUPDC, RTS5228_PUPDC);
0236 
0237     switch (voltage) {
0238     case OUTPUT_3V3:
0239         rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
0240         val |= PHY_TUNE_SDBUS_33;
0241         err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
0242         if (err < 0)
0243             return err;
0244 
0245         rtsx_pci_write_register(pcr, RTS5228_DV3318_CFG,
0246                 RTS5228_DV3318_TUNE_MASK, RTS5228_DV3318_33);
0247         rtsx_pci_write_register(pcr, SD_PAD_CTL,
0248                 SD_IO_USING_1V8, 0);
0249         break;
0250     case OUTPUT_1V8:
0251         rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
0252         val &= ~PHY_TUNE_SDBUS_33;
0253         err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
0254         if (err < 0)
0255             return err;
0256 
0257         rtsx_pci_write_register(pcr, RTS5228_DV3318_CFG,
0258                 RTS5228_DV3318_TUNE_MASK, RTS5228_DV3318_18);
0259         rtsx_pci_write_register(pcr, SD_PAD_CTL,
0260                 SD_IO_USING_1V8, SD_IO_USING_1V8);
0261         break;
0262     default:
0263         return -EINVAL;
0264     }
0265 
0266     /* set pad drive */
0267     rts5228_fill_driving(pcr, voltage);
0268 
0269     return 0;
0270 }
0271 
0272 static void rts5228_stop_cmd(struct rtsx_pcr *pcr)
0273 {
0274     rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
0275     rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
0276     rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0,
0277                 RTS5260_DMA_RST | RTS5260_ADMA3_RST,
0278                 RTS5260_DMA_RST | RTS5260_ADMA3_RST);
0279     rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
0280 }
0281 
0282 static void rts5228_card_before_power_off(struct rtsx_pcr *pcr)
0283 {
0284     rts5228_stop_cmd(pcr);
0285     rts5228_switch_output_voltage(pcr, OUTPUT_3V3);
0286 }
0287 
0288 static void rts5228_enable_ocp(struct rtsx_pcr *pcr)
0289 {
0290     u8 val = 0;
0291 
0292     val = SD_OCP_INT_EN | SD_DETECT_EN;
0293     rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
0294     rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
0295             RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN,
0296             RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN);
0297 }
0298 
0299 static void rts5228_disable_ocp(struct rtsx_pcr *pcr)
0300 {
0301     u8 mask = 0;
0302 
0303     mask = SD_OCP_INT_EN | SD_DETECT_EN;
0304     rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
0305     rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
0306             RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, 0);
0307 }
0308 
0309 static int rts5228_card_power_off(struct rtsx_pcr *pcr, int card)
0310 {
0311     int err = 0;
0312 
0313     rts5228_card_before_power_off(pcr);
0314     err = rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL,
0315                 RTS5228_LDO_POWERON_MASK, 0);
0316     rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0, CFG_SD_POW_AUTO_PD, 0);
0317 
0318     if (pcr->option.ocp_en)
0319         rtsx_pci_disable_ocp(pcr);
0320 
0321     return err;
0322 }
0323 
0324 static void rts5228_init_ocp(struct rtsx_pcr *pcr)
0325 {
0326     struct rtsx_cr_option *option = &pcr->option;
0327 
0328     if (option->ocp_en) {
0329         u8 mask, val;
0330 
0331         rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
0332             RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN,
0333             RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN);
0334 
0335         rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
0336             RTS5228_LDO1_OCP_THD_MASK, option->sd_800mA_ocp_thd);
0337 
0338         rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
0339             RTS5228_LDO1_OCP_LMT_THD_MASK,
0340             RTS5228_LDO1_LMT_THD_1500);
0341 
0342         rtsx_pci_read_register(pcr, RTS5228_LDO1_CFG0, &val);
0343 
0344         mask = SD_OCP_GLITCH_MASK;
0345         val = pcr->hw_param.ocp_glitch;
0346         rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
0347 
0348         rts5228_enable_ocp(pcr);
0349 
0350     } else {
0351         rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0,
0352             RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, 0);
0353     }
0354 }
0355 
0356 static void rts5228_clear_ocpstat(struct rtsx_pcr *pcr)
0357 {
0358     u8 mask = 0;
0359     u8 val = 0;
0360 
0361     mask = SD_OCP_INT_CLR | SD_OC_CLR;
0362     val = SD_OCP_INT_CLR | SD_OC_CLR;
0363 
0364     rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
0365 
0366     udelay(1000);
0367     rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
0368 
0369 }
0370 
0371 static void rts5228_process_ocp(struct rtsx_pcr *pcr)
0372 {
0373     if (!pcr->option.ocp_en)
0374         return;
0375 
0376     rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
0377 
0378     if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
0379         rts5228_clear_ocpstat(pcr);
0380         rts5228_card_power_off(pcr, RTSX_SD_CARD);
0381         rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
0382         pcr->ocp_stat = 0;
0383     }
0384 
0385 }
0386 
0387 static void rts5228_init_from_cfg(struct rtsx_pcr *pcr)
0388 {
0389     struct pci_dev *pdev = pcr->pci;
0390     int l1ss;
0391     u32 lval;
0392     struct rtsx_cr_option *option = &pcr->option;
0393 
0394     l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
0395     if (!l1ss)
0396         return;
0397 
0398     pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
0399 
0400     if (0 == (lval & 0x0F))
0401         rtsx_pci_enable_oobs_polling(pcr);
0402     else
0403         rtsx_pci_disable_oobs_polling(pcr);
0404 
0405     if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
0406         rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
0407     else
0408         rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
0409 
0410     if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
0411         rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
0412     else
0413         rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
0414 
0415     if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
0416         rtsx_set_dev_flag(pcr, PM_L1_1_EN);
0417     else
0418         rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
0419 
0420     if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
0421         rtsx_set_dev_flag(pcr, PM_L1_2_EN);
0422     else
0423         rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
0424 
0425     rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
0426     if (option->ltr_en) {
0427         u16 val;
0428 
0429         pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
0430         if (val & PCI_EXP_DEVCTL2_LTR_EN) {
0431             option->ltr_enabled = true;
0432             option->ltr_active = true;
0433             rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
0434         } else {
0435             option->ltr_enabled = false;
0436         }
0437     }
0438 
0439     if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
0440                 | PM_L1_1_EN | PM_L1_2_EN))
0441         option->force_clkreq_0 = false;
0442     else
0443         option->force_clkreq_0 = true;
0444 }
0445 
0446 static int rts5228_extra_init_hw(struct rtsx_pcr *pcr)
0447 {
0448     struct rtsx_cr_option *option = &pcr->option;
0449 
0450     rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1,
0451             CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
0452 
0453     rts5228_init_from_cfg(pcr);
0454 
0455     rtsx_pci_write_register(pcr, L1SUB_CONFIG1,
0456             AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE);
0457     rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0);
0458 
0459     rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
0460             FUNC_FORCE_UPME_XMT_DBG, FUNC_FORCE_UPME_XMT_DBG);
0461 
0462     rtsx_pci_write_register(pcr, PCLK_CTL,
0463             PCLK_MODE_SEL, PCLK_MODE_SEL);
0464 
0465     rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
0466     rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, CLK_PM_EN, CLK_PM_EN);
0467 
0468     /* LED shine disabled, set initial shine cycle period */
0469     rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02);
0470 
0471     /* Configure driving */
0472     rts5228_fill_driving(pcr, OUTPUT_3V3);
0473 
0474     if (pcr->flags & PCR_REVERSE_SOCKET)
0475         rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30);
0476     else
0477         rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);
0478 
0479     /*
0480      * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
0481      * to drive low, and we forcibly request clock.
0482      */
0483     if (option->force_clkreq_0)
0484         rtsx_pci_write_register(pcr, PETXCFG,
0485                  FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
0486     else
0487         rtsx_pci_write_register(pcr, PETXCFG,
0488                  FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
0489 
0490     rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB);
0491 
0492     if (pcr->rtd3_en) {
0493         rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x01);
0494         rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL,
0495                 FORCE_PM_CONTROL | FORCE_PM_VALUE,
0496                 FORCE_PM_CONTROL | FORCE_PM_VALUE);
0497     } else {
0498         rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
0499         rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL,
0500                 FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
0501     }
0502     rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, D3_DELINK_MODE_EN, 0x00);
0503 
0504     return 0;
0505 }
0506 
0507 static void rts5228_enable_aspm(struct rtsx_pcr *pcr, bool enable)
0508 {
0509     u8 mask, val;
0510 
0511     if (pcr->aspm_enabled == enable)
0512         return;
0513 
0514     mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
0515     val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
0516     val |= (pcr->aspm_en & 0x02);
0517     rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
0518     pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
0519                        PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en);
0520     pcr->aspm_enabled = enable;
0521 }
0522 
0523 static void rts5228_disable_aspm(struct rtsx_pcr *pcr, bool enable)
0524 {
0525     u8 mask, val;
0526 
0527     if (pcr->aspm_enabled == enable)
0528         return;
0529 
0530     pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
0531                        PCI_EXP_LNKCTL_ASPMC, 0);
0532     mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
0533     val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
0534     rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
0535     rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
0536     mdelay(10);
0537     pcr->aspm_enabled = enable;
0538 }
0539 
0540 static void rts5228_set_aspm(struct rtsx_pcr *pcr, bool enable)
0541 {
0542     if (enable)
0543         rts5228_enable_aspm(pcr, true);
0544     else
0545         rts5228_disable_aspm(pcr, false);
0546 }
0547 
0548 static void rts5228_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
0549 {
0550     struct rtsx_cr_option *option = &pcr->option;
0551     int aspm_L1_1, aspm_L1_2;
0552     u8 val = 0;
0553 
0554     aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
0555     aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
0556 
0557     if (active) {
0558         /* run, latency: 60us */
0559         if (aspm_L1_1)
0560             val = option->ltr_l1off_snooze_sspwrgate;
0561     } else {
0562         /* l1off, latency: 300us */
0563         if (aspm_L1_2)
0564             val = option->ltr_l1off_sspwrgate;
0565     }
0566 
0567     rtsx_set_l1off_sub(pcr, val);
0568 }
0569 
0570 static const struct pcr_ops rts5228_pcr_ops = {
0571     .fetch_vendor_settings = rtsx5228_fetch_vendor_settings,
0572     .turn_on_led = rts5228_turn_on_led,
0573     .turn_off_led = rts5228_turn_off_led,
0574     .extra_init_hw = rts5228_extra_init_hw,
0575     .enable_auto_blink = rts5228_enable_auto_blink,
0576     .disable_auto_blink = rts5228_disable_auto_blink,
0577     .card_power_on = rts5228_card_power_on,
0578     .card_power_off = rts5228_card_power_off,
0579     .switch_output_voltage = rts5228_switch_output_voltage,
0580     .force_power_down = rts5228_force_power_down,
0581     .stop_cmd = rts5228_stop_cmd,
0582     .set_aspm = rts5228_set_aspm,
0583     .set_l1off_cfg_sub_d0 = rts5228_set_l1off_cfg_sub_d0,
0584     .enable_ocp = rts5228_enable_ocp,
0585     .disable_ocp = rts5228_disable_ocp,
0586     .init_ocp = rts5228_init_ocp,
0587     .process_ocp = rts5228_process_ocp,
0588     .clear_ocpstat = rts5228_clear_ocpstat,
0589     .optimize_phy = rts5228_optimize_phy,
0590 };
0591 
0592 
0593 static inline u8 double_ssc_depth(u8 depth)
0594 {
0595     return ((depth > 1) ? (depth - 1) : depth);
0596 }
0597 
0598 int rts5228_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
0599         u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
0600 {
0601     int err, clk;
0602     u16 n;
0603     u8 clk_divider, mcu_cnt, div;
0604     static const u8 depth[] = {
0605         [RTSX_SSC_DEPTH_4M] = RTS5228_SSC_DEPTH_4M,
0606         [RTSX_SSC_DEPTH_2M] = RTS5228_SSC_DEPTH_2M,
0607         [RTSX_SSC_DEPTH_1M] = RTS5228_SSC_DEPTH_1M,
0608         [RTSX_SSC_DEPTH_500K] = RTS5228_SSC_DEPTH_512K,
0609     };
0610 
0611     if (initial_mode) {
0612         /* We use 250k(around) here, in initial stage */
0613         clk_divider = SD_CLK_DIVIDE_128;
0614         card_clock = 30000000;
0615     } else {
0616         clk_divider = SD_CLK_DIVIDE_0;
0617     }
0618     err = rtsx_pci_write_register(pcr, SD_CFG1,
0619             SD_CLK_DIVIDE_MASK, clk_divider);
0620     if (err < 0)
0621         return err;
0622 
0623     card_clock /= 1000000;
0624     pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
0625 
0626     clk = card_clock;
0627     if (!initial_mode && double_clk)
0628         clk = card_clock * 2;
0629     pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
0630         clk, pcr->cur_clock);
0631 
0632     if (clk == pcr->cur_clock)
0633         return 0;
0634 
0635     if (pcr->ops->conv_clk_and_div_n)
0636         n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
0637     else
0638         n = clk - 4;
0639     if ((clk <= 4) || (n > 396))
0640         return -EINVAL;
0641 
0642     mcu_cnt = 125/clk + 3;
0643     if (mcu_cnt > 15)
0644         mcu_cnt = 15;
0645 
0646     div = CLK_DIV_1;
0647     while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) {
0648         if (pcr->ops->conv_clk_and_div_n) {
0649             int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
0650                     DIV_N_TO_CLK) * 2;
0651             n = pcr->ops->conv_clk_and_div_n(dbl_clk,
0652                     CLK_TO_DIV_N);
0653         } else {
0654             n = (n + 4) * 2 - 4;
0655         }
0656         div++;
0657     }
0658 
0659     n = (n / 2) - 1;
0660     pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
0661 
0662     ssc_depth = depth[ssc_depth];
0663     if (double_clk)
0664         ssc_depth = double_ssc_depth(ssc_depth);
0665 
0666     if (ssc_depth) {
0667         if (div == CLK_DIV_2) {
0668             if (ssc_depth > 1)
0669                 ssc_depth -= 1;
0670             else
0671                 ssc_depth = RTS5228_SSC_DEPTH_8M;
0672         } else if (div == CLK_DIV_4) {
0673             if (ssc_depth > 2)
0674                 ssc_depth -= 2;
0675             else
0676                 ssc_depth = RTS5228_SSC_DEPTH_8M;
0677         } else if (div == CLK_DIV_8) {
0678             if (ssc_depth > 3)
0679                 ssc_depth -= 3;
0680             else
0681                 ssc_depth = RTS5228_SSC_DEPTH_8M;
0682         }
0683     } else {
0684         ssc_depth = 0;
0685     }
0686     pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
0687 
0688     rtsx_pci_init_cmd(pcr);
0689     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
0690                 CLK_LOW_FREQ, CLK_LOW_FREQ);
0691     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
0692             0xFF, (div << 4) | mcu_cnt);
0693     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
0694     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
0695             SSC_DEPTH_MASK, ssc_depth);
0696     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
0697     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
0698     if (vpclk) {
0699         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
0700                 PHASE_NOT_RESET, 0);
0701         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
0702                 PHASE_NOT_RESET, 0);
0703         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
0704                 PHASE_NOT_RESET, PHASE_NOT_RESET);
0705         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
0706                 PHASE_NOT_RESET, PHASE_NOT_RESET);
0707     }
0708 
0709     err = rtsx_pci_send_cmd(pcr, 2000);
0710     if (err < 0)
0711         return err;
0712 
0713     /* Wait SSC clock stable */
0714     udelay(SSC_CLOCK_STABLE_WAIT);
0715     err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
0716     if (err < 0)
0717         return err;
0718 
0719     pcr->cur_clock = clk;
0720     return 0;
0721 
0722 }
0723 
0724 void rts5228_init_params(struct rtsx_pcr *pcr)
0725 {
0726     struct rtsx_cr_option *option = &pcr->option;
0727     struct rtsx_hw_param *hw_param = &pcr->hw_param;
0728 
0729     pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
0730     pcr->num_slots = 1;
0731     pcr->ops = &rts5228_pcr_ops;
0732 
0733     pcr->flags = 0;
0734     pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
0735     pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
0736     pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
0737     pcr->aspm_en = ASPM_L1_EN;
0738     pcr->aspm_mode = ASPM_MODE_REG;
0739     pcr->tx_initial_phase = SET_CLOCK_PHASE(28, 27, 11);
0740     pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
0741 
0742     pcr->ic_version = rts5228_get_ic_version(pcr);
0743     pcr->sd_pull_ctl_enable_tbl = rts5228_sd_pull_ctl_enable_tbl;
0744     pcr->sd_pull_ctl_disable_tbl = rts5228_sd_pull_ctl_disable_tbl;
0745 
0746     pcr->reg_pm_ctrl3 = RTS5228_AUTOLOAD_CFG3;
0747 
0748     option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
0749                 | LTR_L1SS_PWR_GATE_EN);
0750     option->ltr_en = true;
0751 
0752     /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
0753     option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
0754     option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
0755     option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
0756     option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
0757     option->ltr_l1off_sspwrgate = 0x7F;
0758     option->ltr_l1off_snooze_sspwrgate = 0x78;
0759 
0760     option->ocp_en = 1;
0761     hw_param->interrupt_en |= SD_OC_INT_EN;
0762     hw_param->ocp_glitch =  SD_OCP_GLITCH_800U;
0763     option->sd_800mA_ocp_thd =  RTS5228_LDO1_OCP_THD_930;
0764 }
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