misc/cardreader/rts5227.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /* Driver for Realtek PCI-Express card reader
0003  *
0004  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
0005  *
0006  * Author:
0007  *   Wei WANG <wei_wang@realsil.com.cn>
0008  *   Roger Tseng <rogerable@realtek.com>
0009  */
0010
0011 #include <linux/module.h>
0012 #include <linux/delay.h>
0013 #include <linux/rtsx_pci.h>
0014
0015 #include "rtsx_pcr.h"
0016
0017 static u8 rts5227_get_ic_version(struct rtsx_pcr *pcr)
0018 {
0019     u8 val;
0020
0021     rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
0022     return val & 0x0F;
0023 }
0024
0025 static void rts5227_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
0026 {
0027     u8 driving_3v3[4][3] = {
0028         {0x13, 0x13, 0x13},
0029         {0x96, 0x96, 0x96},
0030         {0x7F, 0x7F, 0x7F},
0031         {0x96, 0x96, 0x96},
0032     };
0033     u8 driving_1v8[4][3] = {
0034         {0x99, 0x99, 0x99},
0035         {0xAA, 0xAA, 0xAA},
0036         {0xFE, 0xFE, 0xFE},
0037         {0xB3, 0xB3, 0xB3},
0038     };
0039     u8 (*driving)[3], drive_sel;
0040
0041     if (voltage == OUTPUT_3V3) {
0042         driving = driving_3v3;
0043         drive_sel = pcr->sd30_drive_sel_3v3;
0044     } else {
0045         driving = driving_1v8;
0046         drive_sel = pcr->sd30_drive_sel_1v8;
0047     }
0048
0049     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
0050             0xFF, driving[drive_sel][0]);
0051     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
0052             0xFF, driving[drive_sel][1]);
0053     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
0054             0xFF, driving[drive_sel][2]);
0055 }
0056
0057 static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
0058 {
0059     struct pci_dev *pdev = pcr->pci;
0060     u32 reg;
0061
0062     pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
0063     pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
0064
0065     if (!rtsx_vendor_setting_valid(reg))
0066         return;
0067
0068     pcr->aspm_en = rtsx_reg_to_aspm(reg);
0069     pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
0070     pcr->card_drive_sel &= 0x3F;
0071     pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
0072
0073     pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
0074     pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
0075     if (CHK_PCI_PID(pcr, 0x522A))
0076         pcr->rtd3_en = rtsx_reg_to_rtd3(reg);
0077     if (rtsx_check_mmc_support(reg))
0078         pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
0079     pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
0080     if (rtsx_reg_check_reverse_socket(reg))
0081         pcr->flags |= PCR_REVERSE_SOCKET;
0082 }
0083
0084 static void rts5227_init_from_cfg(struct rtsx_pcr *pcr)
0085 {
0086     struct pci_dev *pdev = pcr->pci;
0087     int l1ss;
0088     u32 lval;
0089     struct rtsx_cr_option *option = &pcr->option;
0090
0091     l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
0092     if (!l1ss)
0093         return;
0094
0095     pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
0096
0097     if (CHK_PCI_PID(pcr, 0x522A)) {
0098         if (0 == (lval & 0x0F))
0099             rtsx_pci_enable_oobs_polling(pcr);
0100         else
0101             rtsx_pci_disable_oobs_polling(pcr);
0102     }
0103
0104     if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
0105         rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
0106     else
0107         rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
0108
0109     if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
0110         rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
0111     else
0112         rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
0113
0114     if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
0115         rtsx_set_dev_flag(pcr, PM_L1_1_EN);
0116     else
0117         rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
0118
0119     if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
0120         rtsx_set_dev_flag(pcr, PM_L1_2_EN);
0121     else
0122         rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
0123
0124     if (option->ltr_en) {
0125         u16 val;
0126
0127         pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
0128         if (val & PCI_EXP_DEVCTL2_LTR_EN) {
0129             option->ltr_enabled = true;
0130             option->ltr_active = true;
0131             rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
0132         } else {
0133             option->ltr_enabled = false;
0134         }
0135     }
0136
0137     if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
0138                 | PM_L1_1_EN | PM_L1_2_EN))
0139         option->force_clkreq_0 = false;
0140     else
0141         option->force_clkreq_0 = true;
0142
0143 }
0144
0145 static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
0146 {
0147     u16 cap;
0148     struct rtsx_cr_option *option = &pcr->option;
0149
0150     rts5227_init_from_cfg(pcr);
0151     rtsx_pci_init_cmd(pcr);
0152
0153     /* Configure GPIO as output */
0154     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
0155     /* Reset ASPM state to default value */
0156     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
0157     /* Switch LDO3318 source from DV33 to card_3v3 */
0158     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
0159     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
0160     /* LED shine disabled, set initial shine cycle period */
0161     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
0162     /* Configure LTR */
0163     pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap);
0164     if (cap & PCI_EXP_DEVCTL2_LTR_EN)
0165         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3);
0166     /* Configure OBFF */
0167     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03);
0168     /* Configure driving */
0169     rts5227_fill_driving(pcr, OUTPUT_3V3);
0170     /* Configure force_clock_req */
0171     if (pcr->flags & PCR_REVERSE_SOCKET)
0172         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x30);
0173     else
0174         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x00);
0175
0176     if (CHK_PCI_PID(pcr, 0x522A))
0177         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_AUTOLOAD_CFG1,
0178             CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
0179
0180     if (pcr->rtd3_en) {
0181         if (CHK_PCI_PID(pcr, 0x522A)) {
0182             rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_PM_CTRL3, 0x01, 0x01);
0183             rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_PME_FORCE_CTL, 0x30, 0x30);
0184         } else {
0185             rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x01, 0x01);
0186             rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PME_FORCE_CTL, 0xFF, 0x33);
0187         }
0188     } else {
0189         if (CHK_PCI_PID(pcr, 0x522A)) {
0190             rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_PM_CTRL3, 0x01, 0x00);
0191             rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_PME_FORCE_CTL, 0x30, 0x20);
0192         } else {
0193             rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PME_FORCE_CTL, 0xFF, 0x30);
0194             rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x01, 0x00);
0195         }
0196     }
0197
0198     if (option->force_clkreq_0)
0199         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
0200                 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
0201     else
0202         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
0203                 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
0204
0205     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, pcr->reg_pm_ctrl3, 0x10, 0x00);
0206
0207     return rtsx_pci_send_cmd(pcr, 100);
0208 }
0209
0210 static int rts5227_optimize_phy(struct rtsx_pcr *pcr)
0211 {
0212     int err;
0213
0214     err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
0215     if (err < 0)
0216         return err;
0217
0218     /* Optimize RX sensitivity */
0219     return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
0220 }
0221
0222 static int rts5227_turn_on_led(struct rtsx_pcr *pcr)
0223 {
0224     return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
0225 }
0226
0227 static int rts5227_turn_off_led(struct rtsx_pcr *pcr)
0228 {
0229     return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
0230 }
0231
0232 static int rts5227_enable_auto_blink(struct rtsx_pcr *pcr)
0233 {
0234     return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
0235 }
0236
0237 static int rts5227_disable_auto_blink(struct rtsx_pcr *pcr)
0238 {
0239     return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
0240 }
0241
0242 static int rts5227_card_power_on(struct rtsx_pcr *pcr, int card)
0243 {
0244     int err;
0245
0246     if (pcr->option.ocp_en)
0247         rtsx_pci_enable_ocp(pcr);
0248
0249     rtsx_pci_init_cmd(pcr);
0250     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
0251             SD_POWER_MASK, SD_PARTIAL_POWER_ON);
0252
0253     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
0254             LDO3318_PWR_MASK, 0x02);
0255
0256     err = rtsx_pci_send_cmd(pcr, 100);
0257     if (err < 0)
0258         return err;
0259
0260     /* To avoid too large in-rush current */
0261     msleep(20);
0262     rtsx_pci_init_cmd(pcr);
0263     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
0264             SD_POWER_MASK, SD_POWER_ON);
0265
0266     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
0267             LDO3318_PWR_MASK, 0x06);
0268
0269     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
0270             SD_OUTPUT_EN, SD_OUTPUT_EN);
0271     rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
0272             MS_OUTPUT_EN, MS_OUTPUT_EN);
0273     return rtsx_pci_send_cmd(pcr, 100);
0274 }
0275
0276 static int rts5227_card_power_off(struct rtsx_pcr *pcr, int card)
0277 {
0278     if (pcr->option.ocp_en)
0279         rtsx_pci_disable_ocp(pcr);
0280
0281     rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK |
0282             PMOS_STRG_MASK, SD_POWER_OFF | PMOS_STRG_400mA);
0283     rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0X00);
0284
0285     return 0;
0286 }
0287
0288 static int rts5227_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
0289 {
0290     int err;
0291
0292     if (voltage == OUTPUT_3V3) {
0293         err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
0294         if (err < 0)
0295             return err;
0296     } else if (voltage == OUTPUT_1V8) {
0297         err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
0298         if (err < 0)
0299             return err;
0300         err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C80 | 0x24);
0301         if (err < 0)
0302             return err;
0303     } else {
0304         return -EINVAL;
0305     }
0306
0307     /* set pad drive */
0308     rtsx_pci_init_cmd(pcr);
0309     rts5227_fill_driving(pcr, voltage);
0310     return rtsx_pci_send_cmd(pcr, 100);
0311 }
0312
0313 static const struct pcr_ops rts5227_pcr_ops = {
0314     .fetch_vendor_settings = rts5227_fetch_vendor_settings,
0315     .extra_init_hw = rts5227_extra_init_hw,
0316     .optimize_phy = rts5227_optimize_phy,
0317     .turn_on_led = rts5227_turn_on_led,
0318     .turn_off_led = rts5227_turn_off_led,
0319     .enable_auto_blink = rts5227_enable_auto_blink,
0320     .disable_auto_blink = rts5227_disable_auto_blink,
0321     .card_power_on = rts5227_card_power_on,
0322     .card_power_off = rts5227_card_power_off,
0323     .switch_output_voltage = rts5227_switch_output_voltage,
0324     .cd_deglitch = NULL,
0325     .conv_clk_and_div_n = NULL,
0326 };
0327
0328 /* SD Pull Control Enable:
0329  *     SD_DAT[3:0] ==> pull up
0330  *     SD_CD       ==> pull up
0331  *     SD_WP       ==> pull up
0332  *     SD_CMD      ==> pull up
0333  *     SD_CLK      ==> pull down
0334  */
0335 static const u32 rts5227_sd_pull_ctl_enable_tbl[] = {
0336     RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
0337     RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
0338     0,
0339 };
0340
0341 /* SD Pull Control Disable:
0342  *     SD_DAT[3:0] ==> pull down
0343  *     SD_CD       ==> pull up
0344  *     SD_WP       ==> pull down
0345  *     SD_CMD      ==> pull down
0346  *     SD_CLK      ==> pull down
0347  */
0348 static const u32 rts5227_sd_pull_ctl_disable_tbl[] = {
0349     RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
0350     RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
0351     0,
0352 };
0353
0354 /* MS Pull Control Enable:
0355  *     MS CD       ==> pull up
0356  *     others      ==> pull down
0357  */
0358 static const u32 rts5227_ms_pull_ctl_enable_tbl[] = {
0359     RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
0360     RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
0361     0,
0362 };
0363
0364 /* MS Pull Control Disable:
0365  *     MS CD       ==> pull up
0366  *     others      ==> pull down
0367  */
0368 static const u32 rts5227_ms_pull_ctl_disable_tbl[] = {
0369     RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
0370     RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
0371     0,
0372 };
0373
0374 void rts5227_init_params(struct rtsx_pcr *pcr)
0375 {
0376     pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
0377     pcr->num_slots = 2;
0378     pcr->ops = &rts5227_pcr_ops;
0379
0380     pcr->flags = 0;
0381     pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
0382     pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
0383     pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
0384     pcr->aspm_en = ASPM_L1_EN;
0385     pcr->aspm_mode = ASPM_MODE_CFG;
0386     pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
0387     pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7);
0388
0389     pcr->ic_version = rts5227_get_ic_version(pcr);
0390     pcr->sd_pull_ctl_enable_tbl = rts5227_sd_pull_ctl_enable_tbl;
0391     pcr->sd_pull_ctl_disable_tbl = rts5227_sd_pull_ctl_disable_tbl;
0392     pcr->ms_pull_ctl_enable_tbl = rts5227_ms_pull_ctl_enable_tbl;
0393     pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl;
0394
0395     pcr->reg_pm_ctrl3 = PM_CTRL3;
0396 }
0397
0398 static int rts522a_optimize_phy(struct rtsx_pcr *pcr)
0399 {
0400     int err;
0401
0402     err = rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3, D3_DELINK_MODE_EN,
0403         0x00);
0404     if (err < 0)
0405         return err;
0406
0407     if (is_version(pcr, 0x522A, IC_VER_A)) {
0408         err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
0409             PHY_RCR2_INIT_27S);
0410         if (err)
0411             return err;
0412
0413         rtsx_pci_write_phy_register(pcr, PHY_RCR1, PHY_RCR1_INIT_27S);
0414         rtsx_pci_write_phy_register(pcr, PHY_FLD0, PHY_FLD0_INIT_27S);
0415         rtsx_pci_write_phy_register(pcr, PHY_FLD3, PHY_FLD3_INIT_27S);
0416         rtsx_pci_write_phy_register(pcr, PHY_FLD4, PHY_FLD4_INIT_27S);
0417     }
0418
0419     return 0;
0420 }
0421
0422 static int rts522a_extra_init_hw(struct rtsx_pcr *pcr)
0423 {
0424     rts5227_extra_init_hw(pcr);
0425
0426     /* Power down OCP for power consumption */
0427     if (!pcr->card_exist)
0428         rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN,
0429                 OC_POWER_DOWN);
0430
0431     rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, FUNC_FORCE_UPME_XMT_DBG,
0432         FUNC_FORCE_UPME_XMT_DBG);
0433     rtsx_pci_write_register(pcr, PCLK_CTL, 0x04, 0x04);
0434     rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
0435     rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 0xFF, 0x11);
0436
0437     return 0;
0438 }
0439
0440 static int rts522a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
0441 {
0442     int err;
0443
0444     if (voltage == OUTPUT_3V3) {
0445         err = rtsx_pci_write_phy_register(pcr, 0x08, 0x57E4);
0446         if (err < 0)
0447             return err;
0448     } else if (voltage == OUTPUT_1V8) {
0449         err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
0450         if (err < 0)
0451             return err;
0452         err = rtsx_pci_write_phy_register(pcr, 0x08, 0x54A4);
0453         if (err < 0)
0454             return err;
0455     } else {
0456         return -EINVAL;
0457     }
0458
0459     /* set pad drive */
0460     rtsx_pci_init_cmd(pcr);
0461     rts5227_fill_driving(pcr, voltage);
0462     return rtsx_pci_send_cmd(pcr, 100);
0463 }
0464
0465 static void rts522a_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
0466 {
0467     /* Set relink_time to 0 */
0468     rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
0469     rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
0470     rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
0471                 RELINK_TIME_MASK, 0);
0472
0473     rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3,
0474             D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
0475
0476     if (!runtime) {
0477         rtsx_pci_write_register(pcr, RTS522A_AUTOLOAD_CFG1,
0478                 CD_RESUME_EN_MASK, 0);
0479         rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3, 0x01, 0x00);
0480         rtsx_pci_write_register(pcr, RTS522A_PME_FORCE_CTL, 0x30, 0x20);
0481     }
0482
0483     rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN);
0484 }
0485
0486
0487 static void rts522a_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
0488 {
0489     struct rtsx_cr_option *option = &pcr->option;
0490     int aspm_L1_1, aspm_L1_2;
0491     u8 val = 0;
0492
0493     aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
0494     aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
0495
0496     if (active) {
0497         /* run, latency: 60us */
0498         if (aspm_L1_1)
0499             val = option->ltr_l1off_snooze_sspwrgate;
0500     } else {
0501         /* l1off, latency: 300us */
0502         if (aspm_L1_2)
0503             val = option->ltr_l1off_sspwrgate;
0504     }
0505
0506     rtsx_set_l1off_sub(pcr, val);
0507 }
0508
0509 /* rts522a operations mainly derived from rts5227, except phy/hw init setting.
0510  */
0511 static const struct pcr_ops rts522a_pcr_ops = {
0512     .fetch_vendor_settings = rts5227_fetch_vendor_settings,
0513     .extra_init_hw = rts522a_extra_init_hw,
0514     .optimize_phy = rts522a_optimize_phy,
0515     .turn_on_led = rts5227_turn_on_led,
0516     .turn_off_led = rts5227_turn_off_led,
0517     .enable_auto_blink = rts5227_enable_auto_blink,
0518     .disable_auto_blink = rts5227_disable_auto_blink,
0519     .card_power_on = rts5227_card_power_on,
0520     .card_power_off = rts5227_card_power_off,
0521     .switch_output_voltage = rts522a_switch_output_voltage,
0522     .force_power_down = rts522a_force_power_down,
0523     .cd_deglitch = NULL,
0524     .conv_clk_and_div_n = NULL,
0525     .set_l1off_cfg_sub_d0 = rts522a_set_l1off_cfg_sub_d0,
0526 };
0527
0528 void rts522a_init_params(struct rtsx_pcr *pcr)
0529 {
0530     struct rtsx_cr_option *option = &pcr->option;
0531
0532     rts5227_init_params(pcr);
0533     pcr->ops = &rts522a_pcr_ops;
0534     pcr->aspm_mode = ASPM_MODE_REG;
0535     pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 20, 11);
0536     pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3;
0537
0538     option->dev_flags = LTR_L1SS_PWR_GATE_EN;
0539     option->ltr_en = true;
0540
0541     /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
0542     option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
0543     option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
0544     option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
0545     option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
0546     option->ltr_l1off_sspwrgate = 0x7F;
0547     option->ltr_l1off_snooze_sspwrgate = 0x78;
0548
0549     pcr->option.ocp_en = 1;
0550     if (pcr->option.ocp_en)
0551         pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
0552     pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
0553     pcr->option.sd_800mA_ocp_thd = RTS522A_OCP_THD_800;
0554
0555 }