misc/cardreader/alcor_pci.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright (C) 2018 Oleksij Rempel <linux@rempel-privat.de>
0004  *
0005  * Driver for Alcor Micro AU6601 and AU6621 controllers
0006  */
0007
0008 #include <linux/delay.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/io.h>
0011 #include <linux/irq.h>
0012 #include <linux/mfd/core.h>
0013 #include <linux/module.h>
0014 #include <linux/pci.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/pm.h>
0017
0018 #include <linux/alcor_pci.h>
0019
0020 #define DRV_NAME_ALCOR_PCI          "alcor_pci"
0021
0022 static DEFINE_IDA(alcor_pci_idr);
0023
0024 static struct mfd_cell alcor_pci_cells[] = {
0025     [ALCOR_SD_CARD] = {
0026         .name = DRV_NAME_ALCOR_PCI_SDMMC,
0027     },
0028     [ALCOR_MS_CARD] = {
0029         .name = DRV_NAME_ALCOR_PCI_MS,
0030     },
0031 };
0032
0033 static const struct alcor_dev_cfg alcor_cfg = {
0034     .dma = 0,
0035 };
0036
0037 static const struct alcor_dev_cfg au6621_cfg = {
0038     .dma = 1,
0039 };
0040
0041 static const struct alcor_dev_cfg au6625_cfg = {
0042     .dma = 0,
0043 };
0044
0045 static const struct pci_device_id pci_ids[] = {
0046     { PCI_DEVICE(PCI_ID_ALCOR_MICRO, PCI_ID_AU6601),
0047         .driver_data = (kernel_ulong_t)&alcor_cfg },
0048     { PCI_DEVICE(PCI_ID_ALCOR_MICRO, PCI_ID_AU6621),
0049         .driver_data = (kernel_ulong_t)&au6621_cfg },
0050     { PCI_DEVICE(PCI_ID_ALCOR_MICRO, PCI_ID_AU6625),
0051         .driver_data = (kernel_ulong_t)&au6625_cfg },
0052     {},
0053 };
0054 MODULE_DEVICE_TABLE(pci, pci_ids);
0055
0056 void alcor_write8(struct alcor_pci_priv *priv, u8 val, unsigned int addr)
0057 {
0058     writeb(val, priv->iobase + addr);
0059 }
0060 EXPORT_SYMBOL_GPL(alcor_write8);
0061
0062 void alcor_write16(struct alcor_pci_priv *priv, u16 val, unsigned int addr)
0063 {
0064     writew(val, priv->iobase + addr);
0065 }
0066 EXPORT_SYMBOL_GPL(alcor_write16);
0067
0068 void alcor_write32(struct alcor_pci_priv *priv, u32 val, unsigned int addr)
0069 {
0070     writel(val, priv->iobase + addr);
0071 }
0072 EXPORT_SYMBOL_GPL(alcor_write32);
0073
0074 void alcor_write32be(struct alcor_pci_priv *priv, u32 val, unsigned int addr)
0075 {
0076     iowrite32be(val, priv->iobase + addr);
0077 }
0078 EXPORT_SYMBOL_GPL(alcor_write32be);
0079
0080 u8 alcor_read8(struct alcor_pci_priv *priv, unsigned int addr)
0081 {
0082     return readb(priv->iobase + addr);
0083 }
0084 EXPORT_SYMBOL_GPL(alcor_read8);
0085
0086 u32 alcor_read32(struct alcor_pci_priv *priv, unsigned int addr)
0087 {
0088     return readl(priv->iobase + addr);
0089 }
0090 EXPORT_SYMBOL_GPL(alcor_read32);
0091
0092 u32 alcor_read32be(struct alcor_pci_priv *priv, unsigned int addr)
0093 {
0094     return ioread32be(priv->iobase + addr);
0095 }
0096 EXPORT_SYMBOL_GPL(alcor_read32be);
0097
0098 static int alcor_pci_find_cap_offset(struct alcor_pci_priv *priv,
0099                      struct pci_dev *pci)
0100 {
0101     int where;
0102     u8 val8;
0103     u32 val32;
0104
0105     where = ALCOR_CAP_START_OFFSET;
0106     pci_read_config_byte(pci, where, &val8);
0107     if (!val8)
0108         return 0;
0109
0110     where = (int)val8;
0111     while (1) {
0112         pci_read_config_dword(pci, where, &val32);
0113         if (val32 == 0xffffffff) {
0114             dev_dbg(priv->dev, "find_cap_offset invalid value %x.\n",
0115                 val32);
0116             return 0;
0117         }
0118
0119         if ((val32 & 0xff) == 0x10) {
0120             dev_dbg(priv->dev, "pcie cap offset: %x\n", where);
0121             return where;
0122         }
0123
0124         if ((val32 & 0xff00) == 0x00) {
0125             dev_dbg(priv->dev, "pci_find_cap_offset invalid value %x.\n",
0126                 val32);
0127             break;
0128         }
0129         where = (int)((val32 >> 8) & 0xff);
0130     }
0131
0132     return 0;
0133 }
0134
0135 static void alcor_pci_init_check_aspm(struct alcor_pci_priv *priv)
0136 {
0137     struct pci_dev *pci;
0138     int where;
0139     u32 val32;
0140
0141     priv->pdev_cap_off    = alcor_pci_find_cap_offset(priv, priv->pdev);
0142     /*
0143      * A device might be attached to root complex directly and
0144      * priv->parent_pdev will be NULL. In this case we don't check its
0145      * capability and disable ASPM completely.
0146      */
0147     if (priv->parent_pdev)
0148         priv->parent_cap_off = alcor_pci_find_cap_offset(priv,
0149                              priv->parent_pdev);
0150
0151     if ((priv->pdev_cap_off == 0) || (priv->parent_cap_off == 0)) {
0152         dev_dbg(priv->dev, "pci_cap_off: %x, parent_cap_off: %x\n",
0153             priv->pdev_cap_off, priv->parent_cap_off);
0154         return;
0155     }
0156
0157     /* link capability */
0158     pci   = priv->pdev;
0159     where = priv->pdev_cap_off + ALCOR_PCIE_LINK_CAP_OFFSET;
0160     pci_read_config_dword(pci, where, &val32);
0161     priv->pdev_aspm_cap = (u8)(val32 >> 10) & 0x03;
0162
0163     pci   = priv->parent_pdev;
0164     where = priv->parent_cap_off + ALCOR_PCIE_LINK_CAP_OFFSET;
0165     pci_read_config_dword(pci, where, &val32);
0166     priv->parent_aspm_cap = (u8)(val32 >> 10) & 0x03;
0167
0168     if (priv->pdev_aspm_cap != priv->parent_aspm_cap) {
0169         u8 aspm_cap;
0170
0171         dev_dbg(priv->dev, "pdev_aspm_cap: %x, parent_aspm_cap: %x\n",
0172             priv->pdev_aspm_cap, priv->parent_aspm_cap);
0173         aspm_cap = priv->pdev_aspm_cap & priv->parent_aspm_cap;
0174         priv->pdev_aspm_cap    = aspm_cap;
0175         priv->parent_aspm_cap = aspm_cap;
0176     }
0177
0178     dev_dbg(priv->dev, "ext_config_dev_aspm: %x, pdev_aspm_cap: %x\n",
0179         priv->ext_config_dev_aspm, priv->pdev_aspm_cap);
0180     priv->ext_config_dev_aspm &= priv->pdev_aspm_cap;
0181 }
0182
0183 static void alcor_pci_aspm_ctrl(struct alcor_pci_priv *priv, u8 aspm_enable)
0184 {
0185     struct pci_dev *pci;
0186     u8 aspm_ctrl, i;
0187     int where;
0188     u32 val32;
0189
0190     if ((!priv->pdev_cap_off) || (!priv->parent_cap_off)) {
0191         dev_dbg(priv->dev, "pci_cap_off: %x, parent_cap_off: %x\n",
0192             priv->pdev_cap_off, priv->parent_cap_off);
0193         return;
0194     }
0195
0196     if (!priv->pdev_aspm_cap)
0197         return;
0198
0199     aspm_ctrl = 0;
0200     if (aspm_enable) {
0201         aspm_ctrl = priv->ext_config_dev_aspm;
0202
0203         if (!aspm_ctrl) {
0204             dev_dbg(priv->dev, "aspm_ctrl == 0\n");
0205             return;
0206         }
0207     }
0208
0209     for (i = 0; i < 2; i++) {
0210
0211         if (i) {
0212             pci   = priv->parent_pdev;
0213             where = priv->parent_cap_off
0214                 + ALCOR_PCIE_LINK_CTRL_OFFSET;
0215         } else {
0216             pci   = priv->pdev;
0217             where = priv->pdev_cap_off
0218                 + ALCOR_PCIE_LINK_CTRL_OFFSET;
0219         }
0220
0221         pci_read_config_dword(pci, where, &val32);
0222         val32 &= (~0x03);
0223         val32 |= (aspm_ctrl & priv->pdev_aspm_cap);
0224         pci_write_config_byte(pci, where, (u8)val32);
0225     }
0226
0227 }
0228
0229 static inline void alcor_mask_sd_irqs(struct alcor_pci_priv *priv)
0230 {
0231     alcor_write32(priv, 0, AU6601_REG_INT_ENABLE);
0232 }
0233
0234 static inline void alcor_unmask_sd_irqs(struct alcor_pci_priv *priv)
0235 {
0236     alcor_write32(priv, AU6601_INT_CMD_MASK | AU6601_INT_DATA_MASK |
0237           AU6601_INT_CARD_INSERT | AU6601_INT_CARD_REMOVE |
0238           AU6601_INT_OVER_CURRENT_ERR,
0239           AU6601_REG_INT_ENABLE);
0240 }
0241
0242 static inline void alcor_mask_ms_irqs(struct alcor_pci_priv *priv)
0243 {
0244     alcor_write32(priv, 0, AU6601_MS_INT_ENABLE);
0245 }
0246
0247 static inline void alcor_unmask_ms_irqs(struct alcor_pci_priv *priv)
0248 {
0249     alcor_write32(priv, 0x3d00fa, AU6601_MS_INT_ENABLE);
0250 }
0251
0252 static int alcor_pci_probe(struct pci_dev *pdev,
0253                const struct pci_device_id *ent)
0254 {
0255     struct alcor_dev_cfg *cfg;
0256     struct alcor_pci_priv *priv;
0257     int ret, i, bar = 0;
0258
0259     cfg = (void *)ent->driver_data;
0260
0261     ret = pcim_enable_device(pdev);
0262     if (ret)
0263         return ret;
0264
0265     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
0266     if (!priv)
0267         return -ENOMEM;
0268
0269     ret = ida_alloc(&alcor_pci_idr, GFP_KERNEL);
0270     if (ret < 0)
0271         return ret;
0272     priv->id = ret;
0273
0274     priv->pdev = pdev;
0275     priv->parent_pdev = pdev->bus->self;
0276     priv->dev = &pdev->dev;
0277     priv->cfg = cfg;
0278     priv->irq = pdev->irq;
0279
0280     ret = pci_request_regions(pdev, DRV_NAME_ALCOR_PCI);
0281     if (ret) {
0282         dev_err(&pdev->dev, "Cannot request region\n");
0283         ret = -ENOMEM;
0284         goto error_free_ida;
0285     }
0286
0287     if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
0288         dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
0289         ret = -ENODEV;
0290         goto error_release_regions;
0291     }
0292
0293     priv->iobase = pcim_iomap(pdev, bar, 0);
0294     if (!priv->iobase) {
0295         ret = -ENOMEM;
0296         goto error_release_regions;
0297     }
0298
0299     /* make sure irqs are disabled */
0300     alcor_write32(priv, 0, AU6601_REG_INT_ENABLE);
0301     alcor_write32(priv, 0, AU6601_MS_INT_ENABLE);
0302
0303     ret = dma_set_mask_and_coherent(priv->dev, AU6601_SDMA_MASK);
0304     if (ret) {
0305         dev_err(priv->dev, "Failed to set DMA mask\n");
0306         goto error_release_regions;
0307     }
0308
0309     pci_set_master(pdev);
0310     pci_set_drvdata(pdev, priv);
0311     alcor_pci_init_check_aspm(priv);
0312
0313     for (i = 0; i < ARRAY_SIZE(alcor_pci_cells); i++) {
0314         alcor_pci_cells[i].platform_data = priv;
0315         alcor_pci_cells[i].pdata_size = sizeof(*priv);
0316     }
0317     ret = mfd_add_devices(&pdev->dev, priv->id, alcor_pci_cells,
0318             ARRAY_SIZE(alcor_pci_cells), NULL, 0, NULL);
0319     if (ret < 0)
0320         goto error_clear_drvdata;
0321
0322     alcor_pci_aspm_ctrl(priv, 0);
0323
0324     return 0;
0325
0326 error_clear_drvdata:
0327     pci_clear_master(pdev);
0328     pci_set_drvdata(pdev, NULL);
0329 error_release_regions:
0330     pci_release_regions(pdev);
0331 error_free_ida:
0332     ida_free(&alcor_pci_idr, priv->id);
0333     return ret;
0334 }
0335
0336 static void alcor_pci_remove(struct pci_dev *pdev)
0337 {
0338     struct alcor_pci_priv *priv;
0339
0340     priv = pci_get_drvdata(pdev);
0341
0342     alcor_pci_aspm_ctrl(priv, 1);
0343
0344     mfd_remove_devices(&pdev->dev);
0345
0346     ida_free(&alcor_pci_idr, priv->id);
0347
0348     pci_release_regions(pdev);
0349     pci_clear_master(pdev);
0350     pci_set_drvdata(pdev, NULL);
0351 }
0352
0353 #ifdef CONFIG_PM_SLEEP
0354 static int alcor_suspend(struct device *dev)
0355 {
0356     struct alcor_pci_priv *priv = dev_get_drvdata(dev);
0357
0358     alcor_pci_aspm_ctrl(priv, 1);
0359     return 0;
0360 }
0361
0362 static int alcor_resume(struct device *dev)
0363 {
0364
0365     struct alcor_pci_priv *priv = dev_get_drvdata(dev);
0366
0367     alcor_pci_aspm_ctrl(priv, 0);
0368     return 0;
0369 }
0370 #endif /* CONFIG_PM_SLEEP */
0371
0372 static SIMPLE_DEV_PM_OPS(alcor_pci_pm_ops, alcor_suspend, alcor_resume);
0373
0374 static struct pci_driver alcor_driver = {
0375     .name   =   DRV_NAME_ALCOR_PCI,
0376     .id_table = pci_ids,
0377     .probe  =   alcor_pci_probe,
0378     .remove =   alcor_pci_remove,
0379     .driver =   {
0380         .pm = &alcor_pci_pm_ops
0381     },
0382 };
0383
0384 module_pci_driver(alcor_driver);
0385
0386 MODULE_AUTHOR("Oleksij Rempel <linux@rempel-privat.de>");
0387 MODULE_DESCRIPTION("PCI driver for Alcor Micro AU6601 Secure Digital Host Controller Interface");
0388 MODULE_LICENSE("GPL");