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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * wm831x-irq.c  --  Interrupt controller support for Wolfson WM831x PMICs
0004  *
0005  * Copyright 2009 Wolfson Microelectronics PLC.
0006  *
0007  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
0008  */
0009 
0010 #include <linux/kernel.h>
0011 #include <linux/module.h>
0012 #include <linux/i2c.h>
0013 #include <linux/irq.h>
0014 #include <linux/mfd/core.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/irqdomain.h>
0017 
0018 #include <linux/mfd/wm831x/core.h>
0019 #include <linux/mfd/wm831x/pdata.h>
0020 #include <linux/mfd/wm831x/gpio.h>
0021 #include <linux/mfd/wm831x/irq.h>
0022 
0023 #include <linux/delay.h>
0024 
0025 struct wm831x_irq_data {
0026     int primary;
0027     int reg;
0028     int mask;
0029 };
0030 
0031 static struct wm831x_irq_data wm831x_irqs[] = {
0032     [WM831X_IRQ_TEMP_THW] = {
0033         .primary = WM831X_TEMP_INT,
0034         .reg = 1,
0035         .mask = WM831X_TEMP_THW_EINT,
0036     },
0037     [WM831X_IRQ_GPIO_1] = {
0038         .primary = WM831X_GP_INT,
0039         .reg = 5,
0040         .mask = WM831X_GP1_EINT,
0041     },
0042     [WM831X_IRQ_GPIO_2] = {
0043         .primary = WM831X_GP_INT,
0044         .reg = 5,
0045         .mask = WM831X_GP2_EINT,
0046     },
0047     [WM831X_IRQ_GPIO_3] = {
0048         .primary = WM831X_GP_INT,
0049         .reg = 5,
0050         .mask = WM831X_GP3_EINT,
0051     },
0052     [WM831X_IRQ_GPIO_4] = {
0053         .primary = WM831X_GP_INT,
0054         .reg = 5,
0055         .mask = WM831X_GP4_EINT,
0056     },
0057     [WM831X_IRQ_GPIO_5] = {
0058         .primary = WM831X_GP_INT,
0059         .reg = 5,
0060         .mask = WM831X_GP5_EINT,
0061     },
0062     [WM831X_IRQ_GPIO_6] = {
0063         .primary = WM831X_GP_INT,
0064         .reg = 5,
0065         .mask = WM831X_GP6_EINT,
0066     },
0067     [WM831X_IRQ_GPIO_7] = {
0068         .primary = WM831X_GP_INT,
0069         .reg = 5,
0070         .mask = WM831X_GP7_EINT,
0071     },
0072     [WM831X_IRQ_GPIO_8] = {
0073         .primary = WM831X_GP_INT,
0074         .reg = 5,
0075         .mask = WM831X_GP8_EINT,
0076     },
0077     [WM831X_IRQ_GPIO_9] = {
0078         .primary = WM831X_GP_INT,
0079         .reg = 5,
0080         .mask = WM831X_GP9_EINT,
0081     },
0082     [WM831X_IRQ_GPIO_10] = {
0083         .primary = WM831X_GP_INT,
0084         .reg = 5,
0085         .mask = WM831X_GP10_EINT,
0086     },
0087     [WM831X_IRQ_GPIO_11] = {
0088         .primary = WM831X_GP_INT,
0089         .reg = 5,
0090         .mask = WM831X_GP11_EINT,
0091     },
0092     [WM831X_IRQ_GPIO_12] = {
0093         .primary = WM831X_GP_INT,
0094         .reg = 5,
0095         .mask = WM831X_GP12_EINT,
0096     },
0097     [WM831X_IRQ_GPIO_13] = {
0098         .primary = WM831X_GP_INT,
0099         .reg = 5,
0100         .mask = WM831X_GP13_EINT,
0101     },
0102     [WM831X_IRQ_GPIO_14] = {
0103         .primary = WM831X_GP_INT,
0104         .reg = 5,
0105         .mask = WM831X_GP14_EINT,
0106     },
0107     [WM831X_IRQ_GPIO_15] = {
0108         .primary = WM831X_GP_INT,
0109         .reg = 5,
0110         .mask = WM831X_GP15_EINT,
0111     },
0112     [WM831X_IRQ_GPIO_16] = {
0113         .primary = WM831X_GP_INT,
0114         .reg = 5,
0115         .mask = WM831X_GP16_EINT,
0116     },
0117     [WM831X_IRQ_ON] = {
0118         .primary = WM831X_ON_PIN_INT,
0119         .reg = 1,
0120         .mask = WM831X_ON_PIN_EINT,
0121     },
0122     [WM831X_IRQ_PPM_SYSLO] = {
0123         .primary = WM831X_PPM_INT,
0124         .reg = 1,
0125         .mask = WM831X_PPM_SYSLO_EINT,
0126     },
0127     [WM831X_IRQ_PPM_PWR_SRC] = {
0128         .primary = WM831X_PPM_INT,
0129         .reg = 1,
0130         .mask = WM831X_PPM_PWR_SRC_EINT,
0131     },
0132     [WM831X_IRQ_PPM_USB_CURR] = {
0133         .primary = WM831X_PPM_INT,
0134         .reg = 1,
0135         .mask = WM831X_PPM_USB_CURR_EINT,
0136     },
0137     [WM831X_IRQ_WDOG_TO] = {
0138         .primary = WM831X_WDOG_INT,
0139         .reg = 1,
0140         .mask = WM831X_WDOG_TO_EINT,
0141     },
0142     [WM831X_IRQ_RTC_PER] = {
0143         .primary = WM831X_RTC_INT,
0144         .reg = 1,
0145         .mask = WM831X_RTC_PER_EINT,
0146     },
0147     [WM831X_IRQ_RTC_ALM] = {
0148         .primary = WM831X_RTC_INT,
0149         .reg = 1,
0150         .mask = WM831X_RTC_ALM_EINT,
0151     },
0152     [WM831X_IRQ_CHG_BATT_HOT] = {
0153         .primary = WM831X_CHG_INT,
0154         .reg = 2,
0155         .mask = WM831X_CHG_BATT_HOT_EINT,
0156     },
0157     [WM831X_IRQ_CHG_BATT_COLD] = {
0158         .primary = WM831X_CHG_INT,
0159         .reg = 2,
0160         .mask = WM831X_CHG_BATT_COLD_EINT,
0161     },
0162     [WM831X_IRQ_CHG_BATT_FAIL] = {
0163         .primary = WM831X_CHG_INT,
0164         .reg = 2,
0165         .mask = WM831X_CHG_BATT_FAIL_EINT,
0166     },
0167     [WM831X_IRQ_CHG_OV] = {
0168         .primary = WM831X_CHG_INT,
0169         .reg = 2,
0170         .mask = WM831X_CHG_OV_EINT,
0171     },
0172     [WM831X_IRQ_CHG_END] = {
0173         .primary = WM831X_CHG_INT,
0174         .reg = 2,
0175         .mask = WM831X_CHG_END_EINT,
0176     },
0177     [WM831X_IRQ_CHG_TO] = {
0178         .primary = WM831X_CHG_INT,
0179         .reg = 2,
0180         .mask = WM831X_CHG_TO_EINT,
0181     },
0182     [WM831X_IRQ_CHG_MODE] = {
0183         .primary = WM831X_CHG_INT,
0184         .reg = 2,
0185         .mask = WM831X_CHG_MODE_EINT,
0186     },
0187     [WM831X_IRQ_CHG_START] = {
0188         .primary = WM831X_CHG_INT,
0189         .reg = 2,
0190         .mask = WM831X_CHG_START_EINT,
0191     },
0192     [WM831X_IRQ_TCHDATA] = {
0193         .primary = WM831X_TCHDATA_INT,
0194         .reg = 1,
0195         .mask = WM831X_TCHDATA_EINT,
0196     },
0197     [WM831X_IRQ_TCHPD] = {
0198         .primary = WM831X_TCHPD_INT,
0199         .reg = 1,
0200         .mask = WM831X_TCHPD_EINT,
0201     },
0202     [WM831X_IRQ_AUXADC_DATA] = {
0203         .primary = WM831X_AUXADC_INT,
0204         .reg = 1,
0205         .mask = WM831X_AUXADC_DATA_EINT,
0206     },
0207     [WM831X_IRQ_AUXADC_DCOMP1] = {
0208         .primary = WM831X_AUXADC_INT,
0209         .reg = 1,
0210         .mask = WM831X_AUXADC_DCOMP1_EINT,
0211     },
0212     [WM831X_IRQ_AUXADC_DCOMP2] = {
0213         .primary = WM831X_AUXADC_INT,
0214         .reg = 1,
0215         .mask = WM831X_AUXADC_DCOMP2_EINT,
0216     },
0217     [WM831X_IRQ_AUXADC_DCOMP3] = {
0218         .primary = WM831X_AUXADC_INT,
0219         .reg = 1,
0220         .mask = WM831X_AUXADC_DCOMP3_EINT,
0221     },
0222     [WM831X_IRQ_AUXADC_DCOMP4] = {
0223         .primary = WM831X_AUXADC_INT,
0224         .reg = 1,
0225         .mask = WM831X_AUXADC_DCOMP4_EINT,
0226     },
0227     [WM831X_IRQ_CS1] = {
0228         .primary = WM831X_CS_INT,
0229         .reg = 2,
0230         .mask = WM831X_CS1_EINT,
0231     },
0232     [WM831X_IRQ_CS2] = {
0233         .primary = WM831X_CS_INT,
0234         .reg = 2,
0235         .mask = WM831X_CS2_EINT,
0236     },
0237     [WM831X_IRQ_HC_DC1] = {
0238         .primary = WM831X_HC_INT,
0239         .reg = 4,
0240         .mask = WM831X_HC_DC1_EINT,
0241     },
0242     [WM831X_IRQ_HC_DC2] = {
0243         .primary = WM831X_HC_INT,
0244         .reg = 4,
0245         .mask = WM831X_HC_DC2_EINT,
0246     },
0247     [WM831X_IRQ_UV_LDO1] = {
0248         .primary = WM831X_UV_INT,
0249         .reg = 3,
0250         .mask = WM831X_UV_LDO1_EINT,
0251     },
0252     [WM831X_IRQ_UV_LDO2] = {
0253         .primary = WM831X_UV_INT,
0254         .reg = 3,
0255         .mask = WM831X_UV_LDO2_EINT,
0256     },
0257     [WM831X_IRQ_UV_LDO3] = {
0258         .primary = WM831X_UV_INT,
0259         .reg = 3,
0260         .mask = WM831X_UV_LDO3_EINT,
0261     },
0262     [WM831X_IRQ_UV_LDO4] = {
0263         .primary = WM831X_UV_INT,
0264         .reg = 3,
0265         .mask = WM831X_UV_LDO4_EINT,
0266     },
0267     [WM831X_IRQ_UV_LDO5] = {
0268         .primary = WM831X_UV_INT,
0269         .reg = 3,
0270         .mask = WM831X_UV_LDO5_EINT,
0271     },
0272     [WM831X_IRQ_UV_LDO6] = {
0273         .primary = WM831X_UV_INT,
0274         .reg = 3,
0275         .mask = WM831X_UV_LDO6_EINT,
0276     },
0277     [WM831X_IRQ_UV_LDO7] = {
0278         .primary = WM831X_UV_INT,
0279         .reg = 3,
0280         .mask = WM831X_UV_LDO7_EINT,
0281     },
0282     [WM831X_IRQ_UV_LDO8] = {
0283         .primary = WM831X_UV_INT,
0284         .reg = 3,
0285         .mask = WM831X_UV_LDO8_EINT,
0286     },
0287     [WM831X_IRQ_UV_LDO9] = {
0288         .primary = WM831X_UV_INT,
0289         .reg = 3,
0290         .mask = WM831X_UV_LDO9_EINT,
0291     },
0292     [WM831X_IRQ_UV_LDO10] = {
0293         .primary = WM831X_UV_INT,
0294         .reg = 3,
0295         .mask = WM831X_UV_LDO10_EINT,
0296     },
0297     [WM831X_IRQ_UV_DC1] = {
0298         .primary = WM831X_UV_INT,
0299         .reg = 4,
0300         .mask = WM831X_UV_DC1_EINT,
0301     },
0302     [WM831X_IRQ_UV_DC2] = {
0303         .primary = WM831X_UV_INT,
0304         .reg = 4,
0305         .mask = WM831X_UV_DC2_EINT,
0306     },
0307     [WM831X_IRQ_UV_DC3] = {
0308         .primary = WM831X_UV_INT,
0309         .reg = 4,
0310         .mask = WM831X_UV_DC3_EINT,
0311     },
0312     [WM831X_IRQ_UV_DC4] = {
0313         .primary = WM831X_UV_INT,
0314         .reg = 4,
0315         .mask = WM831X_UV_DC4_EINT,
0316     },
0317 };
0318 
0319 static inline int irq_data_to_status_reg(struct wm831x_irq_data *irq_data)
0320 {
0321     return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg;
0322 }
0323 
0324 static inline struct wm831x_irq_data *irq_to_wm831x_irq(struct wm831x *wm831x,
0325                             int irq)
0326 {
0327     return &wm831x_irqs[irq];
0328 }
0329 
0330 static void wm831x_irq_lock(struct irq_data *data)
0331 {
0332     struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
0333 
0334     mutex_lock(&wm831x->irq_lock);
0335 }
0336 
0337 static void wm831x_irq_sync_unlock(struct irq_data *data)
0338 {
0339     struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
0340     int i;
0341 
0342     for (i = 0; i < ARRAY_SIZE(wm831x->gpio_update); i++) {
0343         if (wm831x->gpio_update[i]) {
0344             wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + i,
0345                     WM831X_GPN_INT_MODE | WM831X_GPN_POL,
0346                     wm831x->gpio_update[i]);
0347             wm831x->gpio_update[i] = 0;
0348         }
0349     }
0350 
0351     for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
0352         /* If there's been a change in the mask write it back
0353          * to the hardware. */
0354         if (wm831x->irq_masks_cur[i] != wm831x->irq_masks_cache[i]) {
0355             dev_dbg(wm831x->dev, "IRQ mask sync: %x = %x\n",
0356                 WM831X_INTERRUPT_STATUS_1_MASK + i,
0357                 wm831x->irq_masks_cur[i]);
0358 
0359             wm831x->irq_masks_cache[i] = wm831x->irq_masks_cur[i];
0360             wm831x_reg_write(wm831x,
0361                      WM831X_INTERRUPT_STATUS_1_MASK + i,
0362                      wm831x->irq_masks_cur[i]);
0363         }
0364     }
0365 
0366     mutex_unlock(&wm831x->irq_lock);
0367 }
0368 
0369 static void wm831x_irq_enable(struct irq_data *data)
0370 {
0371     struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
0372     struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
0373                                  data->hwirq);
0374 
0375     wm831x->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
0376 }
0377 
0378 static void wm831x_irq_disable(struct irq_data *data)
0379 {
0380     struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
0381     struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
0382                                  data->hwirq);
0383 
0384     wm831x->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
0385 }
0386 
0387 static int wm831x_irq_set_type(struct irq_data *data, unsigned int type)
0388 {
0389     struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
0390     int irq;
0391 
0392     irq = data->hwirq;
0393 
0394     if (irq < WM831X_IRQ_GPIO_1 || irq > WM831X_IRQ_GPIO_11) {
0395         /* Ignore internal-only IRQs */
0396         if (irq >= 0 && irq < WM831X_NUM_IRQS)
0397             return 0;
0398         else
0399             return -EINVAL;
0400     }
0401 
0402     /* Rebase the IRQ into the GPIO range so we've got a sensible array
0403      * index.
0404      */
0405     irq -= WM831X_IRQ_GPIO_1;
0406 
0407     /* We set the high bit to flag that we need an update; don't
0408      * do the update here as we can be called with the bus lock
0409      * held.
0410      */
0411     wm831x->gpio_level_low[irq] = false;
0412     wm831x->gpio_level_high[irq] = false;
0413     switch (type) {
0414     case IRQ_TYPE_EDGE_BOTH:
0415         wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_INT_MODE;
0416         break;
0417     case IRQ_TYPE_EDGE_RISING:
0418         wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_POL;
0419         break;
0420     case IRQ_TYPE_EDGE_FALLING:
0421         wm831x->gpio_update[irq] = 0x10000;
0422         break;
0423     case IRQ_TYPE_LEVEL_HIGH:
0424         wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_POL;
0425         wm831x->gpio_level_high[irq] = true;
0426         break;
0427     case IRQ_TYPE_LEVEL_LOW:
0428         wm831x->gpio_update[irq] = 0x10000;
0429         wm831x->gpio_level_low[irq] = true;
0430         break;
0431     default:
0432         return -EINVAL;
0433     }
0434 
0435     return 0;
0436 }
0437 
0438 static struct irq_chip wm831x_irq_chip = {
0439     .name           = "wm831x",
0440     .irq_bus_lock       = wm831x_irq_lock,
0441     .irq_bus_sync_unlock    = wm831x_irq_sync_unlock,
0442     .irq_disable        = wm831x_irq_disable,
0443     .irq_enable     = wm831x_irq_enable,
0444     .irq_set_type       = wm831x_irq_set_type,
0445 };
0446 
0447 /* The processing of the primary interrupt occurs in a thread so that
0448  * we can interact with the device over I2C or SPI. */
0449 static irqreturn_t wm831x_irq_thread(int irq, void *data)
0450 {
0451     struct wm831x *wm831x = data;
0452     unsigned int i;
0453     int primary, status_addr, ret;
0454     int status_regs[WM831X_NUM_IRQ_REGS] = { 0 };
0455     int read[WM831X_NUM_IRQ_REGS] = { 0 };
0456     int *status;
0457 
0458     primary = wm831x_reg_read(wm831x, WM831X_SYSTEM_INTERRUPTS);
0459     if (primary < 0) {
0460         dev_err(wm831x->dev, "Failed to read system interrupt: %d\n",
0461             primary);
0462         goto out;
0463     }
0464 
0465     /* The touch interrupts are visible in the primary register as
0466      * an optimisation; open code this to avoid complicating the
0467      * main handling loop and so we can also skip iterating the
0468      * descriptors.
0469      */
0470     if (primary & WM831X_TCHPD_INT)
0471         handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
0472                            WM831X_IRQ_TCHPD));
0473     if (primary & WM831X_TCHDATA_INT)
0474         handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
0475                            WM831X_IRQ_TCHDATA));
0476     primary &= ~(WM831X_TCHDATA_EINT | WM831X_TCHPD_EINT);
0477 
0478     for (i = 0; i < ARRAY_SIZE(wm831x_irqs); i++) {
0479         int offset = wm831x_irqs[i].reg - 1;
0480 
0481         if (!(primary & wm831x_irqs[i].primary))
0482             continue;
0483 
0484         status = &status_regs[offset];
0485 
0486         /* Hopefully there should only be one register to read
0487          * each time otherwise we ought to do a block read. */
0488         if (!read[offset]) {
0489             status_addr = irq_data_to_status_reg(&wm831x_irqs[i]);
0490 
0491             *status = wm831x_reg_read(wm831x, status_addr);
0492             if (*status < 0) {
0493                 dev_err(wm831x->dev,
0494                     "Failed to read IRQ status: %d\n",
0495                     *status);
0496                 goto out;
0497             }
0498 
0499             read[offset] = 1;
0500 
0501             /* Ignore any bits that we don't think are masked */
0502             *status &= ~wm831x->irq_masks_cur[offset];
0503 
0504             /* Acknowledge now so we don't miss
0505              * notifications while we handle.
0506              */
0507             wm831x_reg_write(wm831x, status_addr, *status);
0508         }
0509 
0510         if (*status & wm831x_irqs[i].mask)
0511             handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
0512                                i));
0513 
0514         /* Simulate an edge triggered IRQ by polling the input
0515          * status.  This is sucky but improves interoperability.
0516          */
0517         if (primary == WM831X_GP_INT &&
0518             wm831x->gpio_level_high[i - WM831X_IRQ_GPIO_1]) {
0519             ret = wm831x_reg_read(wm831x, WM831X_GPIO_LEVEL);
0520             while (ret & 1 << (i - WM831X_IRQ_GPIO_1)) {
0521                 handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
0522                                    i));
0523                 ret = wm831x_reg_read(wm831x,
0524                               WM831X_GPIO_LEVEL);
0525             }
0526         }
0527 
0528         if (primary == WM831X_GP_INT &&
0529             wm831x->gpio_level_low[i - WM831X_IRQ_GPIO_1]) {
0530             ret = wm831x_reg_read(wm831x, WM831X_GPIO_LEVEL);
0531             while (!(ret & 1 << (i - WM831X_IRQ_GPIO_1))) {
0532                 handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
0533                                    i));
0534                 ret = wm831x_reg_read(wm831x,
0535                               WM831X_GPIO_LEVEL);
0536             }
0537         }
0538     }
0539 
0540 out:
0541     return IRQ_HANDLED;
0542 }
0543 
0544 static int wm831x_irq_map(struct irq_domain *h, unsigned int virq,
0545               irq_hw_number_t hw)
0546 {
0547     irq_set_chip_data(virq, h->host_data);
0548     irq_set_chip_and_handler(virq, &wm831x_irq_chip, handle_edge_irq);
0549     irq_set_nested_thread(virq, 1);
0550     irq_set_noprobe(virq);
0551 
0552     return 0;
0553 }
0554 
0555 static const struct irq_domain_ops wm831x_irq_domain_ops = {
0556     .map    = wm831x_irq_map,
0557     .xlate  = irq_domain_xlate_twocell,
0558 };
0559 
0560 int wm831x_irq_init(struct wm831x *wm831x, int irq)
0561 {
0562     struct wm831x_pdata *pdata = &wm831x->pdata;
0563     struct irq_domain *domain;
0564     int i, ret, irq_base;
0565 
0566     mutex_init(&wm831x->irq_lock);
0567 
0568     /* Mask the individual interrupt sources */
0569     for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
0570         wm831x->irq_masks_cur[i] = 0xffff;
0571         wm831x->irq_masks_cache[i] = 0xffff;
0572         wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i,
0573                  0xffff);
0574     }
0575 
0576     /* Try to dynamically allocate IRQs if no base is specified */
0577     if (pdata->irq_base) {
0578         irq_base = irq_alloc_descs(pdata->irq_base, 0,
0579                        WM831X_NUM_IRQS, 0);
0580         if (irq_base < 0) {
0581             dev_warn(wm831x->dev, "Failed to allocate IRQs: %d\n",
0582                  irq_base);
0583             irq_base = 0;
0584         }
0585     } else {
0586         irq_base = 0;
0587     }
0588 
0589     if (irq_base)
0590         domain = irq_domain_add_legacy(wm831x->dev->of_node,
0591                            ARRAY_SIZE(wm831x_irqs),
0592                            irq_base, 0,
0593                            &wm831x_irq_domain_ops,
0594                            wm831x);
0595     else
0596         domain = irq_domain_add_linear(wm831x->dev->of_node,
0597                            ARRAY_SIZE(wm831x_irqs),
0598                            &wm831x_irq_domain_ops,
0599                            wm831x);
0600 
0601     if (!domain) {
0602         dev_warn(wm831x->dev, "Failed to allocate IRQ domain\n");
0603         return -EINVAL;
0604     }
0605 
0606     if (pdata->irq_cmos)
0607         i = 0;
0608     else
0609         i = WM831X_IRQ_OD;
0610 
0611     wm831x_set_bits(wm831x, WM831X_IRQ_CONFIG,
0612             WM831X_IRQ_OD, i);
0613 
0614     wm831x->irq = irq;
0615     wm831x->irq_domain = domain;
0616 
0617     if (irq) {
0618         /* Try to flag /IRQ as a wake source; there are a number of
0619          * unconditional wake sources in the PMIC so this isn't
0620          * conditional but we don't actually care *too* much if it
0621          * fails.
0622          */
0623         ret = enable_irq_wake(irq);
0624         if (ret != 0) {
0625             dev_warn(wm831x->dev,
0626                  "Can't enable IRQ as wake source: %d\n",
0627                  ret);
0628         }
0629 
0630         ret = request_threaded_irq(irq, NULL, wm831x_irq_thread,
0631                        IRQF_TRIGGER_LOW | IRQF_ONESHOT,
0632                        "wm831x", wm831x);
0633         if (ret != 0) {
0634             dev_err(wm831x->dev, "Failed to request IRQ %d: %d\n",
0635                 irq, ret);
0636             return ret;
0637         }
0638     } else {
0639         dev_warn(wm831x->dev,
0640              "No interrupt specified - functionality limited\n");
0641     }
0642 
0643     /* Enable top level interrupts, we mask at secondary level */
0644     wm831x_reg_write(wm831x, WM831X_SYSTEM_INTERRUPTS_MASK, 0);
0645 
0646     return 0;
0647 }
0648 
0649 void wm831x_irq_exit(struct wm831x *wm831x)
0650 {
0651     if (wm831x->irq)
0652         free_irq(wm831x->irq, wm831x);
0653 }
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