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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  linux/drivers/mfd/ucb1x00-core.c
0004  *
0005  *  Copyright (C) 2001 Russell King, All Rights Reserved.
0006  *
0007  *  The UCB1x00 core driver provides basic services for handling IO,
0008  *  the ADC, interrupts, and accessing registers.  It is designed
0009  *  such that everything goes through this layer, thereby providing
0010  *  a consistent locking methodology, as well as allowing the drivers
0011  *  to be used on other non-MCP-enabled hardware platforms.
0012  *
0013  *  Note that all locks are private to this file.  Nothing else may
0014  *  touch them.
0015  */
0016 #include <linux/module.h>
0017 #include <linux/kernel.h>
0018 #include <linux/sched.h>
0019 #include <linux/slab.h>
0020 #include <linux/init.h>
0021 #include <linux/errno.h>
0022 #include <linux/interrupt.h>
0023 #include <linux/irq.h>
0024 #include <linux/device.h>
0025 #include <linux/mutex.h>
0026 #include <linux/mfd/ucb1x00.h>
0027 #include <linux/pm.h>
0028 #include <linux/gpio/driver.h>
0029 
0030 static DEFINE_MUTEX(ucb1x00_mutex);
0031 static LIST_HEAD(ucb1x00_drivers);
0032 static LIST_HEAD(ucb1x00_devices);
0033 
0034 /**
0035  *  ucb1x00_io_set_dir - set IO direction
0036  *  @ucb: UCB1x00 structure describing chip
0037  *  @in:  bitfield of IO pins to be set as inputs
0038  *  @out: bitfield of IO pins to be set as outputs
0039  *
0040  *  Set the IO direction of the ten general purpose IO pins on
0041  *  the UCB1x00 chip.  The @in bitfield has priority over the
0042  *  @out bitfield, in that if you specify a pin as both input
0043  *  and output, it will end up as an input.
0044  *
0045  *  ucb1x00_enable must have been called to enable the comms
0046  *  before using this function.
0047  *
0048  *  This function takes a spinlock, disabling interrupts.
0049  */
0050 void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int in, unsigned int out)
0051 {
0052     unsigned long flags;
0053 
0054     spin_lock_irqsave(&ucb->io_lock, flags);
0055     ucb->io_dir |= out;
0056     ucb->io_dir &= ~in;
0057 
0058     ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
0059     spin_unlock_irqrestore(&ucb->io_lock, flags);
0060 }
0061 
0062 /**
0063  *  ucb1x00_io_write - set or clear IO outputs
0064  *  @ucb:   UCB1x00 structure describing chip
0065  *  @set:   bitfield of IO pins to set to logic '1'
0066  *  @clear: bitfield of IO pins to set to logic '0'
0067  *
0068  *  Set the IO output state of the specified IO pins.  The value
0069  *  is retained if the pins are subsequently configured as inputs.
0070  *  The @clear bitfield has priority over the @set bitfield -
0071  *  outputs will be cleared.
0072  *
0073  *  ucb1x00_enable must have been called to enable the comms
0074  *  before using this function.
0075  *
0076  *  This function takes a spinlock, disabling interrupts.
0077  */
0078 void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int set, unsigned int clear)
0079 {
0080     unsigned long flags;
0081 
0082     spin_lock_irqsave(&ucb->io_lock, flags);
0083     ucb->io_out |= set;
0084     ucb->io_out &= ~clear;
0085 
0086     ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
0087     spin_unlock_irqrestore(&ucb->io_lock, flags);
0088 }
0089 
0090 /**
0091  *  ucb1x00_io_read - read the current state of the IO pins
0092  *  @ucb: UCB1x00 structure describing chip
0093  *
0094  *  Return a bitfield describing the logic state of the ten
0095  *  general purpose IO pins.
0096  *
0097  *  ucb1x00_enable must have been called to enable the comms
0098  *  before using this function.
0099  *
0100  *  This function does not take any mutexes or spinlocks.
0101  */
0102 unsigned int ucb1x00_io_read(struct ucb1x00 *ucb)
0103 {
0104     return ucb1x00_reg_read(ucb, UCB_IO_DATA);
0105 }
0106 
0107 static void ucb1x00_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
0108 {
0109     struct ucb1x00 *ucb = gpiochip_get_data(chip);
0110     unsigned long flags;
0111 
0112     spin_lock_irqsave(&ucb->io_lock, flags);
0113     if (value)
0114         ucb->io_out |= 1 << offset;
0115     else
0116         ucb->io_out &= ~(1 << offset);
0117 
0118     ucb1x00_enable(ucb);
0119     ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
0120     ucb1x00_disable(ucb);
0121     spin_unlock_irqrestore(&ucb->io_lock, flags);
0122 }
0123 
0124 static int ucb1x00_gpio_get(struct gpio_chip *chip, unsigned offset)
0125 {
0126     struct ucb1x00 *ucb = gpiochip_get_data(chip);
0127     unsigned val;
0128 
0129     ucb1x00_enable(ucb);
0130     val = ucb1x00_reg_read(ucb, UCB_IO_DATA);
0131     ucb1x00_disable(ucb);
0132 
0133     return !!(val & (1 << offset));
0134 }
0135 
0136 static int ucb1x00_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
0137 {
0138     struct ucb1x00 *ucb = gpiochip_get_data(chip);
0139     unsigned long flags;
0140 
0141     spin_lock_irqsave(&ucb->io_lock, flags);
0142     ucb->io_dir &= ~(1 << offset);
0143     ucb1x00_enable(ucb);
0144     ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
0145     ucb1x00_disable(ucb);
0146     spin_unlock_irqrestore(&ucb->io_lock, flags);
0147 
0148     return 0;
0149 }
0150 
0151 static int ucb1x00_gpio_direction_output(struct gpio_chip *chip, unsigned offset
0152         , int value)
0153 {
0154     struct ucb1x00 *ucb = gpiochip_get_data(chip);
0155     unsigned long flags;
0156     unsigned old, mask = 1 << offset;
0157 
0158     spin_lock_irqsave(&ucb->io_lock, flags);
0159     old = ucb->io_out;
0160     if (value)
0161         ucb->io_out |= mask;
0162     else
0163         ucb->io_out &= ~mask;
0164 
0165     ucb1x00_enable(ucb);
0166     if (old != ucb->io_out)
0167         ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
0168 
0169     if (!(ucb->io_dir & mask)) {
0170         ucb->io_dir |= mask;
0171         ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
0172     }
0173     ucb1x00_disable(ucb);
0174     spin_unlock_irqrestore(&ucb->io_lock, flags);
0175 
0176     return 0;
0177 }
0178 
0179 static int ucb1x00_to_irq(struct gpio_chip *chip, unsigned offset)
0180 {
0181     struct ucb1x00 *ucb = gpiochip_get_data(chip);
0182 
0183     return ucb->irq_base > 0 ? ucb->irq_base + offset : -ENXIO;
0184 }
0185 
0186 /*
0187  * UCB1300 data sheet says we must:
0188  *  1. enable ADC   => 5us (including reference startup time)
0189  *  2. select input => 51*tsibclk  => 4.3us
0190  *  3. start conversion => 102*tsibclk => 8.5us
0191  * (tsibclk = 1/11981000)
0192  * Period between SIB 128-bit frames = 10.7us
0193  */
0194 
0195 /**
0196  *  ucb1x00_adc_enable - enable the ADC converter
0197  *  @ucb: UCB1x00 structure describing chip
0198  *
0199  *  Enable the ucb1x00 and ADC converter on the UCB1x00 for use.
0200  *  Any code wishing to use the ADC converter must call this
0201  *  function prior to using it.
0202  *
0203  *  This function takes the ADC mutex to prevent two or more
0204  *  concurrent uses, and therefore may sleep.  As a result, it
0205  *  can only be called from process context, not interrupt
0206  *  context.
0207  *
0208  *  You should release the ADC as soon as possible using
0209  *  ucb1x00_adc_disable.
0210  */
0211 void ucb1x00_adc_enable(struct ucb1x00 *ucb)
0212 {
0213     mutex_lock(&ucb->adc_mutex);
0214 
0215     ucb->adc_cr |= UCB_ADC_ENA;
0216 
0217     ucb1x00_enable(ucb);
0218     ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr);
0219 }
0220 
0221 /**
0222  *  ucb1x00_adc_read - read the specified ADC channel
0223  *  @ucb: UCB1x00 structure describing chip
0224  *  @adc_channel: ADC channel mask
0225  *  @sync: wait for syncronisation pulse.
0226  *
0227  *  Start an ADC conversion and wait for the result.  Note that
0228  *  synchronised ADC conversions (via the ADCSYNC pin) must wait
0229  *  until the trigger is asserted and the conversion is finished.
0230  *
0231  *  This function currently spins waiting for the conversion to
0232  *  complete (2 frames max without sync).
0233  *
0234  *  If called for a synchronised ADC conversion, it may sleep
0235  *  with the ADC mutex held.
0236  */
0237 unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync)
0238 {
0239     unsigned int val;
0240 
0241     if (sync)
0242         adc_channel |= UCB_ADC_SYNC_ENA;
0243 
0244     ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel);
0245     ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel | UCB_ADC_START);
0246 
0247     for (;;) {
0248         val = ucb1x00_reg_read(ucb, UCB_ADC_DATA);
0249         if (val & UCB_ADC_DAT_VAL)
0250             break;
0251         /* yield to other processes */
0252         set_current_state(TASK_INTERRUPTIBLE);
0253         schedule_timeout(1);
0254     }
0255 
0256     return UCB_ADC_DAT(val);
0257 }
0258 
0259 /**
0260  *  ucb1x00_adc_disable - disable the ADC converter
0261  *  @ucb: UCB1x00 structure describing chip
0262  *
0263  *  Disable the ADC converter and release the ADC mutex.
0264  */
0265 void ucb1x00_adc_disable(struct ucb1x00 *ucb)
0266 {
0267     ucb->adc_cr &= ~UCB_ADC_ENA;
0268     ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr);
0269     ucb1x00_disable(ucb);
0270 
0271     mutex_unlock(&ucb->adc_mutex);
0272 }
0273 
0274 /*
0275  * UCB1x00 Interrupt handling.
0276  *
0277  * The UCB1x00 can generate interrupts when the SIBCLK is stopped.
0278  * Since we need to read an internal register, we must re-enable
0279  * SIBCLK to talk to the chip.  We leave the clock running until
0280  * we have finished processing all interrupts from the chip.
0281  */
0282 static void ucb1x00_irq(struct irq_desc *desc)
0283 {
0284     struct ucb1x00 *ucb = irq_desc_get_handler_data(desc);
0285     unsigned int isr, i;
0286 
0287     ucb1x00_enable(ucb);
0288     isr = ucb1x00_reg_read(ucb, UCB_IE_STATUS);
0289     ucb1x00_reg_write(ucb, UCB_IE_CLEAR, isr);
0290     ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
0291 
0292     for (i = 0; i < 16 && isr; i++, isr >>= 1)
0293         if (isr & 1)
0294             generic_handle_irq(ucb->irq_base + i);
0295     ucb1x00_disable(ucb);
0296 }
0297 
0298 static void ucb1x00_irq_update(struct ucb1x00 *ucb, unsigned mask)
0299 {
0300     ucb1x00_enable(ucb);
0301     if (ucb->irq_ris_enbl & mask)
0302         ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl &
0303                   ucb->irq_mask);
0304     if (ucb->irq_fal_enbl & mask)
0305         ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl &
0306                   ucb->irq_mask);
0307     ucb1x00_disable(ucb);
0308 }
0309 
0310 static void ucb1x00_irq_noop(struct irq_data *data)
0311 {
0312 }
0313 
0314 static void ucb1x00_irq_mask(struct irq_data *data)
0315 {
0316     struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data);
0317     unsigned mask = 1 << (data->irq - ucb->irq_base);
0318 
0319     raw_spin_lock(&ucb->irq_lock);
0320     ucb->irq_mask &= ~mask;
0321     ucb1x00_irq_update(ucb, mask);
0322     raw_spin_unlock(&ucb->irq_lock);
0323 }
0324 
0325 static void ucb1x00_irq_unmask(struct irq_data *data)
0326 {
0327     struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data);
0328     unsigned mask = 1 << (data->irq - ucb->irq_base);
0329 
0330     raw_spin_lock(&ucb->irq_lock);
0331     ucb->irq_mask |= mask;
0332     ucb1x00_irq_update(ucb, mask);
0333     raw_spin_unlock(&ucb->irq_lock);
0334 }
0335 
0336 static int ucb1x00_irq_set_type(struct irq_data *data, unsigned int type)
0337 {
0338     struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data);
0339     unsigned mask = 1 << (data->irq - ucb->irq_base);
0340 
0341     raw_spin_lock(&ucb->irq_lock);
0342     if (type & IRQ_TYPE_EDGE_RISING)
0343         ucb->irq_ris_enbl |= mask;
0344     else
0345         ucb->irq_ris_enbl &= ~mask;
0346 
0347     if (type & IRQ_TYPE_EDGE_FALLING)
0348         ucb->irq_fal_enbl |= mask;
0349     else
0350         ucb->irq_fal_enbl &= ~mask;
0351     if (ucb->irq_mask & mask) {
0352         ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl &
0353                   ucb->irq_mask);
0354         ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl &
0355                   ucb->irq_mask);
0356     }
0357     raw_spin_unlock(&ucb->irq_lock);
0358 
0359     return 0;
0360 }
0361 
0362 static int ucb1x00_irq_set_wake(struct irq_data *data, unsigned int on)
0363 {
0364     struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data);
0365     struct ucb1x00_plat_data *pdata = ucb->mcp->attached_device.platform_data;
0366     unsigned mask = 1 << (data->irq - ucb->irq_base);
0367 
0368     if (!pdata || !pdata->can_wakeup)
0369         return -EINVAL;
0370 
0371     raw_spin_lock(&ucb->irq_lock);
0372     if (on)
0373         ucb->irq_wake |= mask;
0374     else
0375         ucb->irq_wake &= ~mask;
0376     raw_spin_unlock(&ucb->irq_lock);
0377 
0378     return 0;
0379 }
0380 
0381 static struct irq_chip ucb1x00_irqchip = {
0382     .name = "ucb1x00",
0383     .irq_ack = ucb1x00_irq_noop,
0384     .irq_mask = ucb1x00_irq_mask,
0385     .irq_unmask = ucb1x00_irq_unmask,
0386     .irq_set_type = ucb1x00_irq_set_type,
0387     .irq_set_wake = ucb1x00_irq_set_wake,
0388 };
0389 
0390 static int ucb1x00_add_dev(struct ucb1x00 *ucb, struct ucb1x00_driver *drv)
0391 {
0392     struct ucb1x00_dev *dev;
0393     int ret;
0394 
0395     dev = kmalloc(sizeof(struct ucb1x00_dev), GFP_KERNEL);
0396     if (!dev)
0397         return -ENOMEM;
0398 
0399     dev->ucb = ucb;
0400     dev->drv = drv;
0401 
0402     ret = drv->add(dev);
0403     if (ret) {
0404         kfree(dev);
0405         return ret;
0406     }
0407 
0408     list_add_tail(&dev->dev_node, &ucb->devs);
0409     list_add_tail(&dev->drv_node, &drv->devs);
0410 
0411     return ret;
0412 }
0413 
0414 static void ucb1x00_remove_dev(struct ucb1x00_dev *dev)
0415 {
0416     dev->drv->remove(dev);
0417     list_del(&dev->dev_node);
0418     list_del(&dev->drv_node);
0419     kfree(dev);
0420 }
0421 
0422 /*
0423  * Try to probe our interrupt, rather than relying on lots of
0424  * hard-coded machine dependencies.  For reference, the expected
0425  * IRQ mappings are:
0426  *
0427  *      Machine     Default IRQ
0428  *  adsbitsy    IRQ_GPCIN4
0429  *  cerf        IRQ_GPIO_UCB1200_IRQ
0430  *  flexanet    IRQ_GPIO_GUI
0431  *  freebird    IRQ_GPIO_FREEBIRD_UCB1300_IRQ
0432  *  graphicsclient  ADS_EXT_IRQ(8)
0433  *  graphicsmaster  ADS_EXT_IRQ(8)
0434  *  lart        LART_IRQ_UCB1200
0435  *  omnimeter   IRQ_GPIO23
0436  *  pfs168      IRQ_GPIO_UCB1300_IRQ
0437  *  simpad      IRQ_GPIO_UCB1300_IRQ
0438  *  shannon     SHANNON_IRQ_GPIO_IRQ_CODEC
0439  *  yopy        IRQ_GPIO_UCB1200_IRQ
0440  */
0441 static int ucb1x00_detect_irq(struct ucb1x00 *ucb)
0442 {
0443     unsigned long mask;
0444 
0445     mask = probe_irq_on();
0446 
0447     /*
0448      * Enable the ADC interrupt.
0449      */
0450     ucb1x00_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC);
0451     ucb1x00_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC);
0452     ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
0453     ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
0454 
0455     /*
0456      * Cause an ADC interrupt.
0457      */
0458     ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA);
0459     ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START);
0460 
0461     /*
0462      * Wait for the conversion to complete.
0463      */
0464     while ((ucb1x00_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VAL) == 0);
0465     ucb1x00_reg_write(ucb, UCB_ADC_CR, 0);
0466 
0467     /*
0468      * Disable and clear interrupt.
0469      */
0470     ucb1x00_reg_write(ucb, UCB_IE_RIS, 0);
0471     ucb1x00_reg_write(ucb, UCB_IE_FAL, 0);
0472     ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
0473     ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
0474 
0475     /*
0476      * Read triggered interrupt.
0477      */
0478     return probe_irq_off(mask);
0479 }
0480 
0481 static void ucb1x00_release(struct device *dev)
0482 {
0483     struct ucb1x00 *ucb = classdev_to_ucb1x00(dev);
0484     kfree(ucb);
0485 }
0486 
0487 static struct class ucb1x00_class = {
0488     .name       = "ucb1x00",
0489     .dev_release    = ucb1x00_release,
0490 };
0491 
0492 static int ucb1x00_probe(struct mcp *mcp)
0493 {
0494     struct ucb1x00_plat_data *pdata = mcp->attached_device.platform_data;
0495     struct ucb1x00_driver *drv;
0496     struct ucb1x00 *ucb;
0497     unsigned id, i, irq_base;
0498     int ret = -ENODEV;
0499 
0500     /* Tell the platform to deassert the UCB1x00 reset */
0501     if (pdata && pdata->reset)
0502         pdata->reset(UCB_RST_PROBE);
0503 
0504     mcp_enable(mcp);
0505     id = mcp_reg_read(mcp, UCB_ID);
0506     mcp_disable(mcp);
0507 
0508     if (id != UCB_ID_1200 && id != UCB_ID_1300 && id != UCB_ID_TC35143) {
0509         printk(KERN_WARNING "UCB1x00 ID not found: %04x\n", id);
0510         goto out;
0511     }
0512 
0513     ucb = kzalloc(sizeof(struct ucb1x00), GFP_KERNEL);
0514     ret = -ENOMEM;
0515     if (!ucb)
0516         goto out;
0517 
0518     device_initialize(&ucb->dev);
0519     ucb->dev.class = &ucb1x00_class;
0520     ucb->dev.parent = &mcp->attached_device;
0521     dev_set_name(&ucb->dev, "ucb1x00");
0522 
0523     raw_spin_lock_init(&ucb->irq_lock);
0524     spin_lock_init(&ucb->io_lock);
0525     mutex_init(&ucb->adc_mutex);
0526 
0527     ucb->id  = id;
0528     ucb->mcp = mcp;
0529 
0530     ret = device_add(&ucb->dev);
0531     if (ret)
0532         goto err_dev_add;
0533 
0534     ucb1x00_enable(ucb);
0535     ucb->irq = ucb1x00_detect_irq(ucb);
0536     ucb1x00_disable(ucb);
0537     if (!ucb->irq) {
0538         dev_err(&ucb->dev, "IRQ probe failed\n");
0539         ret = -ENODEV;
0540         goto err_no_irq;
0541     }
0542 
0543     ucb->gpio.base = -1;
0544     irq_base = pdata ? pdata->irq_base : 0;
0545     ucb->irq_base = irq_alloc_descs(-1, irq_base, 16, -1);
0546     if (ucb->irq_base < 0) {
0547         dev_err(&ucb->dev, "unable to allocate 16 irqs: %d\n",
0548             ucb->irq_base);
0549         ret = ucb->irq_base;
0550         goto err_irq_alloc;
0551     }
0552 
0553     for (i = 0; i < 16; i++) {
0554         unsigned irq = ucb->irq_base + i;
0555 
0556         irq_set_chip_and_handler(irq, &ucb1x00_irqchip, handle_edge_irq);
0557         irq_set_chip_data(irq, ucb);
0558         irq_clear_status_flags(irq, IRQ_NOREQUEST);
0559     }
0560 
0561     irq_set_irq_type(ucb->irq, IRQ_TYPE_EDGE_RISING);
0562     irq_set_chained_handler_and_data(ucb->irq, ucb1x00_irq, ucb);
0563 
0564     if (pdata && pdata->gpio_base) {
0565         ucb->gpio.label = dev_name(&ucb->dev);
0566         ucb->gpio.parent = &ucb->dev;
0567         ucb->gpio.owner = THIS_MODULE;
0568         ucb->gpio.base = pdata->gpio_base;
0569         ucb->gpio.ngpio = 10;
0570         ucb->gpio.set = ucb1x00_gpio_set;
0571         ucb->gpio.get = ucb1x00_gpio_get;
0572         ucb->gpio.direction_input = ucb1x00_gpio_direction_input;
0573         ucb->gpio.direction_output = ucb1x00_gpio_direction_output;
0574         ucb->gpio.to_irq = ucb1x00_to_irq;
0575         ret = gpiochip_add_data(&ucb->gpio, ucb);
0576         if (ret)
0577             goto err_gpio_add;
0578     } else
0579         dev_info(&ucb->dev, "gpio_base not set so no gpiolib support");
0580 
0581     mcp_set_drvdata(mcp, ucb);
0582 
0583     if (pdata)
0584         device_set_wakeup_capable(&ucb->dev, pdata->can_wakeup);
0585 
0586     INIT_LIST_HEAD(&ucb->devs);
0587     mutex_lock(&ucb1x00_mutex);
0588     list_add_tail(&ucb->node, &ucb1x00_devices);
0589     list_for_each_entry(drv, &ucb1x00_drivers, node) {
0590         ucb1x00_add_dev(ucb, drv);
0591     }
0592     mutex_unlock(&ucb1x00_mutex);
0593 
0594     return ret;
0595 
0596  err_gpio_add:
0597     irq_set_chained_handler(ucb->irq, NULL);
0598  err_irq_alloc:
0599     if (ucb->irq_base > 0)
0600         irq_free_descs(ucb->irq_base, 16);
0601  err_no_irq:
0602     device_del(&ucb->dev);
0603  err_dev_add:
0604     put_device(&ucb->dev);
0605  out:
0606     if (pdata && pdata->reset)
0607         pdata->reset(UCB_RST_PROBE_FAIL);
0608     return ret;
0609 }
0610 
0611 static void ucb1x00_remove(struct mcp *mcp)
0612 {
0613     struct ucb1x00_plat_data *pdata = mcp->attached_device.platform_data;
0614     struct ucb1x00 *ucb = mcp_get_drvdata(mcp);
0615     struct list_head *l, *n;
0616 
0617     mutex_lock(&ucb1x00_mutex);
0618     list_del(&ucb->node);
0619     list_for_each_safe(l, n, &ucb->devs) {
0620         struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, dev_node);
0621         ucb1x00_remove_dev(dev);
0622     }
0623     mutex_unlock(&ucb1x00_mutex);
0624 
0625     if (ucb->gpio.base != -1)
0626         gpiochip_remove(&ucb->gpio);
0627 
0628     irq_set_chained_handler(ucb->irq, NULL);
0629     irq_free_descs(ucb->irq_base, 16);
0630     device_unregister(&ucb->dev);
0631 
0632     if (pdata && pdata->reset)
0633         pdata->reset(UCB_RST_REMOVE);
0634 }
0635 
0636 int ucb1x00_register_driver(struct ucb1x00_driver *drv)
0637 {
0638     struct ucb1x00 *ucb;
0639 
0640     INIT_LIST_HEAD(&drv->devs);
0641     mutex_lock(&ucb1x00_mutex);
0642     list_add_tail(&drv->node, &ucb1x00_drivers);
0643     list_for_each_entry(ucb, &ucb1x00_devices, node) {
0644         ucb1x00_add_dev(ucb, drv);
0645     }
0646     mutex_unlock(&ucb1x00_mutex);
0647     return 0;
0648 }
0649 
0650 void ucb1x00_unregister_driver(struct ucb1x00_driver *drv)
0651 {
0652     struct list_head *n, *l;
0653 
0654     mutex_lock(&ucb1x00_mutex);
0655     list_del(&drv->node);
0656     list_for_each_safe(l, n, &drv->devs) {
0657         struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, drv_node);
0658         ucb1x00_remove_dev(dev);
0659     }
0660     mutex_unlock(&ucb1x00_mutex);
0661 }
0662 
0663 #ifdef CONFIG_PM_SLEEP
0664 static int ucb1x00_suspend(struct device *dev)
0665 {
0666     struct ucb1x00_plat_data *pdata = dev_get_platdata(dev);
0667     struct ucb1x00 *ucb = dev_get_drvdata(dev);
0668     struct ucb1x00_dev *udev;
0669 
0670     mutex_lock(&ucb1x00_mutex);
0671     list_for_each_entry(udev, &ucb->devs, dev_node) {
0672         if (udev->drv->suspend)
0673             udev->drv->suspend(udev);
0674     }
0675     mutex_unlock(&ucb1x00_mutex);
0676 
0677     if (ucb->irq_wake) {
0678         unsigned long flags;
0679 
0680         raw_spin_lock_irqsave(&ucb->irq_lock, flags);
0681         ucb1x00_enable(ucb);
0682         ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl &
0683                   ucb->irq_wake);
0684         ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl &
0685                   ucb->irq_wake);
0686         ucb1x00_disable(ucb);
0687         raw_spin_unlock_irqrestore(&ucb->irq_lock, flags);
0688 
0689         enable_irq_wake(ucb->irq);
0690     } else if (pdata && pdata->reset)
0691         pdata->reset(UCB_RST_SUSPEND);
0692 
0693     return 0;
0694 }
0695 
0696 static int ucb1x00_resume(struct device *dev)
0697 {
0698     struct ucb1x00_plat_data *pdata = dev_get_platdata(dev);
0699     struct ucb1x00 *ucb = dev_get_drvdata(dev);
0700     struct ucb1x00_dev *udev;
0701 
0702     if (!ucb->irq_wake && pdata && pdata->reset)
0703         pdata->reset(UCB_RST_RESUME);
0704 
0705     ucb1x00_enable(ucb);
0706     ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
0707     ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
0708 
0709     if (ucb->irq_wake) {
0710         unsigned long flags;
0711 
0712         raw_spin_lock_irqsave(&ucb->irq_lock, flags);
0713         ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl &
0714                   ucb->irq_mask);
0715         ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl &
0716                   ucb->irq_mask);
0717         raw_spin_unlock_irqrestore(&ucb->irq_lock, flags);
0718 
0719         disable_irq_wake(ucb->irq);
0720     }
0721     ucb1x00_disable(ucb);
0722 
0723     mutex_lock(&ucb1x00_mutex);
0724     list_for_each_entry(udev, &ucb->devs, dev_node) {
0725         if (udev->drv->resume)
0726             udev->drv->resume(udev);
0727     }
0728     mutex_unlock(&ucb1x00_mutex);
0729     return 0;
0730 }
0731 #endif
0732 
0733 static SIMPLE_DEV_PM_OPS(ucb1x00_pm_ops, ucb1x00_suspend, ucb1x00_resume);
0734 
0735 static struct mcp_driver ucb1x00_driver = {
0736     .drv        = {
0737         .name   = "ucb1x00",
0738         .owner  = THIS_MODULE,
0739         .pm = &ucb1x00_pm_ops,
0740     },
0741     .probe      = ucb1x00_probe,
0742     .remove     = ucb1x00_remove,
0743 };
0744 
0745 static int __init ucb1x00_init(void)
0746 {
0747     int ret = class_register(&ucb1x00_class);
0748     if (ret == 0) {
0749         ret = mcp_driver_register(&ucb1x00_driver);
0750         if (ret)
0751             class_unregister(&ucb1x00_class);
0752     }
0753     return ret;
0754 }
0755 
0756 static void __exit ucb1x00_exit(void)
0757 {
0758     mcp_driver_unregister(&ucb1x00_driver);
0759     class_unregister(&ucb1x00_class);
0760 }
0761 
0762 module_init(ucb1x00_init);
0763 module_exit(ucb1x00_exit);
0764 
0765 EXPORT_SYMBOL(ucb1x00_io_set_dir);
0766 EXPORT_SYMBOL(ucb1x00_io_write);
0767 EXPORT_SYMBOL(ucb1x00_io_read);
0768 
0769 EXPORT_SYMBOL(ucb1x00_adc_enable);
0770 EXPORT_SYMBOL(ucb1x00_adc_read);
0771 EXPORT_SYMBOL(ucb1x00_adc_disable);
0772 
0773 EXPORT_SYMBOL(ucb1x00_register_driver);
0774 EXPORT_SYMBOL(ucb1x00_unregister_driver);
0775 
0776 MODULE_ALIAS("mcp:ucb1x00");
0777 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
0778 MODULE_DESCRIPTION("UCB1x00 core driver");
0779 MODULE_LICENSE("GPL");
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