drivers/mfd/timberdale.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * timberdale.h timberdale FPGA MFD driver defines
0004  * Copyright (c) 2009 Intel Corporation
0005  */
0006
0007 /* Supports:
0008  * Timberdale FPGA
0009  */
0010
0011 #ifndef MFD_TIMBERDALE_H
0012 #define MFD_TIMBERDALE_H
0013
0014 #define DRV_VERSION     "0.3"
0015
0016 /* This driver only support versions >= 3.8 and < 4.0  */
0017 #define TIMB_SUPPORTED_MAJOR    3
0018
0019 /* This driver only support minor >= 8 */
0020 #define TIMB_REQUIRED_MINOR 8
0021
0022 /* Registers of the control area */
0023 #define TIMB_REV_MAJOR  0x00
0024 #define TIMB_REV_MINOR  0x04
0025 #define TIMB_HW_CONFIG  0x08
0026 #define TIMB_SW_RST 0x40
0027
0028 /* bits in the TIMB_HW_CONFIG register */
0029 #define TIMB_HW_CONFIG_SPI_8BIT 0x80
0030
0031 #define TIMB_HW_VER_MASK    0x0f
0032 #define TIMB_HW_VER0        0x00
0033 #define TIMB_HW_VER1        0x01
0034 #define TIMB_HW_VER2        0x02
0035 #define TIMB_HW_VER3        0x03
0036
0037 #define OCORESOFFSET    0x0
0038 #define OCORESEND   0x1f
0039
0040 #define SPIOFFSET   0x80
0041 #define SPIEND      0xff
0042
0043 #define UARTLITEOFFSET  0x100
0044 #define UARTLITEEND 0x10f
0045
0046 #define RDSOFFSET   0x180
0047 #define RDSEND      0x183
0048
0049 #define ETHOFFSET   0x300
0050 #define ETHEND      0x3ff
0051
0052 #define GPIOOFFSET  0x400
0053 #define GPIOEND     0x7ff
0054
0055 #define CHIPCTLOFFSET   0x800
0056 #define CHIPCTLEND  0x8ff
0057 #define CHIPCTLSIZE (CHIPCTLEND - CHIPCTLOFFSET + 1)
0058
0059 #define INTCOFFSET  0xc00
0060 #define INTCEND     0xfff
0061 #define INTCSIZE    (INTCEND - INTCOFFSET)
0062
0063 #define MOSTOFFSET  0x1000
0064 #define MOSTEND     0x13ff
0065
0066 #define UARTOFFSET  0x1400
0067 #define UARTEND     0x17ff
0068
0069 #define XIICOFFSET  0x1800
0070 #define XIICEND     0x19ff
0071
0072 #define I2SOFFSET   0x1C00
0073 #define I2SEND      0x1fff
0074
0075 #define LOGIWOFFSET 0x30000
0076 #define LOGIWEND    0x37fff
0077
0078 #define MLCOREOFFSET    0x40000
0079 #define MLCOREEND   0x43fff
0080
0081 #define DMAOFFSET   0x01000000
0082 #define DMAEND      0x013fffff
0083
0084 /* SDHC0 is placed in PCI bar 1 */
0085 #define SDHC0OFFSET 0x00
0086 #define SDHC0END    0xff
0087
0088 /* SDHC1 is placed in PCI bar 2 */
0089 #define SDHC1OFFSET 0x00
0090 #define SDHC1END    0xff
0091
0092 #define PCI_VENDOR_ID_TIMB  0x10ee
0093 #define PCI_DEVICE_ID_TIMB  0xa123
0094
0095 #define IRQ_TIMBERDALE_INIC     0
0096 #define IRQ_TIMBERDALE_MLB      1
0097 #define IRQ_TIMBERDALE_GPIO     2
0098 #define IRQ_TIMBERDALE_I2C      3
0099 #define IRQ_TIMBERDALE_UART     4
0100 #define IRQ_TIMBERDALE_DMA      5
0101 #define IRQ_TIMBERDALE_I2S      6
0102 #define IRQ_TIMBERDALE_TSC_INT      7
0103 #define IRQ_TIMBERDALE_SDHC     8
0104 #define IRQ_TIMBERDALE_ADV7180      9
0105 #define IRQ_TIMBERDALE_ETHSW_IF     10
0106 #define IRQ_TIMBERDALE_SPI      11
0107 #define IRQ_TIMBERDALE_UARTLITE     12
0108 #define IRQ_TIMBERDALE_MLCORE       13
0109 #define IRQ_TIMBERDALE_MLCORE_BUF   14
0110 #define IRQ_TIMBERDALE_RDS      15
0111 #define TIMBERDALE_NR_IRQS      16
0112
0113 #define GPIO_PIN_ASCB       8
0114 #define GPIO_PIN_INIC_RST   14
0115 #define GPIO_PIN_BT_RST     15
0116 #define GPIO_NR_PINS        16
0117
0118 /* DMA Channels */
0119 #define DMA_UART_RX         0
0120 #define DMA_UART_TX         1
0121 #define DMA_MLB_RX          2
0122 #define DMA_MLB_TX          3
0123 #define DMA_VIDEO_RX        4
0124 #define DMA_VIDEO_DROP      5
0125 #define DMA_SDHCI_RX        6
0126 #define DMA_SDHCI_TX        7
0127 #define DMA_ETH_RX          8
0128 #define DMA_ETH_TX          9
0129
0130 #endif