drivers/mfd/stpmic1.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (C) STMicroelectronics 2018
0003 // Author: Pascal Paillet <p.paillet@st.com>
0004
0005 #include <linux/i2c.h>
0006 #include <linux/interrupt.h>
0007 #include <linux/mfd/core.h>
0008 #include <linux/mfd/stpmic1.h>
0009 #include <linux/module.h>
0010 #include <linux/of.h>
0011 #include <linux/of_irq.h>
0012 #include <linux/of_platform.h>
0013 #include <linux/pm_wakeirq.h>
0014 #include <linux/regmap.h>
0015
0016 #include <dt-bindings/mfd/st,stpmic1.h>
0017
0018 #define STPMIC1_MAIN_IRQ 0
0019
0020 static const struct regmap_range stpmic1_readable_ranges[] = {
0021     regmap_reg_range(TURN_ON_SR, VERSION_SR),
0022     regmap_reg_range(SWOFF_PWRCTRL_CR, LDO6_STDBY_CR),
0023     regmap_reg_range(BST_SW_CR, BST_SW_CR),
0024     regmap_reg_range(INT_PENDING_R1, INT_PENDING_R4),
0025     regmap_reg_range(INT_CLEAR_R1, INT_CLEAR_R4),
0026     regmap_reg_range(INT_MASK_R1, INT_MASK_R4),
0027     regmap_reg_range(INT_SET_MASK_R1, INT_SET_MASK_R4),
0028     regmap_reg_range(INT_CLEAR_MASK_R1, INT_CLEAR_MASK_R4),
0029     regmap_reg_range(INT_SRC_R1, INT_SRC_R1),
0030 };
0031
0032 static const struct regmap_range stpmic1_writeable_ranges[] = {
0033     regmap_reg_range(SWOFF_PWRCTRL_CR, LDO6_STDBY_CR),
0034     regmap_reg_range(BST_SW_CR, BST_SW_CR),
0035     regmap_reg_range(INT_CLEAR_R1, INT_CLEAR_R4),
0036     regmap_reg_range(INT_SET_MASK_R1, INT_SET_MASK_R4),
0037     regmap_reg_range(INT_CLEAR_MASK_R1, INT_CLEAR_MASK_R4),
0038 };
0039
0040 static const struct regmap_range stpmic1_volatile_ranges[] = {
0041     regmap_reg_range(TURN_ON_SR, VERSION_SR),
0042     regmap_reg_range(WCHDG_CR, WCHDG_CR),
0043     regmap_reg_range(INT_PENDING_R1, INT_PENDING_R4),
0044     regmap_reg_range(INT_SRC_R1, INT_SRC_R4),
0045 };
0046
0047 static const struct regmap_access_table stpmic1_readable_table = {
0048     .yes_ranges = stpmic1_readable_ranges,
0049     .n_yes_ranges = ARRAY_SIZE(stpmic1_readable_ranges),
0050 };
0051
0052 static const struct regmap_access_table stpmic1_writeable_table = {
0053     .yes_ranges = stpmic1_writeable_ranges,
0054     .n_yes_ranges = ARRAY_SIZE(stpmic1_writeable_ranges),
0055 };
0056
0057 static const struct regmap_access_table stpmic1_volatile_table = {
0058     .yes_ranges = stpmic1_volatile_ranges,
0059     .n_yes_ranges = ARRAY_SIZE(stpmic1_volatile_ranges),
0060 };
0061
0062 static const struct regmap_config stpmic1_regmap_config = {
0063     .reg_bits = 8,
0064     .val_bits = 8,
0065     .cache_type = REGCACHE_RBTREE,
0066     .max_register = PMIC_MAX_REGISTER_ADDRESS,
0067     .rd_table = &stpmic1_readable_table,
0068     .wr_table = &stpmic1_writeable_table,
0069     .volatile_table = &stpmic1_volatile_table,
0070 };
0071
0072 static const struct regmap_irq stpmic1_irqs[] = {
0073     REGMAP_IRQ_REG(IT_PONKEY_F, 0, 0x01),
0074     REGMAP_IRQ_REG(IT_PONKEY_R, 0, 0x02),
0075     REGMAP_IRQ_REG(IT_WAKEUP_F, 0, 0x04),
0076     REGMAP_IRQ_REG(IT_WAKEUP_R, 0, 0x08),
0077     REGMAP_IRQ_REG(IT_VBUS_OTG_F, 0, 0x10),
0078     REGMAP_IRQ_REG(IT_VBUS_OTG_R, 0, 0x20),
0079     REGMAP_IRQ_REG(IT_SWOUT_F, 0, 0x40),
0080     REGMAP_IRQ_REG(IT_SWOUT_R, 0, 0x80),
0081
0082     REGMAP_IRQ_REG(IT_CURLIM_BUCK1, 1, 0x01),
0083     REGMAP_IRQ_REG(IT_CURLIM_BUCK2, 1, 0x02),
0084     REGMAP_IRQ_REG(IT_CURLIM_BUCK3, 1, 0x04),
0085     REGMAP_IRQ_REG(IT_CURLIM_BUCK4, 1, 0x08),
0086     REGMAP_IRQ_REG(IT_OCP_OTG, 1, 0x10),
0087     REGMAP_IRQ_REG(IT_OCP_SWOUT, 1, 0x20),
0088     REGMAP_IRQ_REG(IT_OCP_BOOST, 1, 0x40),
0089     REGMAP_IRQ_REG(IT_OVP_BOOST, 1, 0x80),
0090
0091     REGMAP_IRQ_REG(IT_CURLIM_LDO1, 2, 0x01),
0092     REGMAP_IRQ_REG(IT_CURLIM_LDO2, 2, 0x02),
0093     REGMAP_IRQ_REG(IT_CURLIM_LDO3, 2, 0x04),
0094     REGMAP_IRQ_REG(IT_CURLIM_LDO4, 2, 0x08),
0095     REGMAP_IRQ_REG(IT_CURLIM_LDO5, 2, 0x10),
0096     REGMAP_IRQ_REG(IT_CURLIM_LDO6, 2, 0x20),
0097     REGMAP_IRQ_REG(IT_SHORT_SWOTG, 2, 0x40),
0098     REGMAP_IRQ_REG(IT_SHORT_SWOUT, 2, 0x80),
0099
0100     REGMAP_IRQ_REG(IT_TWARN_F, 3, 0x01),
0101     REGMAP_IRQ_REG(IT_TWARN_R, 3, 0x02),
0102     REGMAP_IRQ_REG(IT_VINLOW_F, 3, 0x04),
0103     REGMAP_IRQ_REG(IT_VINLOW_R, 3, 0x08),
0104     REGMAP_IRQ_REG(IT_SWIN_F, 3, 0x40),
0105     REGMAP_IRQ_REG(IT_SWIN_R, 3, 0x80),
0106 };
0107
0108 static const struct regmap_irq_chip stpmic1_regmap_irq_chip = {
0109     .name = "pmic_irq",
0110     .status_base = INT_PENDING_R1,
0111     .mask_base = INT_CLEAR_MASK_R1,
0112     .unmask_base = INT_SET_MASK_R1,
0113     .ack_base = INT_CLEAR_R1,
0114     .num_regs = STPMIC1_PMIC_NUM_IRQ_REGS,
0115     .irqs = stpmic1_irqs,
0116     .num_irqs = ARRAY_SIZE(stpmic1_irqs),
0117 };
0118
0119 static int stpmic1_probe(struct i2c_client *i2c,
0120              const struct i2c_device_id *id)
0121 {
0122     struct stpmic1 *ddata;
0123     struct device *dev = &i2c->dev;
0124     int ret;
0125     struct device_node *np = dev->of_node;
0126     u32 reg;
0127
0128     ddata = devm_kzalloc(dev, sizeof(struct stpmic1), GFP_KERNEL);
0129     if (!ddata)
0130         return -ENOMEM;
0131
0132     i2c_set_clientdata(i2c, ddata);
0133     ddata->dev = dev;
0134
0135     ddata->regmap = devm_regmap_init_i2c(i2c, &stpmic1_regmap_config);
0136     if (IS_ERR(ddata->regmap))
0137         return PTR_ERR(ddata->regmap);
0138
0139     ddata->irq = of_irq_get(np, STPMIC1_MAIN_IRQ);
0140     if (ddata->irq < 0) {
0141         dev_err(dev, "Failed to get main IRQ: %d\n", ddata->irq);
0142         return ddata->irq;
0143     }
0144
0145     ret = regmap_read(ddata->regmap, VERSION_SR, &reg);
0146     if (ret) {
0147         dev_err(dev, "Unable to read PMIC version\n");
0148         return ret;
0149     }
0150     dev_info(dev, "PMIC Chip Version: 0x%x\n", reg);
0151
0152     /* Initialize PMIC IRQ Chip & associated IRQ domains */
0153     ret = devm_regmap_add_irq_chip(dev, ddata->regmap, ddata->irq,
0154                        IRQF_ONESHOT | IRQF_SHARED,
0155                        0, &stpmic1_regmap_irq_chip,
0156                        &ddata->irq_data);
0157     if (ret) {
0158         dev_err(dev, "IRQ Chip registration failed: %d\n", ret);
0159         return ret;
0160     }
0161
0162     return devm_of_platform_populate(dev);
0163 }
0164
0165 #ifdef CONFIG_PM_SLEEP
0166 static int stpmic1_suspend(struct device *dev)
0167 {
0168     struct i2c_client *i2c = to_i2c_client(dev);
0169     struct stpmic1 *pmic_dev = i2c_get_clientdata(i2c);
0170
0171     disable_irq(pmic_dev->irq);
0172
0173     return 0;
0174 }
0175
0176 static int stpmic1_resume(struct device *dev)
0177 {
0178     struct i2c_client *i2c = to_i2c_client(dev);
0179     struct stpmic1 *pmic_dev = i2c_get_clientdata(i2c);
0180     int ret;
0181
0182     ret = regcache_sync(pmic_dev->regmap);
0183     if (ret)
0184         return ret;
0185
0186     enable_irq(pmic_dev->irq);
0187
0188     return 0;
0189 }
0190 #endif
0191
0192 static SIMPLE_DEV_PM_OPS(stpmic1_pm, stpmic1_suspend, stpmic1_resume);
0193
0194 static const struct of_device_id stpmic1_of_match[] = {
0195     { .compatible = "st,stpmic1", },
0196     {},
0197 };
0198 MODULE_DEVICE_TABLE(of, stpmic1_of_match);
0199
0200 static struct i2c_driver stpmic1_driver = {
0201     .driver = {
0202         .name = "stpmic1",
0203         .of_match_table = of_match_ptr(stpmic1_of_match),
0204         .pm = &stpmic1_pm,
0205     },
0206     .probe = stpmic1_probe,
0207 };
0208
0209 module_i2c_driver(stpmic1_driver);
0210
0211 MODULE_DESCRIPTION("STPMIC1 PMIC Driver");
0212 MODULE_AUTHOR("Pascal Paillet <p.paillet@st.com>");
0213 MODULE_LICENSE("GPL v2");