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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * ST Microelectronics MFD: stmpe's driver
0004  *
0005  * Copyright (C) ST-Ericsson SA 2010
0006  *
0007  * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
0008  */
0009 
0010 #include <linux/err.h>
0011 #include <linux/gpio.h>
0012 #include <linux/export.h>
0013 #include <linux/kernel.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/irq.h>
0016 #include <linux/irqdomain.h>
0017 #include <linux/of.h>
0018 #include <linux/of_gpio.h>
0019 #include <linux/pm.h>
0020 #include <linux/slab.h>
0021 #include <linux/mfd/core.h>
0022 #include <linux/delay.h>
0023 #include <linux/regulator/consumer.h>
0024 #include "stmpe.h"
0025 
0026 /**
0027  * struct stmpe_platform_data - STMPE platform data
0028  * @id: device id to distinguish between multiple STMPEs on the same board
0029  * @blocks: bitmask of blocks to enable (use STMPE_BLOCK_*)
0030  * @irq_trigger: IRQ trigger to use for the interrupt to the host
0031  * @autosleep: bool to enable/disable stmpe autosleep
0032  * @autosleep_timeout: inactivity timeout in milliseconds for autosleep
0033  * @irq_over_gpio: true if gpio is used to get irq
0034  * @irq_gpio: gpio number over which irq will be requested (significant only if
0035  *        irq_over_gpio is true)
0036  */
0037 struct stmpe_platform_data {
0038     int id;
0039     unsigned int blocks;
0040     unsigned int irq_trigger;
0041     bool autosleep;
0042     bool irq_over_gpio;
0043     int irq_gpio;
0044     int autosleep_timeout;
0045 };
0046 
0047 static int __stmpe_enable(struct stmpe *stmpe, unsigned int blocks)
0048 {
0049     return stmpe->variant->enable(stmpe, blocks, true);
0050 }
0051 
0052 static int __stmpe_disable(struct stmpe *stmpe, unsigned int blocks)
0053 {
0054     return stmpe->variant->enable(stmpe, blocks, false);
0055 }
0056 
0057 static int __stmpe_reg_read(struct stmpe *stmpe, u8 reg)
0058 {
0059     int ret;
0060 
0061     ret = stmpe->ci->read_byte(stmpe, reg);
0062     if (ret < 0)
0063         dev_err(stmpe->dev, "failed to read reg %#x: %d\n", reg, ret);
0064 
0065     dev_vdbg(stmpe->dev, "rd: reg %#x => data %#x\n", reg, ret);
0066 
0067     return ret;
0068 }
0069 
0070 static int __stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val)
0071 {
0072     int ret;
0073 
0074     dev_vdbg(stmpe->dev, "wr: reg %#x <= %#x\n", reg, val);
0075 
0076     ret = stmpe->ci->write_byte(stmpe, reg, val);
0077     if (ret < 0)
0078         dev_err(stmpe->dev, "failed to write reg %#x: %d\n", reg, ret);
0079 
0080     return ret;
0081 }
0082 
0083 static int __stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val)
0084 {
0085     int ret;
0086 
0087     ret = __stmpe_reg_read(stmpe, reg);
0088     if (ret < 0)
0089         return ret;
0090 
0091     ret &= ~mask;
0092     ret |= val;
0093 
0094     return __stmpe_reg_write(stmpe, reg, ret);
0095 }
0096 
0097 static int __stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length,
0098                   u8 *values)
0099 {
0100     int ret;
0101 
0102     ret = stmpe->ci->read_block(stmpe, reg, length, values);
0103     if (ret < 0)
0104         dev_err(stmpe->dev, "failed to read regs %#x: %d\n", reg, ret);
0105 
0106     dev_vdbg(stmpe->dev, "rd: reg %#x (%d) => ret %#x\n", reg, length, ret);
0107     stmpe_dump_bytes("stmpe rd: ", values, length);
0108 
0109     return ret;
0110 }
0111 
0112 static int __stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length,
0113             const u8 *values)
0114 {
0115     int ret;
0116 
0117     dev_vdbg(stmpe->dev, "wr: regs %#x (%d)\n", reg, length);
0118     stmpe_dump_bytes("stmpe wr: ", values, length);
0119 
0120     ret = stmpe->ci->write_block(stmpe, reg, length, values);
0121     if (ret < 0)
0122         dev_err(stmpe->dev, "failed to write regs %#x: %d\n", reg, ret);
0123 
0124     return ret;
0125 }
0126 
0127 /**
0128  * stmpe_enable - enable blocks on an STMPE device
0129  * @stmpe:  Device to work on
0130  * @blocks: Mask of blocks (enum stmpe_block values) to enable
0131  */
0132 int stmpe_enable(struct stmpe *stmpe, unsigned int blocks)
0133 {
0134     int ret;
0135 
0136     mutex_lock(&stmpe->lock);
0137     ret = __stmpe_enable(stmpe, blocks);
0138     mutex_unlock(&stmpe->lock);
0139 
0140     return ret;
0141 }
0142 EXPORT_SYMBOL_GPL(stmpe_enable);
0143 
0144 /**
0145  * stmpe_disable - disable blocks on an STMPE device
0146  * @stmpe:  Device to work on
0147  * @blocks: Mask of blocks (enum stmpe_block values) to enable
0148  */
0149 int stmpe_disable(struct stmpe *stmpe, unsigned int blocks)
0150 {
0151     int ret;
0152 
0153     mutex_lock(&stmpe->lock);
0154     ret = __stmpe_disable(stmpe, blocks);
0155     mutex_unlock(&stmpe->lock);
0156 
0157     return ret;
0158 }
0159 EXPORT_SYMBOL_GPL(stmpe_disable);
0160 
0161 /**
0162  * stmpe_reg_read() - read a single STMPE register
0163  * @stmpe:  Device to read from
0164  * @reg:    Register to read
0165  */
0166 int stmpe_reg_read(struct stmpe *stmpe, u8 reg)
0167 {
0168     int ret;
0169 
0170     mutex_lock(&stmpe->lock);
0171     ret = __stmpe_reg_read(stmpe, reg);
0172     mutex_unlock(&stmpe->lock);
0173 
0174     return ret;
0175 }
0176 EXPORT_SYMBOL_GPL(stmpe_reg_read);
0177 
0178 /**
0179  * stmpe_reg_write() - write a single STMPE register
0180  * @stmpe:  Device to write to
0181  * @reg:    Register to write
0182  * @val:    Value to write
0183  */
0184 int stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val)
0185 {
0186     int ret;
0187 
0188     mutex_lock(&stmpe->lock);
0189     ret = __stmpe_reg_write(stmpe, reg, val);
0190     mutex_unlock(&stmpe->lock);
0191 
0192     return ret;
0193 }
0194 EXPORT_SYMBOL_GPL(stmpe_reg_write);
0195 
0196 /**
0197  * stmpe_set_bits() - set the value of a bitfield in a STMPE register
0198  * @stmpe:  Device to write to
0199  * @reg:    Register to write
0200  * @mask:   Mask of bits to set
0201  * @val:    Value to set
0202  */
0203 int stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val)
0204 {
0205     int ret;
0206 
0207     mutex_lock(&stmpe->lock);
0208     ret = __stmpe_set_bits(stmpe, reg, mask, val);
0209     mutex_unlock(&stmpe->lock);
0210 
0211     return ret;
0212 }
0213 EXPORT_SYMBOL_GPL(stmpe_set_bits);
0214 
0215 /**
0216  * stmpe_block_read() - read multiple STMPE registers
0217  * @stmpe:  Device to read from
0218  * @reg:    First register
0219  * @length: Number of registers
0220  * @values: Buffer to write to
0221  */
0222 int stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length, u8 *values)
0223 {
0224     int ret;
0225 
0226     mutex_lock(&stmpe->lock);
0227     ret = __stmpe_block_read(stmpe, reg, length, values);
0228     mutex_unlock(&stmpe->lock);
0229 
0230     return ret;
0231 }
0232 EXPORT_SYMBOL_GPL(stmpe_block_read);
0233 
0234 /**
0235  * stmpe_block_write() - write multiple STMPE registers
0236  * @stmpe:  Device to write to
0237  * @reg:    First register
0238  * @length: Number of registers
0239  * @values: Values to write
0240  */
0241 int stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length,
0242               const u8 *values)
0243 {
0244     int ret;
0245 
0246     mutex_lock(&stmpe->lock);
0247     ret = __stmpe_block_write(stmpe, reg, length, values);
0248     mutex_unlock(&stmpe->lock);
0249 
0250     return ret;
0251 }
0252 EXPORT_SYMBOL_GPL(stmpe_block_write);
0253 
0254 /**
0255  * stmpe_set_altfunc()- set the alternate function for STMPE pins
0256  * @stmpe:  Device to configure
0257  * @pins:   Bitmask of pins to affect
0258  * @block:  block to enable alternate functions for
0259  *
0260  * @pins is assumed to have a bit set for each of the bits whose alternate
0261  * function is to be changed, numbered according to the GPIOXY numbers.
0262  *
0263  * If the GPIO module is not enabled, this function automatically enables it in
0264  * order to perform the change.
0265  */
0266 int stmpe_set_altfunc(struct stmpe *stmpe, u32 pins, enum stmpe_block block)
0267 {
0268     struct stmpe_variant_info *variant = stmpe->variant;
0269     u8 regaddr = stmpe->regs[STMPE_IDX_GPAFR_U_MSB];
0270     int af_bits = variant->af_bits;
0271     int numregs = DIV_ROUND_UP(stmpe->num_gpios * af_bits, 8);
0272     int mask = (1 << af_bits) - 1;
0273     u8 regs[8];
0274     int af, afperreg, ret;
0275 
0276     if (!variant->get_altfunc)
0277         return 0;
0278 
0279     afperreg = 8 / af_bits;
0280     mutex_lock(&stmpe->lock);
0281 
0282     ret = __stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
0283     if (ret < 0)
0284         goto out;
0285 
0286     ret = __stmpe_block_read(stmpe, regaddr, numregs, regs);
0287     if (ret < 0)
0288         goto out;
0289 
0290     af = variant->get_altfunc(stmpe, block);
0291 
0292     while (pins) {
0293         int pin = __ffs(pins);
0294         int regoffset = numregs - (pin / afperreg) - 1;
0295         int pos = (pin % afperreg) * (8 / afperreg);
0296 
0297         regs[regoffset] &= ~(mask << pos);
0298         regs[regoffset] |= af << pos;
0299 
0300         pins &= ~(1 << pin);
0301     }
0302 
0303     ret = __stmpe_block_write(stmpe, regaddr, numregs, regs);
0304 
0305 out:
0306     mutex_unlock(&stmpe->lock);
0307     return ret;
0308 }
0309 EXPORT_SYMBOL_GPL(stmpe_set_altfunc);
0310 
0311 /*
0312  * GPIO (all variants)
0313  */
0314 
0315 static struct resource stmpe_gpio_resources[] = {
0316     /* Start and end filled dynamically */
0317     {
0318         .flags  = IORESOURCE_IRQ,
0319     },
0320 };
0321 
0322 static const struct mfd_cell stmpe_gpio_cell = {
0323     .name       = "stmpe-gpio",
0324     .of_compatible  = "st,stmpe-gpio",
0325     .resources  = stmpe_gpio_resources,
0326     .num_resources  = ARRAY_SIZE(stmpe_gpio_resources),
0327 };
0328 
0329 static const struct mfd_cell stmpe_gpio_cell_noirq = {
0330     .name       = "stmpe-gpio",
0331     .of_compatible  = "st,stmpe-gpio",
0332     /* gpio cell resources consist of an irq only so no resources here */
0333 };
0334 
0335 /*
0336  * Keypad (1601, 2401, 2403)
0337  */
0338 
0339 static struct resource stmpe_keypad_resources[] = {
0340     /* Start and end filled dynamically */
0341     {
0342         .name   = "KEYPAD",
0343         .flags  = IORESOURCE_IRQ,
0344     },
0345     {
0346         .name   = "KEYPAD_OVER",
0347         .flags  = IORESOURCE_IRQ,
0348     },
0349 };
0350 
0351 static const struct mfd_cell stmpe_keypad_cell = {
0352     .name       = "stmpe-keypad",
0353     .of_compatible  = "st,stmpe-keypad",
0354     .resources  = stmpe_keypad_resources,
0355     .num_resources  = ARRAY_SIZE(stmpe_keypad_resources),
0356 };
0357 
0358 /*
0359  * PWM (1601, 2401, 2403)
0360  */
0361 static struct resource stmpe_pwm_resources[] = {
0362     /* Start and end filled dynamically */
0363     {
0364         .name   = "PWM0",
0365         .flags  = IORESOURCE_IRQ,
0366     },
0367     {
0368         .name   = "PWM1",
0369         .flags  = IORESOURCE_IRQ,
0370     },
0371     {
0372         .name   = "PWM2",
0373         .flags  = IORESOURCE_IRQ,
0374     },
0375 };
0376 
0377 static const struct mfd_cell stmpe_pwm_cell = {
0378     .name       = "stmpe-pwm",
0379     .of_compatible  = "st,stmpe-pwm",
0380     .resources  = stmpe_pwm_resources,
0381     .num_resources  = ARRAY_SIZE(stmpe_pwm_resources),
0382 };
0383 
0384 /*
0385  * STMPE801
0386  */
0387 static const u8 stmpe801_regs[] = {
0388     [STMPE_IDX_CHIP_ID] = STMPE801_REG_CHIP_ID,
0389     [STMPE_IDX_ICR_LSB] = STMPE801_REG_SYS_CTRL,
0390     [STMPE_IDX_GPMR_LSB]    = STMPE801_REG_GPIO_MP_STA,
0391     [STMPE_IDX_GPSR_LSB]    = STMPE801_REG_GPIO_SET_PIN,
0392     [STMPE_IDX_GPCR_LSB]    = STMPE801_REG_GPIO_SET_PIN,
0393     [STMPE_IDX_GPDR_LSB]    = STMPE801_REG_GPIO_DIR,
0394     [STMPE_IDX_IEGPIOR_LSB] = STMPE801_REG_GPIO_INT_EN,
0395     [STMPE_IDX_ISGPIOR_MSB] = STMPE801_REG_GPIO_INT_STA,
0396 
0397 };
0398 
0399 static struct stmpe_variant_block stmpe801_blocks[] = {
0400     {
0401         .cell   = &stmpe_gpio_cell,
0402         .irq    = 0,
0403         .block  = STMPE_BLOCK_GPIO,
0404     },
0405 };
0406 
0407 static struct stmpe_variant_block stmpe801_blocks_noirq[] = {
0408     {
0409         .cell   = &stmpe_gpio_cell_noirq,
0410         .block  = STMPE_BLOCK_GPIO,
0411     },
0412 };
0413 
0414 static int stmpe801_enable(struct stmpe *stmpe, unsigned int blocks,
0415                bool enable)
0416 {
0417     if (blocks & STMPE_BLOCK_GPIO)
0418         return 0;
0419     else
0420         return -EINVAL;
0421 }
0422 
0423 static struct stmpe_variant_info stmpe801 = {
0424     .name       = "stmpe801",
0425     .id_val     = STMPE801_ID,
0426     .id_mask    = 0xffff,
0427     .num_gpios  = 8,
0428     .regs       = stmpe801_regs,
0429     .blocks     = stmpe801_blocks,
0430     .num_blocks = ARRAY_SIZE(stmpe801_blocks),
0431     .num_irqs   = STMPE801_NR_INTERNAL_IRQS,
0432     .enable     = stmpe801_enable,
0433 };
0434 
0435 static struct stmpe_variant_info stmpe801_noirq = {
0436     .name       = "stmpe801",
0437     .id_val     = STMPE801_ID,
0438     .id_mask    = 0xffff,
0439     .num_gpios  = 8,
0440     .regs       = stmpe801_regs,
0441     .blocks     = stmpe801_blocks_noirq,
0442     .num_blocks = ARRAY_SIZE(stmpe801_blocks_noirq),
0443     .enable     = stmpe801_enable,
0444 };
0445 
0446 /*
0447  * Touchscreen (STMPE811 or STMPE610)
0448  */
0449 
0450 static struct resource stmpe_ts_resources[] = {
0451     /* Start and end filled dynamically */
0452     {
0453         .name   = "TOUCH_DET",
0454         .flags  = IORESOURCE_IRQ,
0455     },
0456     {
0457         .name   = "FIFO_TH",
0458         .flags  = IORESOURCE_IRQ,
0459     },
0460 };
0461 
0462 static const struct mfd_cell stmpe_ts_cell = {
0463     .name       = "stmpe-ts",
0464     .of_compatible  = "st,stmpe-ts",
0465     .resources  = stmpe_ts_resources,
0466     .num_resources  = ARRAY_SIZE(stmpe_ts_resources),
0467 };
0468 
0469 /*
0470  * ADC (STMPE811)
0471  */
0472 
0473 static struct resource stmpe_adc_resources[] = {
0474     /* Start and end filled dynamically */
0475     {
0476         .name   = "STMPE_TEMP_SENS",
0477         .flags  = IORESOURCE_IRQ,
0478     },
0479     {
0480         .name   = "STMPE_ADC",
0481         .flags  = IORESOURCE_IRQ,
0482     },
0483 };
0484 
0485 static const struct mfd_cell stmpe_adc_cell = {
0486     .name       = "stmpe-adc",
0487     .of_compatible  = "st,stmpe-adc",
0488     .resources  = stmpe_adc_resources,
0489     .num_resources  = ARRAY_SIZE(stmpe_adc_resources),
0490 };
0491 
0492 /*
0493  * STMPE811 or STMPE610
0494  */
0495 
0496 static const u8 stmpe811_regs[] = {
0497     [STMPE_IDX_CHIP_ID] = STMPE811_REG_CHIP_ID,
0498     [STMPE_IDX_SYS_CTRL]    = STMPE811_REG_SYS_CTRL,
0499     [STMPE_IDX_SYS_CTRL2]   = STMPE811_REG_SYS_CTRL2,
0500     [STMPE_IDX_ICR_LSB] = STMPE811_REG_INT_CTRL,
0501     [STMPE_IDX_IER_LSB] = STMPE811_REG_INT_EN,
0502     [STMPE_IDX_ISR_MSB] = STMPE811_REG_INT_STA,
0503     [STMPE_IDX_GPMR_LSB]    = STMPE811_REG_GPIO_MP_STA,
0504     [STMPE_IDX_GPSR_LSB]    = STMPE811_REG_GPIO_SET_PIN,
0505     [STMPE_IDX_GPCR_LSB]    = STMPE811_REG_GPIO_CLR_PIN,
0506     [STMPE_IDX_GPDR_LSB]    = STMPE811_REG_GPIO_DIR,
0507     [STMPE_IDX_GPRER_LSB]   = STMPE811_REG_GPIO_RE,
0508     [STMPE_IDX_GPFER_LSB]   = STMPE811_REG_GPIO_FE,
0509     [STMPE_IDX_GPAFR_U_MSB] = STMPE811_REG_GPIO_AF,
0510     [STMPE_IDX_IEGPIOR_LSB] = STMPE811_REG_GPIO_INT_EN,
0511     [STMPE_IDX_ISGPIOR_MSB] = STMPE811_REG_GPIO_INT_STA,
0512     [STMPE_IDX_GPEDR_LSB]   = STMPE811_REG_GPIO_ED,
0513 };
0514 
0515 static struct stmpe_variant_block stmpe811_blocks[] = {
0516     {
0517         .cell   = &stmpe_gpio_cell,
0518         .irq    = STMPE811_IRQ_GPIOC,
0519         .block  = STMPE_BLOCK_GPIO,
0520     },
0521     {
0522         .cell   = &stmpe_ts_cell,
0523         .irq    = STMPE811_IRQ_TOUCH_DET,
0524         .block  = STMPE_BLOCK_TOUCHSCREEN,
0525     },
0526     {
0527         .cell   = &stmpe_adc_cell,
0528         .irq    = STMPE811_IRQ_TEMP_SENS,
0529         .block  = STMPE_BLOCK_ADC,
0530     },
0531 };
0532 
0533 static int stmpe811_enable(struct stmpe *stmpe, unsigned int blocks,
0534                bool enable)
0535 {
0536     unsigned int mask = 0;
0537 
0538     if (blocks & STMPE_BLOCK_GPIO)
0539         mask |= STMPE811_SYS_CTRL2_GPIO_OFF;
0540 
0541     if (blocks & STMPE_BLOCK_ADC)
0542         mask |= STMPE811_SYS_CTRL2_ADC_OFF;
0543 
0544     if (blocks & STMPE_BLOCK_TOUCHSCREEN)
0545         mask |= STMPE811_SYS_CTRL2_TSC_OFF;
0546 
0547     return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], mask,
0548                 enable ? 0 : mask);
0549 }
0550 
0551 int stmpe811_adc_common_init(struct stmpe *stmpe)
0552 {
0553     int ret;
0554     u8 adc_ctrl1, adc_ctrl1_mask;
0555 
0556     adc_ctrl1 = STMPE_SAMPLE_TIME(stmpe->sample_time) |
0557             STMPE_MOD_12B(stmpe->mod_12b) |
0558             STMPE_REF_SEL(stmpe->ref_sel);
0559     adc_ctrl1_mask = STMPE_SAMPLE_TIME(0xff) | STMPE_MOD_12B(0xff) |
0560              STMPE_REF_SEL(0xff);
0561 
0562     ret = stmpe_set_bits(stmpe, STMPE811_REG_ADC_CTRL1,
0563             adc_ctrl1_mask, adc_ctrl1);
0564     if (ret) {
0565         dev_err(stmpe->dev, "Could not setup ADC\n");
0566         return ret;
0567     }
0568 
0569     ret = stmpe_set_bits(stmpe, STMPE811_REG_ADC_CTRL2,
0570             STMPE_ADC_FREQ(0xff), STMPE_ADC_FREQ(stmpe->adc_freq));
0571     if (ret) {
0572         dev_err(stmpe->dev, "Could not setup ADC\n");
0573         return ret;
0574     }
0575 
0576     return 0;
0577 }
0578 EXPORT_SYMBOL_GPL(stmpe811_adc_common_init);
0579 
0580 static int stmpe811_get_altfunc(struct stmpe *stmpe, enum stmpe_block block)
0581 {
0582     /* 0 for touchscreen, 1 for GPIO */
0583     return block != STMPE_BLOCK_TOUCHSCREEN;
0584 }
0585 
0586 static struct stmpe_variant_info stmpe811 = {
0587     .name       = "stmpe811",
0588     .id_val     = 0x0811,
0589     .id_mask    = 0xffff,
0590     .num_gpios  = 8,
0591     .af_bits    = 1,
0592     .regs       = stmpe811_regs,
0593     .blocks     = stmpe811_blocks,
0594     .num_blocks = ARRAY_SIZE(stmpe811_blocks),
0595     .num_irqs   = STMPE811_NR_INTERNAL_IRQS,
0596     .enable     = stmpe811_enable,
0597     .get_altfunc    = stmpe811_get_altfunc,
0598 };
0599 
0600 /* Similar to 811, except number of gpios */
0601 static struct stmpe_variant_info stmpe610 = {
0602     .name       = "stmpe610",
0603     .id_val     = 0x0811,
0604     .id_mask    = 0xffff,
0605     .num_gpios  = 6,
0606     .af_bits    = 1,
0607     .regs       = stmpe811_regs,
0608     .blocks     = stmpe811_blocks,
0609     .num_blocks = ARRAY_SIZE(stmpe811_blocks),
0610     .num_irqs   = STMPE811_NR_INTERNAL_IRQS,
0611     .enable     = stmpe811_enable,
0612     .get_altfunc    = stmpe811_get_altfunc,
0613 };
0614 
0615 /*
0616  * STMPE1600
0617  * Compared to all others STMPE variant, LSB and MSB regs are located in this
0618  * order :  LSB   addr
0619  *      MSB   addr + 1
0620  * As there is only 2 * 8bits registers for GPMR/GPSR/IEGPIOPR, CSB index is MSB registers
0621  */
0622 
0623 static const u8 stmpe1600_regs[] = {
0624     [STMPE_IDX_CHIP_ID] = STMPE1600_REG_CHIP_ID,
0625     [STMPE_IDX_SYS_CTRL]    = STMPE1600_REG_SYS_CTRL,
0626     [STMPE_IDX_ICR_LSB] = STMPE1600_REG_SYS_CTRL,
0627     [STMPE_IDX_GPMR_LSB]    = STMPE1600_REG_GPMR_LSB,
0628     [STMPE_IDX_GPMR_CSB]    = STMPE1600_REG_GPMR_MSB,
0629     [STMPE_IDX_GPSR_LSB]    = STMPE1600_REG_GPSR_LSB,
0630     [STMPE_IDX_GPSR_CSB]    = STMPE1600_REG_GPSR_MSB,
0631     [STMPE_IDX_GPCR_LSB]    = STMPE1600_REG_GPSR_LSB,
0632     [STMPE_IDX_GPCR_CSB]    = STMPE1600_REG_GPSR_MSB,
0633     [STMPE_IDX_GPDR_LSB]    = STMPE1600_REG_GPDR_LSB,
0634     [STMPE_IDX_GPDR_CSB]    = STMPE1600_REG_GPDR_MSB,
0635     [STMPE_IDX_IEGPIOR_LSB] = STMPE1600_REG_IEGPIOR_LSB,
0636     [STMPE_IDX_IEGPIOR_CSB] = STMPE1600_REG_IEGPIOR_MSB,
0637     [STMPE_IDX_ISGPIOR_LSB] = STMPE1600_REG_ISGPIOR_LSB,
0638 };
0639 
0640 static struct stmpe_variant_block stmpe1600_blocks[] = {
0641     {
0642         .cell   = &stmpe_gpio_cell,
0643         .irq    = 0,
0644         .block  = STMPE_BLOCK_GPIO,
0645     },
0646 };
0647 
0648 static int stmpe1600_enable(struct stmpe *stmpe, unsigned int blocks,
0649                bool enable)
0650 {
0651     if (blocks & STMPE_BLOCK_GPIO)
0652         return 0;
0653     else
0654         return -EINVAL;
0655 }
0656 
0657 static struct stmpe_variant_info stmpe1600 = {
0658     .name       = "stmpe1600",
0659     .id_val     = STMPE1600_ID,
0660     .id_mask    = 0xffff,
0661     .num_gpios  = 16,
0662     .af_bits    = 0,
0663     .regs       = stmpe1600_regs,
0664     .blocks     = stmpe1600_blocks,
0665     .num_blocks = ARRAY_SIZE(stmpe1600_blocks),
0666     .num_irqs   = STMPE1600_NR_INTERNAL_IRQS,
0667     .enable     = stmpe1600_enable,
0668 };
0669 
0670 /*
0671  * STMPE1601
0672  */
0673 
0674 static const u8 stmpe1601_regs[] = {
0675     [STMPE_IDX_CHIP_ID] = STMPE1601_REG_CHIP_ID,
0676     [STMPE_IDX_SYS_CTRL]    = STMPE1601_REG_SYS_CTRL,
0677     [STMPE_IDX_SYS_CTRL2]   = STMPE1601_REG_SYS_CTRL2,
0678     [STMPE_IDX_ICR_LSB] = STMPE1601_REG_ICR_LSB,
0679     [STMPE_IDX_IER_MSB] = STMPE1601_REG_IER_MSB,
0680     [STMPE_IDX_IER_LSB] = STMPE1601_REG_IER_LSB,
0681     [STMPE_IDX_ISR_MSB] = STMPE1601_REG_ISR_MSB,
0682     [STMPE_IDX_GPMR_LSB]    = STMPE1601_REG_GPIO_MP_LSB,
0683     [STMPE_IDX_GPMR_CSB]    = STMPE1601_REG_GPIO_MP_MSB,
0684     [STMPE_IDX_GPSR_LSB]    = STMPE1601_REG_GPIO_SET_LSB,
0685     [STMPE_IDX_GPSR_CSB]    = STMPE1601_REG_GPIO_SET_MSB,
0686     [STMPE_IDX_GPCR_LSB]    = STMPE1601_REG_GPIO_CLR_LSB,
0687     [STMPE_IDX_GPCR_CSB]    = STMPE1601_REG_GPIO_CLR_MSB,
0688     [STMPE_IDX_GPDR_LSB]    = STMPE1601_REG_GPIO_SET_DIR_LSB,
0689     [STMPE_IDX_GPDR_CSB]    = STMPE1601_REG_GPIO_SET_DIR_MSB,
0690     [STMPE_IDX_GPEDR_LSB]   = STMPE1601_REG_GPIO_ED_LSB,
0691     [STMPE_IDX_GPEDR_CSB]   = STMPE1601_REG_GPIO_ED_MSB,
0692     [STMPE_IDX_GPRER_LSB]   = STMPE1601_REG_GPIO_RE_LSB,
0693     [STMPE_IDX_GPRER_CSB]   = STMPE1601_REG_GPIO_RE_MSB,
0694     [STMPE_IDX_GPFER_LSB]   = STMPE1601_REG_GPIO_FE_LSB,
0695     [STMPE_IDX_GPFER_CSB]   = STMPE1601_REG_GPIO_FE_MSB,
0696     [STMPE_IDX_GPPUR_LSB]   = STMPE1601_REG_GPIO_PU_LSB,
0697     [STMPE_IDX_GPAFR_U_MSB] = STMPE1601_REG_GPIO_AF_U_MSB,
0698     [STMPE_IDX_IEGPIOR_LSB] = STMPE1601_REG_INT_EN_GPIO_MASK_LSB,
0699     [STMPE_IDX_IEGPIOR_CSB] = STMPE1601_REG_INT_EN_GPIO_MASK_MSB,
0700     [STMPE_IDX_ISGPIOR_MSB] = STMPE1601_REG_INT_STA_GPIO_MSB,
0701 };
0702 
0703 static struct stmpe_variant_block stmpe1601_blocks[] = {
0704     {
0705         .cell   = &stmpe_gpio_cell,
0706         .irq    = STMPE1601_IRQ_GPIOC,
0707         .block  = STMPE_BLOCK_GPIO,
0708     },
0709     {
0710         .cell   = &stmpe_keypad_cell,
0711         .irq    = STMPE1601_IRQ_KEYPAD,
0712         .block  = STMPE_BLOCK_KEYPAD,
0713     },
0714     {
0715         .cell   = &stmpe_pwm_cell,
0716         .irq    = STMPE1601_IRQ_PWM0,
0717         .block  = STMPE_BLOCK_PWM,
0718     },
0719 };
0720 
0721 /* supported autosleep timeout delay (in msecs) */
0722 static const int stmpe_autosleep_delay[] = {
0723     4, 16, 32, 64, 128, 256, 512, 1024,
0724 };
0725 
0726 static int stmpe_round_timeout(int timeout)
0727 {
0728     int i;
0729 
0730     for (i = 0; i < ARRAY_SIZE(stmpe_autosleep_delay); i++) {
0731         if (stmpe_autosleep_delay[i] >= timeout)
0732             return i;
0733     }
0734 
0735     /*
0736      * requests for delays longer than supported should not return the
0737      * longest supported delay
0738      */
0739     return -EINVAL;
0740 }
0741 
0742 static int stmpe_autosleep(struct stmpe *stmpe, int autosleep_timeout)
0743 {
0744     int ret;
0745 
0746     if (!stmpe->variant->enable_autosleep)
0747         return -ENOSYS;
0748 
0749     mutex_lock(&stmpe->lock);
0750     ret = stmpe->variant->enable_autosleep(stmpe, autosleep_timeout);
0751     mutex_unlock(&stmpe->lock);
0752 
0753     return ret;
0754 }
0755 
0756 /*
0757  * Both stmpe 1601/2403 support same layout for autosleep
0758  */
0759 static int stmpe1601_autosleep(struct stmpe *stmpe,
0760         int autosleep_timeout)
0761 {
0762     int ret, timeout;
0763 
0764     /* choose the best available timeout */
0765     timeout = stmpe_round_timeout(autosleep_timeout);
0766     if (timeout < 0) {
0767         dev_err(stmpe->dev, "invalid timeout\n");
0768         return timeout;
0769     }
0770 
0771     ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2],
0772             STMPE1601_AUTOSLEEP_TIMEOUT_MASK,
0773             timeout);
0774     if (ret < 0)
0775         return ret;
0776 
0777     return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2],
0778             STPME1601_AUTOSLEEP_ENABLE,
0779             STPME1601_AUTOSLEEP_ENABLE);
0780 }
0781 
0782 static int stmpe1601_enable(struct stmpe *stmpe, unsigned int blocks,
0783                 bool enable)
0784 {
0785     unsigned int mask = 0;
0786 
0787     if (blocks & STMPE_BLOCK_GPIO)
0788         mask |= STMPE1601_SYS_CTRL_ENABLE_GPIO;
0789     else
0790         mask &= ~STMPE1601_SYS_CTRL_ENABLE_GPIO;
0791 
0792     if (blocks & STMPE_BLOCK_KEYPAD)
0793         mask |= STMPE1601_SYS_CTRL_ENABLE_KPC;
0794     else
0795         mask &= ~STMPE1601_SYS_CTRL_ENABLE_KPC;
0796 
0797     if (blocks & STMPE_BLOCK_PWM)
0798         mask |= STMPE1601_SYS_CTRL_ENABLE_SPWM;
0799     else
0800         mask &= ~STMPE1601_SYS_CTRL_ENABLE_SPWM;
0801 
0802     return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask,
0803                 enable ? mask : 0);
0804 }
0805 
0806 static int stmpe1601_get_altfunc(struct stmpe *stmpe, enum stmpe_block block)
0807 {
0808     switch (block) {
0809     case STMPE_BLOCK_PWM:
0810         return 2;
0811 
0812     case STMPE_BLOCK_KEYPAD:
0813         return 1;
0814 
0815     case STMPE_BLOCK_GPIO:
0816     default:
0817         return 0;
0818     }
0819 }
0820 
0821 static struct stmpe_variant_info stmpe1601 = {
0822     .name       = "stmpe1601",
0823     .id_val     = 0x0210,
0824     .id_mask    = 0xfff0,   /* at least 0x0210 and 0x0212 */
0825     .num_gpios  = 16,
0826     .af_bits    = 2,
0827     .regs       = stmpe1601_regs,
0828     .blocks     = stmpe1601_blocks,
0829     .num_blocks = ARRAY_SIZE(stmpe1601_blocks),
0830     .num_irqs   = STMPE1601_NR_INTERNAL_IRQS,
0831     .enable     = stmpe1601_enable,
0832     .get_altfunc    = stmpe1601_get_altfunc,
0833     .enable_autosleep   = stmpe1601_autosleep,
0834 };
0835 
0836 /*
0837  * STMPE1801
0838  */
0839 static const u8 stmpe1801_regs[] = {
0840     [STMPE_IDX_CHIP_ID] = STMPE1801_REG_CHIP_ID,
0841     [STMPE_IDX_SYS_CTRL]    = STMPE1801_REG_SYS_CTRL,
0842     [STMPE_IDX_ICR_LSB] = STMPE1801_REG_INT_CTRL_LOW,
0843     [STMPE_IDX_IER_LSB] = STMPE1801_REG_INT_EN_MASK_LOW,
0844     [STMPE_IDX_ISR_LSB] = STMPE1801_REG_INT_STA_LOW,
0845     [STMPE_IDX_GPMR_LSB]    = STMPE1801_REG_GPIO_MP_LOW,
0846     [STMPE_IDX_GPMR_CSB]    = STMPE1801_REG_GPIO_MP_MID,
0847     [STMPE_IDX_GPMR_MSB]    = STMPE1801_REG_GPIO_MP_HIGH,
0848     [STMPE_IDX_GPSR_LSB]    = STMPE1801_REG_GPIO_SET_LOW,
0849     [STMPE_IDX_GPSR_CSB]    = STMPE1801_REG_GPIO_SET_MID,
0850     [STMPE_IDX_GPSR_MSB]    = STMPE1801_REG_GPIO_SET_HIGH,
0851     [STMPE_IDX_GPCR_LSB]    = STMPE1801_REG_GPIO_CLR_LOW,
0852     [STMPE_IDX_GPCR_CSB]    = STMPE1801_REG_GPIO_CLR_MID,
0853     [STMPE_IDX_GPCR_MSB]    = STMPE1801_REG_GPIO_CLR_HIGH,
0854     [STMPE_IDX_GPDR_LSB]    = STMPE1801_REG_GPIO_SET_DIR_LOW,
0855     [STMPE_IDX_GPDR_CSB]    = STMPE1801_REG_GPIO_SET_DIR_MID,
0856     [STMPE_IDX_GPDR_MSB]    = STMPE1801_REG_GPIO_SET_DIR_HIGH,
0857     [STMPE_IDX_GPRER_LSB]   = STMPE1801_REG_GPIO_RE_LOW,
0858     [STMPE_IDX_GPRER_CSB]   = STMPE1801_REG_GPIO_RE_MID,
0859     [STMPE_IDX_GPRER_MSB]   = STMPE1801_REG_GPIO_RE_HIGH,
0860     [STMPE_IDX_GPFER_LSB]   = STMPE1801_REG_GPIO_FE_LOW,
0861     [STMPE_IDX_GPFER_CSB]   = STMPE1801_REG_GPIO_FE_MID,
0862     [STMPE_IDX_GPFER_MSB]   = STMPE1801_REG_GPIO_FE_HIGH,
0863     [STMPE_IDX_GPPUR_LSB]   = STMPE1801_REG_GPIO_PULL_UP_LOW,
0864     [STMPE_IDX_IEGPIOR_LSB] = STMPE1801_REG_INT_EN_GPIO_MASK_LOW,
0865     [STMPE_IDX_IEGPIOR_CSB] = STMPE1801_REG_INT_EN_GPIO_MASK_MID,
0866     [STMPE_IDX_IEGPIOR_MSB] = STMPE1801_REG_INT_EN_GPIO_MASK_HIGH,
0867     [STMPE_IDX_ISGPIOR_MSB] = STMPE1801_REG_INT_STA_GPIO_HIGH,
0868 };
0869 
0870 static struct stmpe_variant_block stmpe1801_blocks[] = {
0871     {
0872         .cell   = &stmpe_gpio_cell,
0873         .irq    = STMPE1801_IRQ_GPIOC,
0874         .block  = STMPE_BLOCK_GPIO,
0875     },
0876     {
0877         .cell   = &stmpe_keypad_cell,
0878         .irq    = STMPE1801_IRQ_KEYPAD,
0879         .block  = STMPE_BLOCK_KEYPAD,
0880     },
0881 };
0882 
0883 static int stmpe1801_enable(struct stmpe *stmpe, unsigned int blocks,
0884                 bool enable)
0885 {
0886     unsigned int mask = 0;
0887     if (blocks & STMPE_BLOCK_GPIO)
0888         mask |= STMPE1801_MSK_INT_EN_GPIO;
0889 
0890     if (blocks & STMPE_BLOCK_KEYPAD)
0891         mask |= STMPE1801_MSK_INT_EN_KPC;
0892 
0893     return __stmpe_set_bits(stmpe, STMPE1801_REG_INT_EN_MASK_LOW, mask,
0894                 enable ? mask : 0);
0895 }
0896 
0897 static int stmpe_reset(struct stmpe *stmpe)
0898 {
0899     u16 id_val = stmpe->variant->id_val;
0900     unsigned long timeout;
0901     int ret = 0;
0902     u8 reset_bit;
0903 
0904     if (id_val == STMPE811_ID)
0905         /* STMPE801 and STMPE610 use bit 1 of SYS_CTRL register */
0906         reset_bit = STMPE811_SYS_CTRL_RESET;
0907     else
0908         /* all other STMPE variant use bit 7 of SYS_CTRL register */
0909         reset_bit = STMPE_SYS_CTRL_RESET;
0910 
0911     ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL],
0912                    reset_bit, reset_bit);
0913     if (ret < 0)
0914         return ret;
0915 
0916     msleep(10);
0917 
0918     timeout = jiffies + msecs_to_jiffies(100);
0919     while (time_before(jiffies, timeout)) {
0920         ret = __stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL]);
0921         if (ret < 0)
0922             return ret;
0923         if (!(ret & reset_bit))
0924             return 0;
0925         usleep_range(100, 200);
0926     }
0927     return -EIO;
0928 }
0929 
0930 static struct stmpe_variant_info stmpe1801 = {
0931     .name       = "stmpe1801",
0932     .id_val     = STMPE1801_ID,
0933     .id_mask    = 0xfff0,
0934     .num_gpios  = 18,
0935     .af_bits    = 0,
0936     .regs       = stmpe1801_regs,
0937     .blocks     = stmpe1801_blocks,
0938     .num_blocks = ARRAY_SIZE(stmpe1801_blocks),
0939     .num_irqs   = STMPE1801_NR_INTERNAL_IRQS,
0940     .enable     = stmpe1801_enable,
0941     /* stmpe1801 do not have any gpio alternate function */
0942     .get_altfunc    = NULL,
0943 };
0944 
0945 /*
0946  * STMPE24XX
0947  */
0948 
0949 static const u8 stmpe24xx_regs[] = {
0950     [STMPE_IDX_CHIP_ID] = STMPE24XX_REG_CHIP_ID,
0951     [STMPE_IDX_SYS_CTRL]    = STMPE24XX_REG_SYS_CTRL,
0952     [STMPE_IDX_SYS_CTRL2]   = STMPE24XX_REG_SYS_CTRL2,
0953     [STMPE_IDX_ICR_LSB] = STMPE24XX_REG_ICR_LSB,
0954     [STMPE_IDX_IER_MSB] = STMPE24XX_REG_IER_MSB,
0955     [STMPE_IDX_IER_LSB] = STMPE24XX_REG_IER_LSB,
0956     [STMPE_IDX_ISR_MSB] = STMPE24XX_REG_ISR_MSB,
0957     [STMPE_IDX_GPMR_LSB]    = STMPE24XX_REG_GPMR_LSB,
0958     [STMPE_IDX_GPMR_CSB]    = STMPE24XX_REG_GPMR_CSB,
0959     [STMPE_IDX_GPMR_MSB]    = STMPE24XX_REG_GPMR_MSB,
0960     [STMPE_IDX_GPSR_LSB]    = STMPE24XX_REG_GPSR_LSB,
0961     [STMPE_IDX_GPSR_CSB]    = STMPE24XX_REG_GPSR_CSB,
0962     [STMPE_IDX_GPSR_MSB]    = STMPE24XX_REG_GPSR_MSB,
0963     [STMPE_IDX_GPCR_LSB]    = STMPE24XX_REG_GPCR_LSB,
0964     [STMPE_IDX_GPCR_CSB]    = STMPE24XX_REG_GPCR_CSB,
0965     [STMPE_IDX_GPCR_MSB]    = STMPE24XX_REG_GPCR_MSB,
0966     [STMPE_IDX_GPDR_LSB]    = STMPE24XX_REG_GPDR_LSB,
0967     [STMPE_IDX_GPDR_CSB]    = STMPE24XX_REG_GPDR_CSB,
0968     [STMPE_IDX_GPDR_MSB]    = STMPE24XX_REG_GPDR_MSB,
0969     [STMPE_IDX_GPRER_LSB]   = STMPE24XX_REG_GPRER_LSB,
0970     [STMPE_IDX_GPRER_CSB]   = STMPE24XX_REG_GPRER_CSB,
0971     [STMPE_IDX_GPRER_MSB]   = STMPE24XX_REG_GPRER_MSB,
0972     [STMPE_IDX_GPFER_LSB]   = STMPE24XX_REG_GPFER_LSB,
0973     [STMPE_IDX_GPFER_CSB]   = STMPE24XX_REG_GPFER_CSB,
0974     [STMPE_IDX_GPFER_MSB]   = STMPE24XX_REG_GPFER_MSB,
0975     [STMPE_IDX_GPPUR_LSB]   = STMPE24XX_REG_GPPUR_LSB,
0976     [STMPE_IDX_GPPDR_LSB]   = STMPE24XX_REG_GPPDR_LSB,
0977     [STMPE_IDX_GPAFR_U_MSB] = STMPE24XX_REG_GPAFR_U_MSB,
0978     [STMPE_IDX_IEGPIOR_LSB] = STMPE24XX_REG_IEGPIOR_LSB,
0979     [STMPE_IDX_IEGPIOR_CSB] = STMPE24XX_REG_IEGPIOR_CSB,
0980     [STMPE_IDX_IEGPIOR_MSB] = STMPE24XX_REG_IEGPIOR_MSB,
0981     [STMPE_IDX_ISGPIOR_MSB] = STMPE24XX_REG_ISGPIOR_MSB,
0982     [STMPE_IDX_GPEDR_LSB]   = STMPE24XX_REG_GPEDR_LSB,
0983     [STMPE_IDX_GPEDR_CSB]   = STMPE24XX_REG_GPEDR_CSB,
0984     [STMPE_IDX_GPEDR_MSB]   = STMPE24XX_REG_GPEDR_MSB,
0985 };
0986 
0987 static struct stmpe_variant_block stmpe24xx_blocks[] = {
0988     {
0989         .cell   = &stmpe_gpio_cell,
0990         .irq    = STMPE24XX_IRQ_GPIOC,
0991         .block  = STMPE_BLOCK_GPIO,
0992     },
0993     {
0994         .cell   = &stmpe_keypad_cell,
0995         .irq    = STMPE24XX_IRQ_KEYPAD,
0996         .block  = STMPE_BLOCK_KEYPAD,
0997     },
0998     {
0999         .cell   = &stmpe_pwm_cell,
1000         .irq    = STMPE24XX_IRQ_PWM0,
1001         .block  = STMPE_BLOCK_PWM,
1002     },
1003 };
1004 
1005 static int stmpe24xx_enable(struct stmpe *stmpe, unsigned int blocks,
1006                 bool enable)
1007 {
1008     unsigned int mask = 0;
1009 
1010     if (blocks & STMPE_BLOCK_GPIO)
1011         mask |= STMPE24XX_SYS_CTRL_ENABLE_GPIO;
1012 
1013     if (blocks & STMPE_BLOCK_KEYPAD)
1014         mask |= STMPE24XX_SYS_CTRL_ENABLE_KPC;
1015 
1016     return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask,
1017                 enable ? mask : 0);
1018 }
1019 
1020 static int stmpe24xx_get_altfunc(struct stmpe *stmpe, enum stmpe_block block)
1021 {
1022     switch (block) {
1023     case STMPE_BLOCK_ROTATOR:
1024         return 2;
1025 
1026     case STMPE_BLOCK_KEYPAD:
1027     case STMPE_BLOCK_PWM:
1028         return 1;
1029 
1030     case STMPE_BLOCK_GPIO:
1031     default:
1032         return 0;
1033     }
1034 }
1035 
1036 static struct stmpe_variant_info stmpe2401 = {
1037     .name       = "stmpe2401",
1038     .id_val     = 0x0101,
1039     .id_mask    = 0xffff,
1040     .num_gpios  = 24,
1041     .af_bits    = 2,
1042     .regs       = stmpe24xx_regs,
1043     .blocks     = stmpe24xx_blocks,
1044     .num_blocks = ARRAY_SIZE(stmpe24xx_blocks),
1045     .num_irqs   = STMPE24XX_NR_INTERNAL_IRQS,
1046     .enable     = stmpe24xx_enable,
1047     .get_altfunc    = stmpe24xx_get_altfunc,
1048 };
1049 
1050 static struct stmpe_variant_info stmpe2403 = {
1051     .name       = "stmpe2403",
1052     .id_val     = 0x0120,
1053     .id_mask    = 0xffff,
1054     .num_gpios  = 24,
1055     .af_bits    = 2,
1056     .regs       = stmpe24xx_regs,
1057     .blocks     = stmpe24xx_blocks,
1058     .num_blocks = ARRAY_SIZE(stmpe24xx_blocks),
1059     .num_irqs   = STMPE24XX_NR_INTERNAL_IRQS,
1060     .enable     = stmpe24xx_enable,
1061     .get_altfunc    = stmpe24xx_get_altfunc,
1062     .enable_autosleep   = stmpe1601_autosleep, /* same as stmpe1601 */
1063 };
1064 
1065 static struct stmpe_variant_info *stmpe_variant_info[STMPE_NBR_PARTS] = {
1066     [STMPE610]  = &stmpe610,
1067     [STMPE801]  = &stmpe801,
1068     [STMPE811]  = &stmpe811,
1069     [STMPE1600] = &stmpe1600,
1070     [STMPE1601] = &stmpe1601,
1071     [STMPE1801] = &stmpe1801,
1072     [STMPE2401] = &stmpe2401,
1073     [STMPE2403] = &stmpe2403,
1074 };
1075 
1076 /*
1077  * These devices can be connected in a 'no-irq' configuration - the irq pin
1078  * is not used and the device cannot interrupt the CPU. Here we only list
1079  * devices which support this configuration - the driver will fail probing
1080  * for any devices not listed here which are configured in this way.
1081  */
1082 static struct stmpe_variant_info *stmpe_noirq_variant_info[STMPE_NBR_PARTS] = {
1083     [STMPE801]  = &stmpe801_noirq,
1084 };
1085 
1086 static irqreturn_t stmpe_irq(int irq, void *data)
1087 {
1088     struct stmpe *stmpe = data;
1089     struct stmpe_variant_info *variant = stmpe->variant;
1090     int num = DIV_ROUND_UP(variant->num_irqs, 8);
1091     u8 israddr;
1092     u8 isr[3];
1093     int ret;
1094     int i;
1095 
1096     if (variant->id_val == STMPE801_ID ||
1097         variant->id_val == STMPE1600_ID) {
1098         int base = irq_find_mapping(stmpe->domain, 0);
1099 
1100         handle_nested_irq(base);
1101         return IRQ_HANDLED;
1102     }
1103 
1104     if (variant->id_val == STMPE1801_ID)
1105         israddr = stmpe->regs[STMPE_IDX_ISR_LSB];
1106     else
1107         israddr = stmpe->regs[STMPE_IDX_ISR_MSB];
1108 
1109     ret = stmpe_block_read(stmpe, israddr, num, isr);
1110     if (ret < 0)
1111         return IRQ_NONE;
1112 
1113     for (i = 0; i < num; i++) {
1114         int bank = num - i - 1;
1115         u8 status = isr[i];
1116         u8 clear;
1117 
1118         status &= stmpe->ier[bank];
1119         if (!status)
1120             continue;
1121 
1122         clear = status;
1123         while (status) {
1124             int bit = __ffs(status);
1125             int line = bank * 8 + bit;
1126             int nestedirq = irq_find_mapping(stmpe->domain, line);
1127 
1128             handle_nested_irq(nestedirq);
1129             status &= ~(1 << bit);
1130         }
1131 
1132         stmpe_reg_write(stmpe, israddr + i, clear);
1133     }
1134 
1135     return IRQ_HANDLED;
1136 }
1137 
1138 static void stmpe_irq_lock(struct irq_data *data)
1139 {
1140     struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
1141 
1142     mutex_lock(&stmpe->irq_lock);
1143 }
1144 
1145 static void stmpe_irq_sync_unlock(struct irq_data *data)
1146 {
1147     struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
1148     struct stmpe_variant_info *variant = stmpe->variant;
1149     int num = DIV_ROUND_UP(variant->num_irqs, 8);
1150     int i;
1151 
1152     for (i = 0; i < num; i++) {
1153         u8 new = stmpe->ier[i];
1154         u8 old = stmpe->oldier[i];
1155 
1156         if (new == old)
1157             continue;
1158 
1159         stmpe->oldier[i] = new;
1160         stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_IER_LSB + i], new);
1161     }
1162 
1163     mutex_unlock(&stmpe->irq_lock);
1164 }
1165 
1166 static void stmpe_irq_mask(struct irq_data *data)
1167 {
1168     struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
1169     int offset = data->hwirq;
1170     int regoffset = offset / 8;
1171     int mask = 1 << (offset % 8);
1172 
1173     stmpe->ier[regoffset] &= ~mask;
1174 }
1175 
1176 static void stmpe_irq_unmask(struct irq_data *data)
1177 {
1178     struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
1179     int offset = data->hwirq;
1180     int regoffset = offset / 8;
1181     int mask = 1 << (offset % 8);
1182 
1183     stmpe->ier[regoffset] |= mask;
1184 }
1185 
1186 static struct irq_chip stmpe_irq_chip = {
1187     .name           = "stmpe",
1188     .irq_bus_lock       = stmpe_irq_lock,
1189     .irq_bus_sync_unlock    = stmpe_irq_sync_unlock,
1190     .irq_mask       = stmpe_irq_mask,
1191     .irq_unmask     = stmpe_irq_unmask,
1192 };
1193 
1194 static int stmpe_irq_map(struct irq_domain *d, unsigned int virq,
1195                                 irq_hw_number_t hwirq)
1196 {
1197     struct stmpe *stmpe = d->host_data;
1198     struct irq_chip *chip = NULL;
1199 
1200     if (stmpe->variant->id_val != STMPE801_ID)
1201         chip = &stmpe_irq_chip;
1202 
1203     irq_set_chip_data(virq, stmpe);
1204     irq_set_chip_and_handler(virq, chip, handle_edge_irq);
1205     irq_set_nested_thread(virq, 1);
1206     irq_set_noprobe(virq);
1207 
1208     return 0;
1209 }
1210 
1211 static void stmpe_irq_unmap(struct irq_domain *d, unsigned int virq)
1212 {
1213         irq_set_chip_and_handler(virq, NULL, NULL);
1214         irq_set_chip_data(virq, NULL);
1215 }
1216 
1217 static const struct irq_domain_ops stmpe_irq_ops = {
1218         .map    = stmpe_irq_map,
1219         .unmap  = stmpe_irq_unmap,
1220         .xlate  = irq_domain_xlate_twocell,
1221 };
1222 
1223 static int stmpe_irq_init(struct stmpe *stmpe, struct device_node *np)
1224 {
1225     int base = 0;
1226     int num_irqs = stmpe->variant->num_irqs;
1227 
1228     stmpe->domain = irq_domain_add_simple(np, num_irqs, base,
1229                           &stmpe_irq_ops, stmpe);
1230     if (!stmpe->domain) {
1231         dev_err(stmpe->dev, "Failed to create irqdomain\n");
1232         return -ENOSYS;
1233     }
1234 
1235     return 0;
1236 }
1237 
1238 static int stmpe_chip_init(struct stmpe *stmpe)
1239 {
1240     unsigned int irq_trigger = stmpe->pdata->irq_trigger;
1241     int autosleep_timeout = stmpe->pdata->autosleep_timeout;
1242     struct stmpe_variant_info *variant = stmpe->variant;
1243     u8 icr = 0;
1244     unsigned int id;
1245     u8 data[2];
1246     int ret;
1247 
1248     ret = stmpe_block_read(stmpe, stmpe->regs[STMPE_IDX_CHIP_ID],
1249                    ARRAY_SIZE(data), data);
1250     if (ret < 0)
1251         return ret;
1252 
1253     id = (data[0] << 8) | data[1];
1254     if ((id & variant->id_mask) != variant->id_val) {
1255         dev_err(stmpe->dev, "unknown chip id: %#x\n", id);
1256         return -EINVAL;
1257     }
1258 
1259     dev_info(stmpe->dev, "%s detected, chip id: %#x\n", variant->name, id);
1260 
1261     /* Disable all modules -- subdrivers should enable what they need. */
1262     ret = stmpe_disable(stmpe, ~0);
1263     if (ret)
1264         return ret;
1265 
1266     ret =  stmpe_reset(stmpe);
1267     if (ret < 0)
1268         return ret;
1269 
1270     if (stmpe->irq >= 0) {
1271         if (id == STMPE801_ID || id == STMPE1600_ID)
1272             icr = STMPE_SYS_CTRL_INT_EN;
1273         else
1274             icr = STMPE_ICR_LSB_GIM;
1275 
1276         /* STMPE801 and STMPE1600 don't support Edge interrupts */
1277         if (id != STMPE801_ID && id != STMPE1600_ID) {
1278             if (irq_trigger == IRQF_TRIGGER_FALLING ||
1279                     irq_trigger == IRQF_TRIGGER_RISING)
1280                 icr |= STMPE_ICR_LSB_EDGE;
1281         }
1282 
1283         if (irq_trigger == IRQF_TRIGGER_RISING ||
1284                 irq_trigger == IRQF_TRIGGER_HIGH) {
1285             if (id == STMPE801_ID || id == STMPE1600_ID)
1286                 icr |= STMPE_SYS_CTRL_INT_HI;
1287             else
1288                 icr |= STMPE_ICR_LSB_HIGH;
1289         }
1290     }
1291 
1292     if (stmpe->pdata->autosleep) {
1293         ret = stmpe_autosleep(stmpe, autosleep_timeout);
1294         if (ret)
1295             return ret;
1296     }
1297 
1298     return stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_ICR_LSB], icr);
1299 }
1300 
1301 static int stmpe_add_device(struct stmpe *stmpe, const struct mfd_cell *cell)
1302 {
1303     return mfd_add_devices(stmpe->dev, stmpe->pdata->id, cell, 1,
1304                    NULL, 0, stmpe->domain);
1305 }
1306 
1307 static int stmpe_devices_init(struct stmpe *stmpe)
1308 {
1309     struct stmpe_variant_info *variant = stmpe->variant;
1310     unsigned int platform_blocks = stmpe->pdata->blocks;
1311     int ret = -EINVAL;
1312     int i, j;
1313 
1314     for (i = 0; i < variant->num_blocks; i++) {
1315         struct stmpe_variant_block *block = &variant->blocks[i];
1316 
1317         if (!(platform_blocks & block->block))
1318             continue;
1319 
1320         for (j = 0; j < block->cell->num_resources; j++) {
1321             struct resource *res =
1322                 (struct resource *) &block->cell->resources[j];
1323 
1324             /* Dynamically fill in a variant's IRQ. */
1325             if (res->flags & IORESOURCE_IRQ)
1326                 res->start = res->end = block->irq + j;
1327         }
1328 
1329         platform_blocks &= ~block->block;
1330         ret = stmpe_add_device(stmpe, block->cell);
1331         if (ret)
1332             return ret;
1333     }
1334 
1335     if (platform_blocks)
1336         dev_warn(stmpe->dev,
1337              "platform wants blocks (%#x) not present on variant",
1338              platform_blocks);
1339 
1340     return ret;
1341 }
1342 
1343 static void stmpe_of_probe(struct stmpe_platform_data *pdata,
1344                struct device_node *np)
1345 {
1346     struct device_node *child;
1347 
1348     pdata->id = of_alias_get_id(np, "stmpe-i2c");
1349     if (pdata->id < 0)
1350         pdata->id = -1;
1351 
1352     pdata->irq_gpio = of_get_named_gpio_flags(np, "irq-gpio", 0,
1353                 &pdata->irq_trigger);
1354     if (gpio_is_valid(pdata->irq_gpio))
1355         pdata->irq_over_gpio = 1;
1356     else
1357         pdata->irq_trigger = IRQF_TRIGGER_NONE;
1358 
1359     of_property_read_u32(np, "st,autosleep-timeout",
1360             &pdata->autosleep_timeout);
1361 
1362     pdata->autosleep = (pdata->autosleep_timeout) ? true : false;
1363 
1364     for_each_available_child_of_node(np, child) {
1365         if (of_node_name_eq(child, "stmpe_gpio")) {
1366             pdata->blocks |= STMPE_BLOCK_GPIO;
1367         } else if (of_node_name_eq(child, "stmpe_keypad")) {
1368             pdata->blocks |= STMPE_BLOCK_KEYPAD;
1369         } else if (of_node_name_eq(child, "stmpe_touchscreen")) {
1370             pdata->blocks |= STMPE_BLOCK_TOUCHSCREEN;
1371         } else if (of_node_name_eq(child, "stmpe_adc")) {
1372             pdata->blocks |= STMPE_BLOCK_ADC;
1373         } else if (of_node_name_eq(child, "stmpe_pwm")) {
1374             pdata->blocks |= STMPE_BLOCK_PWM;
1375         } else if (of_node_name_eq(child, "stmpe_rotator")) {
1376             pdata->blocks |= STMPE_BLOCK_ROTATOR;
1377         }
1378     }
1379 }
1380 
1381 /* Called from client specific probe routines */
1382 int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum)
1383 {
1384     struct stmpe_platform_data *pdata;
1385     struct device_node *np = ci->dev->of_node;
1386     struct stmpe *stmpe;
1387     int ret;
1388     u32 val;
1389 
1390     pdata = devm_kzalloc(ci->dev, sizeof(*pdata), GFP_KERNEL);
1391     if (!pdata)
1392         return -ENOMEM;
1393 
1394     stmpe_of_probe(pdata, np);
1395 
1396     if (of_find_property(np, "interrupts", NULL) == NULL)
1397         ci->irq = -1;
1398 
1399     stmpe = devm_kzalloc(ci->dev, sizeof(struct stmpe), GFP_KERNEL);
1400     if (!stmpe)
1401         return -ENOMEM;
1402 
1403     mutex_init(&stmpe->irq_lock);
1404     mutex_init(&stmpe->lock);
1405 
1406     if (!of_property_read_u32(np, "st,sample-time", &val))
1407         stmpe->sample_time = val;
1408     if (!of_property_read_u32(np, "st,mod-12b", &val))
1409         stmpe->mod_12b = val;
1410     if (!of_property_read_u32(np, "st,ref-sel", &val))
1411         stmpe->ref_sel = val;
1412     if (!of_property_read_u32(np, "st,adc-freq", &val))
1413         stmpe->adc_freq = val;
1414 
1415     stmpe->dev = ci->dev;
1416     stmpe->client = ci->client;
1417     stmpe->pdata = pdata;
1418     stmpe->ci = ci;
1419     stmpe->partnum = partnum;
1420     stmpe->variant = stmpe_variant_info[partnum];
1421     stmpe->regs = stmpe->variant->regs;
1422     stmpe->num_gpios = stmpe->variant->num_gpios;
1423     stmpe->vcc = devm_regulator_get_optional(ci->dev, "vcc");
1424     if (!IS_ERR(stmpe->vcc)) {
1425         ret = regulator_enable(stmpe->vcc);
1426         if (ret)
1427             dev_warn(ci->dev, "failed to enable VCC supply\n");
1428     }
1429     stmpe->vio = devm_regulator_get_optional(ci->dev, "vio");
1430     if (!IS_ERR(stmpe->vio)) {
1431         ret = regulator_enable(stmpe->vio);
1432         if (ret)
1433             dev_warn(ci->dev, "failed to enable VIO supply\n");
1434     }
1435     dev_set_drvdata(stmpe->dev, stmpe);
1436 
1437     if (ci->init)
1438         ci->init(stmpe);
1439 
1440     if (pdata->irq_over_gpio) {
1441         ret = devm_gpio_request_one(ci->dev, pdata->irq_gpio,
1442                 GPIOF_DIR_IN, "stmpe");
1443         if (ret) {
1444             dev_err(stmpe->dev, "failed to request IRQ GPIO: %d\n",
1445                     ret);
1446             return ret;
1447         }
1448 
1449         stmpe->irq = gpio_to_irq(pdata->irq_gpio);
1450     } else {
1451         stmpe->irq = ci->irq;
1452     }
1453 
1454     if (stmpe->irq < 0) {
1455         /* use alternate variant info for no-irq mode, if supported */
1456         dev_info(stmpe->dev,
1457             "%s configured in no-irq mode by platform data\n",
1458             stmpe->variant->name);
1459         if (!stmpe_noirq_variant_info[stmpe->partnum]) {
1460             dev_err(stmpe->dev,
1461                 "%s does not support no-irq mode!\n",
1462                 stmpe->variant->name);
1463             return -ENODEV;
1464         }
1465         stmpe->variant = stmpe_noirq_variant_info[stmpe->partnum];
1466     } else if (pdata->irq_trigger == IRQF_TRIGGER_NONE) {
1467         pdata->irq_trigger = irq_get_trigger_type(stmpe->irq);
1468     }
1469 
1470     ret = stmpe_chip_init(stmpe);
1471     if (ret)
1472         return ret;
1473 
1474     if (stmpe->irq >= 0) {
1475         ret = stmpe_irq_init(stmpe, np);
1476         if (ret)
1477             return ret;
1478 
1479         ret = devm_request_threaded_irq(ci->dev, stmpe->irq, NULL,
1480                 stmpe_irq, pdata->irq_trigger | IRQF_ONESHOT,
1481                 "stmpe", stmpe);
1482         if (ret) {
1483             dev_err(stmpe->dev, "failed to request IRQ: %d\n",
1484                     ret);
1485             return ret;
1486         }
1487     }
1488 
1489     ret = stmpe_devices_init(stmpe);
1490     if (!ret)
1491         return 0;
1492 
1493     dev_err(stmpe->dev, "failed to add children\n");
1494     mfd_remove_devices(stmpe->dev);
1495 
1496     return ret;
1497 }
1498 
1499 void stmpe_remove(struct stmpe *stmpe)
1500 {
1501     if (!IS_ERR(stmpe->vio))
1502         regulator_disable(stmpe->vio);
1503     if (!IS_ERR(stmpe->vcc))
1504         regulator_disable(stmpe->vcc);
1505 
1506     __stmpe_disable(stmpe, STMPE_BLOCK_ADC);
1507 
1508     mfd_remove_devices(stmpe->dev);
1509 }
1510 
1511 #ifdef CONFIG_PM
1512 static int stmpe_suspend(struct device *dev)
1513 {
1514     struct stmpe *stmpe = dev_get_drvdata(dev);
1515 
1516     if (stmpe->irq >= 0 && device_may_wakeup(dev))
1517         enable_irq_wake(stmpe->irq);
1518 
1519     return 0;
1520 }
1521 
1522 static int stmpe_resume(struct device *dev)
1523 {
1524     struct stmpe *stmpe = dev_get_drvdata(dev);
1525 
1526     if (stmpe->irq >= 0 && device_may_wakeup(dev))
1527         disable_irq_wake(stmpe->irq);
1528 
1529     return 0;
1530 }
1531 
1532 const struct dev_pm_ops stmpe_dev_pm_ops = {
1533     .suspend    = stmpe_suspend,
1534     .resume     = stmpe_resume,
1535 };
1536 #endif
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