drivers/mfd/stm32-timers.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) STMicroelectronics 2016
0004  * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
0005  */
0006
0007 #include <linux/bitfield.h>
0008 #include <linux/mfd/stm32-timers.h>
0009 #include <linux/module.h>
0010 #include <linux/of_platform.h>
0011 #include <linux/reset.h>
0012
0013 #define STM32_TIMERS_MAX_REGISTERS  0x3fc
0014
0015 /* DIER register DMA enable bits */
0016 static const u32 stm32_timers_dier_dmaen[STM32_TIMERS_MAX_DMAS] = {
0017     TIM_DIER_CC1DE,
0018     TIM_DIER_CC2DE,
0019     TIM_DIER_CC3DE,
0020     TIM_DIER_CC4DE,
0021     TIM_DIER_UIE,
0022     TIM_DIER_TDE,
0023     TIM_DIER_COMDE
0024 };
0025
0026 static void stm32_timers_dma_done(void *p)
0027 {
0028     struct stm32_timers_dma *dma = p;
0029     struct dma_tx_state state;
0030     enum dma_status status;
0031
0032     status = dmaengine_tx_status(dma->chan, dma->chan->cookie, &state);
0033     if (status == DMA_COMPLETE)
0034         complete(&dma->completion);
0035 }
0036
0037 /**
0038  * stm32_timers_dma_burst_read - Read from timers registers using DMA.
0039  *
0040  * Read from STM32 timers registers using DMA on a single event.
0041  * @dev: reference to stm32_timers MFD device
0042  * @buf: DMA'able destination buffer
0043  * @id: stm32_timers_dmas event identifier (ch[1..4], up, trig or com)
0044  * @reg: registers start offset for DMA to read from (like CCRx for capture)
0045  * @num_reg: number of registers to read upon each DMA request, starting @reg.
0046  * @bursts: number of bursts to read (e.g. like two for pwm period capture)
0047  * @tmo_ms: timeout (milliseconds)
0048  */
0049 int stm32_timers_dma_burst_read(struct device *dev, u32 *buf,
0050                 enum stm32_timers_dmas id, u32 reg,
0051                 unsigned int num_reg, unsigned int bursts,
0052                 unsigned long tmo_ms)
0053 {
0054     struct stm32_timers *ddata = dev_get_drvdata(dev);
0055     unsigned long timeout = msecs_to_jiffies(tmo_ms);
0056     struct regmap *regmap = ddata->regmap;
0057     struct stm32_timers_dma *dma = &ddata->dma;
0058     size_t len = num_reg * bursts * sizeof(u32);
0059     struct dma_async_tx_descriptor *desc;
0060     struct dma_slave_config config;
0061     dma_cookie_t cookie;
0062     dma_addr_t dma_buf;
0063     u32 dbl, dba;
0064     long err;
0065     int ret;
0066
0067     /* Sanity check */
0068     if (id < STM32_TIMERS_DMA_CH1 || id >= STM32_TIMERS_MAX_DMAS)
0069         return -EINVAL;
0070
0071     if (!num_reg || !bursts || reg > STM32_TIMERS_MAX_REGISTERS ||
0072         (reg + num_reg * sizeof(u32)) > STM32_TIMERS_MAX_REGISTERS)
0073         return -EINVAL;
0074
0075     if (!dma->chans[id])
0076         return -ENODEV;
0077     mutex_lock(&dma->lock);
0078
0079     /* Select DMA channel in use */
0080     dma->chan = dma->chans[id];
0081     dma_buf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
0082     if (dma_mapping_error(dev, dma_buf)) {
0083         ret = -ENOMEM;
0084         goto unlock;
0085     }
0086
0087     /* Prepare DMA read from timer registers, using DMA burst mode */
0088     memset(&config, 0, sizeof(config));
0089     config.src_addr = (dma_addr_t)dma->phys_base + TIM_DMAR;
0090     config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0091     ret = dmaengine_slave_config(dma->chan, &config);
0092     if (ret)
0093         goto unmap;
0094
0095     desc = dmaengine_prep_slave_single(dma->chan, dma_buf, len,
0096                        DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
0097     if (!desc) {
0098         ret = -EBUSY;
0099         goto unmap;
0100     }
0101
0102     desc->callback = stm32_timers_dma_done;
0103     desc->callback_param = dma;
0104     cookie = dmaengine_submit(desc);
0105     ret = dma_submit_error(cookie);
0106     if (ret)
0107         goto dma_term;
0108
0109     reinit_completion(&dma->completion);
0110     dma_async_issue_pending(dma->chan);
0111
0112     /* Setup and enable timer DMA burst mode */
0113     dbl = FIELD_PREP(TIM_DCR_DBL, bursts - 1);
0114     dba = FIELD_PREP(TIM_DCR_DBA, reg >> 2);
0115     ret = regmap_write(regmap, TIM_DCR, dbl | dba);
0116     if (ret)
0117         goto dma_term;
0118
0119     /* Clear pending flags before enabling DMA request */
0120     ret = regmap_write(regmap, TIM_SR, 0);
0121     if (ret)
0122         goto dcr_clr;
0123
0124     ret = regmap_update_bits(regmap, TIM_DIER, stm32_timers_dier_dmaen[id],
0125                  stm32_timers_dier_dmaen[id]);
0126     if (ret)
0127         goto dcr_clr;
0128
0129     err = wait_for_completion_interruptible_timeout(&dma->completion,
0130                             timeout);
0131     if (err == 0)
0132         ret = -ETIMEDOUT;
0133     else if (err < 0)
0134         ret = err;
0135
0136     regmap_update_bits(regmap, TIM_DIER, stm32_timers_dier_dmaen[id], 0);
0137     regmap_write(regmap, TIM_SR, 0);
0138 dcr_clr:
0139     regmap_write(regmap, TIM_DCR, 0);
0140 dma_term:
0141     dmaengine_terminate_all(dma->chan);
0142 unmap:
0143     dma_unmap_single(dev, dma_buf, len, DMA_FROM_DEVICE);
0144 unlock:
0145     dma->chan = NULL;
0146     mutex_unlock(&dma->lock);
0147
0148     return ret;
0149 }
0150 EXPORT_SYMBOL_GPL(stm32_timers_dma_burst_read);
0151
0152 static const struct regmap_config stm32_timers_regmap_cfg = {
0153     .reg_bits = 32,
0154     .val_bits = 32,
0155     .reg_stride = sizeof(u32),
0156     .max_register = STM32_TIMERS_MAX_REGISTERS,
0157 };
0158
0159 static void stm32_timers_get_arr_size(struct stm32_timers *ddata)
0160 {
0161     u32 arr;
0162
0163     /* Backup ARR to restore it after getting the maximum value */
0164     regmap_read(ddata->regmap, TIM_ARR, &arr);
0165
0166     /*
0167      * Only the available bits will be written so when readback
0168      * we get the maximum value of auto reload register
0169      */
0170     regmap_write(ddata->regmap, TIM_ARR, ~0L);
0171     regmap_read(ddata->regmap, TIM_ARR, &ddata->max_arr);
0172     regmap_write(ddata->regmap, TIM_ARR, arr);
0173 }
0174
0175 static int stm32_timers_dma_probe(struct device *dev,
0176                    struct stm32_timers *ddata)
0177 {
0178     int i;
0179     int ret = 0;
0180     char name[4];
0181
0182     init_completion(&ddata->dma.completion);
0183     mutex_init(&ddata->dma.lock);
0184
0185     /* Optional DMA support: get valid DMA channel(s) or NULL */
0186     for (i = STM32_TIMERS_DMA_CH1; i <= STM32_TIMERS_DMA_CH4; i++) {
0187         snprintf(name, ARRAY_SIZE(name), "ch%1d", i + 1);
0188         ddata->dma.chans[i] = dma_request_chan(dev, name);
0189     }
0190     ddata->dma.chans[STM32_TIMERS_DMA_UP] = dma_request_chan(dev, "up");
0191     ddata->dma.chans[STM32_TIMERS_DMA_TRIG] = dma_request_chan(dev, "trig");
0192     ddata->dma.chans[STM32_TIMERS_DMA_COM] = dma_request_chan(dev, "com");
0193
0194     for (i = STM32_TIMERS_DMA_CH1; i < STM32_TIMERS_MAX_DMAS; i++) {
0195         if (IS_ERR(ddata->dma.chans[i])) {
0196             /* Save the first error code to return */
0197             if (PTR_ERR(ddata->dma.chans[i]) != -ENODEV && !ret)
0198                 ret = PTR_ERR(ddata->dma.chans[i]);
0199
0200             ddata->dma.chans[i] = NULL;
0201         }
0202     }
0203
0204     return ret;
0205 }
0206
0207 static void stm32_timers_dma_remove(struct device *dev,
0208                     struct stm32_timers *ddata)
0209 {
0210     int i;
0211
0212     for (i = STM32_TIMERS_DMA_CH1; i < STM32_TIMERS_MAX_DMAS; i++)
0213         if (ddata->dma.chans[i])
0214             dma_release_channel(ddata->dma.chans[i]);
0215 }
0216
0217 static int stm32_timers_probe(struct platform_device *pdev)
0218 {
0219     struct device *dev = &pdev->dev;
0220     struct stm32_timers *ddata;
0221     struct resource *res;
0222     void __iomem *mmio;
0223     int ret;
0224
0225     ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
0226     if (!ddata)
0227         return -ENOMEM;
0228
0229     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0230     mmio = devm_ioremap_resource(dev, res);
0231     if (IS_ERR(mmio))
0232         return PTR_ERR(mmio);
0233
0234     /* Timer physical addr for DMA */
0235     ddata->dma.phys_base = res->start;
0236
0237     ddata->regmap = devm_regmap_init_mmio_clk(dev, "int", mmio,
0238                           &stm32_timers_regmap_cfg);
0239     if (IS_ERR(ddata->regmap))
0240         return PTR_ERR(ddata->regmap);
0241
0242     ddata->clk = devm_clk_get(dev, NULL);
0243     if (IS_ERR(ddata->clk))
0244         return PTR_ERR(ddata->clk);
0245
0246     stm32_timers_get_arr_size(ddata);
0247
0248     ret = stm32_timers_dma_probe(dev, ddata);
0249     if (ret) {
0250         stm32_timers_dma_remove(dev, ddata);
0251         return ret;
0252     }
0253
0254     platform_set_drvdata(pdev, ddata);
0255
0256     ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
0257     if (ret)
0258         stm32_timers_dma_remove(dev, ddata);
0259
0260     return ret;
0261 }
0262
0263 static int stm32_timers_remove(struct platform_device *pdev)
0264 {
0265     struct stm32_timers *ddata = platform_get_drvdata(pdev);
0266
0267     /*
0268      * Don't use devm_ here: enfore of_platform_depopulate() happens before
0269      * DMA are released, to avoid race on DMA.
0270      */
0271     of_platform_depopulate(&pdev->dev);
0272     stm32_timers_dma_remove(&pdev->dev, ddata);
0273
0274     return 0;
0275 }
0276
0277 static const struct of_device_id stm32_timers_of_match[] = {
0278     { .compatible = "st,stm32-timers", },
0279     { /* end node */ },
0280 };
0281 MODULE_DEVICE_TABLE(of, stm32_timers_of_match);
0282
0283 static struct platform_driver stm32_timers_driver = {
0284     .probe = stm32_timers_probe,
0285     .remove = stm32_timers_remove,
0286     .driver = {
0287         .name = "stm32-timers",
0288         .of_match_table = stm32_timers_of_match,
0289     },
0290 };
0291 module_platform_driver(stm32_timers_driver);
0292
0293 MODULE_DESCRIPTION("STMicroelectronics STM32 Timers");
0294 MODULE_LICENSE("GPL v2");