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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * STA2x11 mfd for GPIO, SCTL and APBREG
0004  *
0005  * Copyright (c) 2009-2011 Wind River Systems, Inc.
0006  * Copyright (c) 2011 ST Microelectronics (Alessandro Rubini, Davide Ciminaghi)
0007  */
0008 
0009 #include <linux/kernel.h>
0010 #include <linux/init.h>
0011 #include <linux/export.h>
0012 #include <linux/spinlock.h>
0013 #include <linux/errno.h>
0014 #include <linux/device.h>
0015 #include <linux/slab.h>
0016 #include <linux/list.h>
0017 #include <linux/io.h>
0018 #include <linux/ioport.h>
0019 #include <linux/pci.h>
0020 #include <linux/seq_file.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/mfd/core.h>
0023 #include <linux/mfd/sta2x11-mfd.h>
0024 #include <linux/regmap.h>
0025 
0026 #include <asm/sta2x11.h>
0027 
0028 static inline int __reg_within_range(unsigned int r,
0029                      unsigned int start,
0030                      unsigned int end)
0031 {
0032     return ((r >= start) && (r <= end));
0033 }
0034 
0035 /* This describes STA2X11 MFD chip for us, we may have several */
0036 struct sta2x11_mfd {
0037     struct sta2x11_instance *instance;
0038     struct regmap *regmap[sta2x11_n_mfd_plat_devs];
0039     spinlock_t lock[sta2x11_n_mfd_plat_devs];
0040     struct list_head list;
0041     void __iomem *regs[sta2x11_n_mfd_plat_devs];
0042 };
0043 
0044 static LIST_HEAD(sta2x11_mfd_list);
0045 
0046 /* Three functions to act on the list */
0047 static struct sta2x11_mfd *sta2x11_mfd_find(struct pci_dev *pdev)
0048 {
0049     struct sta2x11_instance *instance;
0050     struct sta2x11_mfd *mfd;
0051 
0052     if (!pdev && !list_empty(&sta2x11_mfd_list)) {
0053         pr_warn("%s: Unspecified device, using first instance\n",
0054             __func__);
0055         return list_entry(sta2x11_mfd_list.next,
0056                   struct sta2x11_mfd, list);
0057     }
0058 
0059     instance = sta2x11_get_instance(pdev);
0060     if (!instance)
0061         return NULL;
0062     list_for_each_entry(mfd, &sta2x11_mfd_list, list) {
0063         if (mfd->instance == instance)
0064             return mfd;
0065     }
0066     return NULL;
0067 }
0068 
0069 static int sta2x11_mfd_add(struct pci_dev *pdev, gfp_t flags)
0070 {
0071     int i;
0072     struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);
0073     struct sta2x11_instance *instance;
0074 
0075     if (mfd)
0076         return -EBUSY;
0077     instance = sta2x11_get_instance(pdev);
0078     if (!instance)
0079         return -EINVAL;
0080     mfd = kzalloc(sizeof(*mfd), flags);
0081     if (!mfd)
0082         return -ENOMEM;
0083     INIT_LIST_HEAD(&mfd->list);
0084     for (i = 0; i < ARRAY_SIZE(mfd->lock); i++)
0085         spin_lock_init(&mfd->lock[i]);
0086     mfd->instance = instance;
0087     list_add(&mfd->list, &sta2x11_mfd_list);
0088     return 0;
0089 }
0090 
0091 /* This function is exported and is not expected to fail */
0092 u32 __sta2x11_mfd_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val,
0093                enum sta2x11_mfd_plat_dev index)
0094 {
0095     struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);
0096     u32 r;
0097     unsigned long flags;
0098     void __iomem *regs;
0099 
0100     if (!mfd) {
0101         dev_warn(&pdev->dev, ": can't access sctl regs\n");
0102         return 0;
0103     }
0104 
0105     regs = mfd->regs[index];
0106     if (!regs) {
0107         dev_warn(&pdev->dev, ": system ctl not initialized\n");
0108         return 0;
0109     }
0110     spin_lock_irqsave(&mfd->lock[index], flags);
0111     r = readl(regs + reg);
0112     r &= ~mask;
0113     r |= val;
0114     if (mask)
0115         writel(r, regs + reg);
0116     spin_unlock_irqrestore(&mfd->lock[index], flags);
0117     return r;
0118 }
0119 EXPORT_SYMBOL(__sta2x11_mfd_mask);
0120 
0121 int sta2x11_mfd_get_regs_data(struct platform_device *dev,
0122                   enum sta2x11_mfd_plat_dev index,
0123                   void __iomem **regs,
0124                   spinlock_t **lock)
0125 {
0126     struct pci_dev *pdev = *(struct pci_dev **)dev_get_platdata(&dev->dev);
0127     struct sta2x11_mfd *mfd;
0128 
0129     if (!pdev)
0130         return -ENODEV;
0131     mfd = sta2x11_mfd_find(pdev);
0132     if (!mfd)
0133         return -ENODEV;
0134     if (index >= sta2x11_n_mfd_plat_devs)
0135         return -ENODEV;
0136     *regs = mfd->regs[index];
0137     *lock = &mfd->lock[index];
0138     pr_debug("%s %d *regs = %p\n", __func__, __LINE__, *regs);
0139     return *regs ? 0 : -ENODEV;
0140 }
0141 EXPORT_SYMBOL(sta2x11_mfd_get_regs_data);
0142 
0143 /*
0144  * Special sta2x11-mfd regmap lock/unlock functions
0145  */
0146 
0147 static void sta2x11_regmap_lock(void *__lock)
0148 {
0149     spinlock_t *lock = __lock;
0150     spin_lock(lock);
0151 }
0152 
0153 static void sta2x11_regmap_unlock(void *__lock)
0154 {
0155     spinlock_t *lock = __lock;
0156     spin_unlock(lock);
0157 }
0158 
0159 /* OTP (one time programmable registers do not require locking */
0160 static void sta2x11_regmap_nolock(void *__lock)
0161 {
0162 }
0163 
0164 static const char *sta2x11_mfd_names[sta2x11_n_mfd_plat_devs] = {
0165     [sta2x11_sctl] = STA2X11_MFD_SCTL_NAME,
0166     [sta2x11_apbreg] = STA2X11_MFD_APBREG_NAME,
0167     [sta2x11_apb_soc_regs] = STA2X11_MFD_APB_SOC_REGS_NAME,
0168     [sta2x11_scr] = STA2X11_MFD_SCR_NAME,
0169 };
0170 
0171 static bool sta2x11_sctl_writeable_reg(struct device *dev, unsigned int reg)
0172 {
0173     return !__reg_within_range(reg, SCTL_SCPCIECSBRST, SCTL_SCRSTSTA);
0174 }
0175 
0176 static struct regmap_config sta2x11_sctl_regmap_config = {
0177     .reg_bits = 32,
0178     .reg_stride = 4,
0179     .val_bits = 32,
0180     .lock = sta2x11_regmap_lock,
0181     .unlock = sta2x11_regmap_unlock,
0182     .max_register = SCTL_SCRSTSTA,
0183     .writeable_reg = sta2x11_sctl_writeable_reg,
0184 };
0185 
0186 static bool sta2x11_scr_readable_reg(struct device *dev, unsigned int reg)
0187 {
0188     return (reg == STA2X11_SECR_CR) ||
0189         __reg_within_range(reg, STA2X11_SECR_FVR0, STA2X11_SECR_FVR1);
0190 }
0191 
0192 static bool sta2x11_scr_writeable_reg(struct device *dev, unsigned int reg)
0193 {
0194     return false;
0195 }
0196 
0197 static struct regmap_config sta2x11_scr_regmap_config = {
0198     .reg_bits = 32,
0199     .reg_stride = 4,
0200     .val_bits = 32,
0201     .lock = sta2x11_regmap_nolock,
0202     .unlock = sta2x11_regmap_nolock,
0203     .max_register = STA2X11_SECR_FVR1,
0204     .readable_reg = sta2x11_scr_readable_reg,
0205     .writeable_reg = sta2x11_scr_writeable_reg,
0206 };
0207 
0208 static bool sta2x11_apbreg_readable_reg(struct device *dev, unsigned int reg)
0209 {
0210     /* Two blocks (CAN and MLB, SARAC) 0x100 bytes apart */
0211     if (reg >= APBREG_BSR_SARAC)
0212         reg -= APBREG_BSR_SARAC;
0213     switch (reg) {
0214     case APBREG_BSR:
0215     case APBREG_PAER:
0216     case APBREG_PWAC:
0217     case APBREG_PRAC:
0218     case APBREG_PCG:
0219     case APBREG_PUR:
0220     case APBREG_EMU_PCG:
0221         return true;
0222     default:
0223         return false;
0224     }
0225 }
0226 
0227 static bool sta2x11_apbreg_writeable_reg(struct device *dev, unsigned int reg)
0228 {
0229     if (reg >= APBREG_BSR_SARAC)
0230         reg -= APBREG_BSR_SARAC;
0231     if (!sta2x11_apbreg_readable_reg(dev, reg))
0232         return false;
0233     return reg != APBREG_PAER;
0234 }
0235 
0236 static struct regmap_config sta2x11_apbreg_regmap_config = {
0237     .reg_bits = 32,
0238     .reg_stride = 4,
0239     .val_bits = 32,
0240     .lock = sta2x11_regmap_lock,
0241     .unlock = sta2x11_regmap_unlock,
0242     .max_register = APBREG_EMU_PCG_SARAC,
0243     .readable_reg = sta2x11_apbreg_readable_reg,
0244     .writeable_reg = sta2x11_apbreg_writeable_reg,
0245 };
0246 
0247 static bool sta2x11_apb_soc_regs_readable_reg(struct device *dev,
0248                           unsigned int reg)
0249 {
0250     return reg <= PCIE_SoC_INT_ROUTER_STATUS3_REG ||
0251         __reg_within_range(reg, DMA_IP_CTRL_REG, SPARE3_RESERVED) ||
0252         __reg_within_range(reg, MASTER_LOCK_REG,
0253                    SYSTEM_CONFIG_STATUS_REG) ||
0254         reg == MSP_CLK_CTRL_REG ||
0255         __reg_within_range(reg, COMPENSATION_REG1, TEST_CTL_REG);
0256 }
0257 
0258 static bool sta2x11_apb_soc_regs_writeable_reg(struct device *dev,
0259                            unsigned int reg)
0260 {
0261     if (!sta2x11_apb_soc_regs_readable_reg(dev, reg))
0262         return false;
0263     switch (reg) {
0264     case PCIE_COMMON_CLOCK_CONFIG_0_4_0:
0265     case SYSTEM_CONFIG_STATUS_REG:
0266     case COMPENSATION_REG1:
0267     case PCIE_SoC_INT_ROUTER_STATUS0_REG...PCIE_SoC_INT_ROUTER_STATUS3_REG:
0268     case PCIE_PM_STATUS_0_PORT_0_4...PCIE_PM_STATUS_7_0_EP4:
0269         return false;
0270     default:
0271         return true;
0272     }
0273 }
0274 
0275 static struct regmap_config sta2x11_apb_soc_regs_regmap_config = {
0276     .reg_bits = 32,
0277     .reg_stride = 4,
0278     .val_bits = 32,
0279     .lock = sta2x11_regmap_lock,
0280     .unlock = sta2x11_regmap_unlock,
0281     .max_register = TEST_CTL_REG,
0282     .readable_reg = sta2x11_apb_soc_regs_readable_reg,
0283     .writeable_reg = sta2x11_apb_soc_regs_writeable_reg,
0284 };
0285 
0286 static struct regmap_config *
0287 sta2x11_mfd_regmap_configs[sta2x11_n_mfd_plat_devs] = {
0288     [sta2x11_sctl] = &sta2x11_sctl_regmap_config,
0289     [sta2x11_apbreg] = &sta2x11_apbreg_regmap_config,
0290     [sta2x11_apb_soc_regs] = &sta2x11_apb_soc_regs_regmap_config,
0291     [sta2x11_scr] = &sta2x11_scr_regmap_config,
0292 };
0293 
0294 /* Probe for the four platform devices */
0295 
0296 static int sta2x11_mfd_platform_probe(struct platform_device *dev,
0297                       enum sta2x11_mfd_plat_dev index)
0298 {
0299     struct pci_dev **pdev;
0300     struct sta2x11_mfd *mfd;
0301     struct resource *res;
0302     const char *name = sta2x11_mfd_names[index];
0303     struct regmap_config *regmap_config = sta2x11_mfd_regmap_configs[index];
0304 
0305     pdev = dev_get_platdata(&dev->dev);
0306     mfd = sta2x11_mfd_find(*pdev);
0307     if (!mfd)
0308         return -ENODEV;
0309     if (!regmap_config)
0310         return -ENODEV;
0311 
0312     res = platform_get_resource(dev, IORESOURCE_MEM, 0);
0313     if (!res)
0314         return -ENOMEM;
0315 
0316     if (!request_mem_region(res->start, resource_size(res), name))
0317         return -EBUSY;
0318 
0319     mfd->regs[index] = ioremap(res->start, resource_size(res));
0320     if (!mfd->regs[index]) {
0321         release_mem_region(res->start, resource_size(res));
0322         return -ENOMEM;
0323     }
0324     regmap_config->lock_arg = &mfd->lock;
0325     /*
0326        No caching, registers could be reached both via regmap and via
0327        void __iomem *
0328     */
0329     regmap_config->cache_type = REGCACHE_NONE;
0330     mfd->regmap[index] = devm_regmap_init_mmio(&dev->dev, mfd->regs[index],
0331                            regmap_config);
0332     WARN_ON(IS_ERR(mfd->regmap[index]));
0333 
0334     return 0;
0335 }
0336 
0337 static int sta2x11_sctl_probe(struct platform_device *dev)
0338 {
0339     return sta2x11_mfd_platform_probe(dev, sta2x11_sctl);
0340 }
0341 
0342 static int sta2x11_apbreg_probe(struct platform_device *dev)
0343 {
0344     return sta2x11_mfd_platform_probe(dev, sta2x11_apbreg);
0345 }
0346 
0347 static int sta2x11_apb_soc_regs_probe(struct platform_device *dev)
0348 {
0349     return sta2x11_mfd_platform_probe(dev, sta2x11_apb_soc_regs);
0350 }
0351 
0352 static int sta2x11_scr_probe(struct platform_device *dev)
0353 {
0354     return sta2x11_mfd_platform_probe(dev, sta2x11_scr);
0355 }
0356 
0357 /* The three platform drivers */
0358 static struct platform_driver sta2x11_sctl_platform_driver = {
0359     .driver = {
0360         .name   = STA2X11_MFD_SCTL_NAME,
0361     },
0362     .probe      = sta2x11_sctl_probe,
0363 };
0364 
0365 static struct platform_driver sta2x11_platform_driver = {
0366     .driver = {
0367         .name   = STA2X11_MFD_APBREG_NAME,
0368     },
0369     .probe      = sta2x11_apbreg_probe,
0370 };
0371 
0372 static struct platform_driver sta2x11_apb_soc_regs_platform_driver = {
0373     .driver = {
0374         .name   = STA2X11_MFD_APB_SOC_REGS_NAME,
0375     },
0376     .probe      = sta2x11_apb_soc_regs_probe,
0377 };
0378 
0379 static struct platform_driver sta2x11_scr_platform_driver = {
0380     .driver = {
0381         .name = STA2X11_MFD_SCR_NAME,
0382     },
0383     .probe = sta2x11_scr_probe,
0384 };
0385 
0386 static struct platform_driver * const drivers[] = {
0387     &sta2x11_platform_driver,
0388     &sta2x11_sctl_platform_driver,
0389     &sta2x11_apb_soc_regs_platform_driver,
0390     &sta2x11_scr_platform_driver,
0391 };
0392 
0393 static int __init sta2x11_drivers_init(void)
0394 {
0395     return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
0396 }
0397 
0398 /*
0399  * What follows are the PCI devices that host the above pdevs.
0400  * Each logic block is 4kB and they are all consecutive: we use this info.
0401  */
0402 
0403 /* Mfd 0 device */
0404 
0405 /* Mfd 0, Bar 0 */
0406 enum mfd0_bar0_cells {
0407     STA2X11_GPIO_0 = 0,
0408     STA2X11_GPIO_1,
0409     STA2X11_GPIO_2,
0410     STA2X11_GPIO_3,
0411     STA2X11_SCTL,
0412     STA2X11_SCR,
0413     STA2X11_TIME,
0414 };
0415 /* Mfd 0 , Bar 1 */
0416 enum mfd0_bar1_cells {
0417     STA2X11_APBREG = 0,
0418 };
0419 #define CELL_4K(_name, _cell) { \
0420         .name = _name, \
0421         .start = _cell * 4096, .end = _cell * 4096 + 4095, \
0422         .flags = IORESOURCE_MEM, \
0423         }
0424 
0425 static const struct resource gpio_resources[] = {
0426     {
0427         /* 4 consecutive cells, 1 driver */
0428         .name = STA2X11_MFD_GPIO_NAME,
0429         .start = 0,
0430         .end = (4 * 4096) - 1,
0431         .flags = IORESOURCE_MEM,
0432     }
0433 };
0434 static const struct resource sctl_resources[] = {
0435     CELL_4K(STA2X11_MFD_SCTL_NAME, STA2X11_SCTL),
0436 };
0437 static const struct resource scr_resources[] = {
0438     CELL_4K(STA2X11_MFD_SCR_NAME, STA2X11_SCR),
0439 };
0440 static const struct resource time_resources[] = {
0441     CELL_4K(STA2X11_MFD_TIME_NAME, STA2X11_TIME),
0442 };
0443 
0444 static const struct resource apbreg_resources[] = {
0445     CELL_4K(STA2X11_MFD_APBREG_NAME, STA2X11_APBREG),
0446 };
0447 
0448 #define DEV(_name, _r) \
0449     { .name = _name, .num_resources = ARRAY_SIZE(_r), .resources = _r, }
0450 
0451 static struct mfd_cell sta2x11_mfd0_bar0[] = {
0452     /* offset 0: we add pdata later */
0453     DEV(STA2X11_MFD_GPIO_NAME, gpio_resources),
0454     DEV(STA2X11_MFD_SCTL_NAME, sctl_resources),
0455     DEV(STA2X11_MFD_SCR_NAME,  scr_resources),
0456     DEV(STA2X11_MFD_TIME_NAME, time_resources),
0457 };
0458 
0459 static struct mfd_cell sta2x11_mfd0_bar1[] = {
0460     DEV(STA2X11_MFD_APBREG_NAME, apbreg_resources),
0461 };
0462 
0463 /* Mfd 1 devices */
0464 
0465 /* Mfd 1, Bar 0 */
0466 enum mfd1_bar0_cells {
0467     STA2X11_VIC = 0,
0468 };
0469 
0470 /* Mfd 1, Bar 1 */
0471 enum mfd1_bar1_cells {
0472     STA2X11_APB_SOC_REGS = 0,
0473 };
0474 
0475 static const struct resource vic_resources[] = {
0476     CELL_4K(STA2X11_MFD_VIC_NAME, STA2X11_VIC),
0477 };
0478 
0479 static const struct resource apb_soc_regs_resources[] = {
0480     CELL_4K(STA2X11_MFD_APB_SOC_REGS_NAME, STA2X11_APB_SOC_REGS),
0481 };
0482 
0483 static struct mfd_cell sta2x11_mfd1_bar0[] = {
0484     DEV(STA2X11_MFD_VIC_NAME, vic_resources),
0485 };
0486 
0487 static struct mfd_cell sta2x11_mfd1_bar1[] = {
0488     DEV(STA2X11_MFD_APB_SOC_REGS_NAME, apb_soc_regs_resources),
0489 };
0490 
0491 
0492 static int sta2x11_mfd_suspend(struct pci_dev *pdev, pm_message_t state)
0493 {
0494     pci_save_state(pdev);
0495     pci_disable_device(pdev);
0496     pci_set_power_state(pdev, pci_choose_state(pdev, state));
0497 
0498     return 0;
0499 }
0500 
0501 static int sta2x11_mfd_resume(struct pci_dev *pdev)
0502 {
0503     int err;
0504 
0505     pci_set_power_state(pdev, PCI_D0);
0506     err = pci_enable_device(pdev);
0507     if (err)
0508         return err;
0509     pci_restore_state(pdev);
0510 
0511     return 0;
0512 }
0513 
0514 struct sta2x11_mfd_bar_setup_data {
0515     struct mfd_cell *cells;
0516     int ncells;
0517 };
0518 
0519 struct sta2x11_mfd_setup_data {
0520     struct sta2x11_mfd_bar_setup_data bars[2];
0521 };
0522 
0523 #define STA2X11_MFD0 0
0524 #define STA2X11_MFD1 1
0525 
0526 static struct sta2x11_mfd_setup_data mfd_setup_data[] = {
0527     /* Mfd 0: gpio, sctl, scr, timers / apbregs */
0528     [STA2X11_MFD0] = {
0529         .bars = {
0530             [0] = {
0531                 .cells = sta2x11_mfd0_bar0,
0532                 .ncells = ARRAY_SIZE(sta2x11_mfd0_bar0),
0533             },
0534             [1] = {
0535                 .cells = sta2x11_mfd0_bar1,
0536                 .ncells = ARRAY_SIZE(sta2x11_mfd0_bar1),
0537             },
0538         },
0539     },
0540     /* Mfd 1: vic / apb-soc-regs */
0541     [STA2X11_MFD1] = {
0542         .bars = {
0543             [0] = {
0544                 .cells = sta2x11_mfd1_bar0,
0545                 .ncells = ARRAY_SIZE(sta2x11_mfd1_bar0),
0546             },
0547             [1] = {
0548                 .cells = sta2x11_mfd1_bar1,
0549                 .ncells = ARRAY_SIZE(sta2x11_mfd1_bar1),
0550             },
0551         },
0552     },
0553 };
0554 
0555 static void sta2x11_mfd_setup(struct pci_dev *pdev,
0556                   struct sta2x11_mfd_setup_data *sd)
0557 {
0558     int i, j;
0559     for (i = 0; i < ARRAY_SIZE(sd->bars); i++)
0560         for (j = 0; j < sd->bars[i].ncells; j++) {
0561             sd->bars[i].cells[j].pdata_size = sizeof(pdev);
0562             sd->bars[i].cells[j].platform_data = &pdev;
0563         }
0564 }
0565 
0566 static int sta2x11_mfd_probe(struct pci_dev *pdev,
0567                  const struct pci_device_id *pci_id)
0568 {
0569     int err, i;
0570     struct sta2x11_mfd_setup_data *setup_data;
0571 
0572     dev_info(&pdev->dev, "%s\n", __func__);
0573 
0574     err = pci_enable_device(pdev);
0575     if (err) {
0576         dev_err(&pdev->dev, "Can't enable device.\n");
0577         return err;
0578     }
0579 
0580     err = pci_enable_msi(pdev);
0581     if (err)
0582         dev_info(&pdev->dev, "Enable msi failed\n");
0583 
0584     setup_data = pci_id->device == PCI_DEVICE_ID_STMICRO_GPIO ?
0585         &mfd_setup_data[STA2X11_MFD0] :
0586         &mfd_setup_data[STA2X11_MFD1];
0587 
0588     /* platform data is the pci device for all of them */
0589     sta2x11_mfd_setup(pdev, setup_data);
0590 
0591     /* Record this pdev before mfd_add_devices: their probe looks for it */
0592     if (!sta2x11_mfd_find(pdev))
0593         sta2x11_mfd_add(pdev, GFP_KERNEL);
0594 
0595     /* Just 2 bars for all mfd's at present */
0596     for (i = 0; i < 2; i++) {
0597         err = mfd_add_devices(&pdev->dev, -1,
0598                       setup_data->bars[i].cells,
0599                       setup_data->bars[i].ncells,
0600                       &pdev->resource[i],
0601                       0, NULL);
0602         if (err) {
0603             dev_err(&pdev->dev,
0604                 "mfd_add_devices[%d] failed: %d\n", i, err);
0605             goto err_disable;
0606         }
0607     }
0608 
0609     return 0;
0610 
0611 err_disable:
0612     mfd_remove_devices(&pdev->dev);
0613     pci_disable_device(pdev);
0614     pci_disable_msi(pdev);
0615     return err;
0616 }
0617 
0618 static const struct pci_device_id sta2x11_mfd_tbl[] = {
0619     {PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_GPIO)},
0620     {PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_VIC)},
0621     {0,},
0622 };
0623 
0624 static struct pci_driver sta2x11_mfd_driver = {
0625     .name =     "sta2x11-mfd",
0626     .id_table = sta2x11_mfd_tbl,
0627     .probe =    sta2x11_mfd_probe,
0628     .suspend =  sta2x11_mfd_suspend,
0629     .resume =   sta2x11_mfd_resume,
0630 };
0631 
0632 static int __init sta2x11_mfd_init(void)
0633 {
0634     pr_info("%s\n", __func__);
0635     return pci_register_driver(&sta2x11_mfd_driver);
0636 }
0637 
0638 /*
0639  * All of this must be ready before "normal" devices like MMCI appear.
0640  * But MFD (the pci device) can't be too early. The following choice
0641  * prepares platform drivers very early and probe the PCI device later,
0642  * but before other PCI devices.
0643  */
0644 subsys_initcall(sta2x11_drivers_init);
0645 rootfs_initcall(sta2x11_mfd_init);
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