drivers/mfd/ssbi.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
0003  * Copyright (c) 2010, Google Inc.
0004  *
0005  * Original authors: Code Aurora Forum
0006  *
0007  * Author: Dima Zavin <dima@android.com>
0008  *  - Largely rewritten from original to not be an i2c driver.
0009  */
0010
0011 #define pr_fmt(fmt) "%s: " fmt, __func__
0012
0013 #include <linux/delay.h>
0014 #include <linux/err.h>
0015 #include <linux/io.h>
0016 #include <linux/kernel.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/slab.h>
0019 #include <linux/ssbi.h>
0020 #include <linux/module.h>
0021 #include <linux/of.h>
0022 #include <linux/of_device.h>
0023
0024 /* SSBI 2.0 controller registers */
0025 #define SSBI2_CMD           0x0008
0026 #define SSBI2_RD            0x0010
0027 #define SSBI2_STATUS            0x0014
0028 #define SSBI2_MODE2         0x001C
0029
0030 /* SSBI_CMD fields */
0031 #define SSBI_CMD_RDWRN          (1 << 24)
0032
0033 /* SSBI_STATUS fields */
0034 #define SSBI_STATUS_RD_READY        (1 << 2)
0035 #define SSBI_STATUS_READY       (1 << 1)
0036 #define SSBI_STATUS_MCHN_BUSY       (1 << 0)
0037
0038 /* SSBI_MODE2 fields */
0039 #define SSBI_MODE2_REG_ADDR_15_8_SHFT   0x04
0040 #define SSBI_MODE2_REG_ADDR_15_8_MASK   (0x7f << SSBI_MODE2_REG_ADDR_15_8_SHFT)
0041
0042 #define SET_SSBI_MODE2_REG_ADDR_15_8(MD, AD) \
0043     (((MD) & 0x0F) | ((((AD) >> 8) << SSBI_MODE2_REG_ADDR_15_8_SHFT) & \
0044     SSBI_MODE2_REG_ADDR_15_8_MASK))
0045
0046 /* SSBI PMIC Arbiter command registers */
0047 #define SSBI_PA_CMD         0x0000
0048 #define SSBI_PA_RD_STATUS       0x0004
0049
0050 /* SSBI_PA_CMD fields */
0051 #define SSBI_PA_CMD_RDWRN       (1 << 24)
0052 #define SSBI_PA_CMD_ADDR_MASK       0x7fff /* REG_ADDR_7_0, REG_ADDR_8_14*/
0053
0054 /* SSBI_PA_RD_STATUS fields */
0055 #define SSBI_PA_RD_STATUS_TRANS_DONE    (1 << 27)
0056 #define SSBI_PA_RD_STATUS_TRANS_DENIED  (1 << 26)
0057
0058 #define SSBI_TIMEOUT_US         100
0059
0060 enum ssbi_controller_type {
0061     MSM_SBI_CTRL_SSBI = 0,
0062     MSM_SBI_CTRL_SSBI2,
0063     MSM_SBI_CTRL_PMIC_ARBITER,
0064 };
0065
0066 struct ssbi {
0067     struct device       *slave;
0068     void __iomem        *base;
0069     spinlock_t      lock;
0070     enum ssbi_controller_type controller_type;
0071     int (*read)(struct ssbi *, u16 addr, u8 *buf, int len);
0072     int (*write)(struct ssbi *, u16 addr, const u8 *buf, int len);
0073 };
0074
0075 static inline u32 ssbi_readl(struct ssbi *ssbi, u32 reg)
0076 {
0077     return readl(ssbi->base + reg);
0078 }
0079
0080 static inline void ssbi_writel(struct ssbi *ssbi, u32 val, u32 reg)
0081 {
0082     writel(val, ssbi->base + reg);
0083 }
0084
0085 /*
0086  * Via private exchange with one of the original authors, the hardware
0087  * should generally finish a transaction in about 5us.  The worst
0088  * case, is when using the arbiter and both other CPUs have just
0089  * started trying to use the SSBI bus will result in a time of about
0090  * 20us.  It should never take longer than this.
0091  *
0092  * As such, this wait merely spins, with a udelay.
0093  */
0094 static int ssbi_wait_mask(struct ssbi *ssbi, u32 set_mask, u32 clr_mask)
0095 {
0096     u32 timeout = SSBI_TIMEOUT_US;
0097     u32 val;
0098
0099     while (timeout--) {
0100         val = ssbi_readl(ssbi, SSBI2_STATUS);
0101         if (((val & set_mask) == set_mask) && ((val & clr_mask) == 0))
0102             return 0;
0103         udelay(1);
0104     }
0105
0106     return -ETIMEDOUT;
0107 }
0108
0109 static int
0110 ssbi_read_bytes(struct ssbi *ssbi, u16 addr, u8 *buf, int len)
0111 {
0112     u32 cmd = SSBI_CMD_RDWRN | ((addr & 0xff) << 16);
0113     int ret = 0;
0114
0115     if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) {
0116         u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2);
0117         mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr);
0118         ssbi_writel(ssbi, mode2, SSBI2_MODE2);
0119     }
0120
0121     while (len) {
0122         ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0);
0123         if (ret)
0124             goto err;
0125
0126         ssbi_writel(ssbi, cmd, SSBI2_CMD);
0127         ret = ssbi_wait_mask(ssbi, SSBI_STATUS_RD_READY, 0);
0128         if (ret)
0129             goto err;
0130         *buf++ = ssbi_readl(ssbi, SSBI2_RD) & 0xff;
0131         len--;
0132     }
0133
0134 err:
0135     return ret;
0136 }
0137
0138 static int
0139 ssbi_write_bytes(struct ssbi *ssbi, u16 addr, const u8 *buf, int len)
0140 {
0141     int ret = 0;
0142
0143     if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) {
0144         u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2);
0145         mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr);
0146         ssbi_writel(ssbi, mode2, SSBI2_MODE2);
0147     }
0148
0149     while (len) {
0150         ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0);
0151         if (ret)
0152             goto err;
0153
0154         ssbi_writel(ssbi, ((addr & 0xff) << 16) | *buf, SSBI2_CMD);
0155         ret = ssbi_wait_mask(ssbi, 0, SSBI_STATUS_MCHN_BUSY);
0156         if (ret)
0157             goto err;
0158         buf++;
0159         len--;
0160     }
0161
0162 err:
0163     return ret;
0164 }
0165
0166 /*
0167  * See ssbi_wait_mask for an explanation of the time and the
0168  * busywait.
0169  */
0170 static inline int
0171 ssbi_pa_transfer(struct ssbi *ssbi, u32 cmd, u8 *data)
0172 {
0173     u32 timeout = SSBI_TIMEOUT_US;
0174     u32 rd_status = 0;
0175
0176     ssbi_writel(ssbi, cmd, SSBI_PA_CMD);
0177
0178     while (timeout--) {
0179         rd_status = ssbi_readl(ssbi, SSBI_PA_RD_STATUS);
0180
0181         if (rd_status & SSBI_PA_RD_STATUS_TRANS_DENIED)
0182             return -EPERM;
0183
0184         if (rd_status & SSBI_PA_RD_STATUS_TRANS_DONE) {
0185             if (data)
0186                 *data = rd_status & 0xff;
0187             return 0;
0188         }
0189         udelay(1);
0190     }
0191
0192     return -ETIMEDOUT;
0193 }
0194
0195 static int
0196 ssbi_pa_read_bytes(struct ssbi *ssbi, u16 addr, u8 *buf, int len)
0197 {
0198     u32 cmd;
0199     int ret = 0;
0200
0201     cmd = SSBI_PA_CMD_RDWRN | (addr & SSBI_PA_CMD_ADDR_MASK) << 8;
0202
0203     while (len) {
0204         ret = ssbi_pa_transfer(ssbi, cmd, buf);
0205         if (ret)
0206             goto err;
0207         buf++;
0208         len--;
0209     }
0210
0211 err:
0212     return ret;
0213 }
0214
0215 static int
0216 ssbi_pa_write_bytes(struct ssbi *ssbi, u16 addr, const u8 *buf, int len)
0217 {
0218     u32 cmd;
0219     int ret = 0;
0220
0221     while (len) {
0222         cmd = (addr & SSBI_PA_CMD_ADDR_MASK) << 8 | *buf;
0223         ret = ssbi_pa_transfer(ssbi, cmd, NULL);
0224         if (ret)
0225             goto err;
0226         buf++;
0227         len--;
0228     }
0229
0230 err:
0231     return ret;
0232 }
0233
0234 int ssbi_read(struct device *dev, u16 addr, u8 *buf, int len)
0235 {
0236     struct ssbi *ssbi = dev_get_drvdata(dev);
0237     unsigned long flags;
0238     int ret;
0239
0240     spin_lock_irqsave(&ssbi->lock, flags);
0241     ret = ssbi->read(ssbi, addr, buf, len);
0242     spin_unlock_irqrestore(&ssbi->lock, flags);
0243
0244     return ret;
0245 }
0246 EXPORT_SYMBOL_GPL(ssbi_read);
0247
0248 int ssbi_write(struct device *dev, u16 addr, const u8 *buf, int len)
0249 {
0250     struct ssbi *ssbi = dev_get_drvdata(dev);
0251     unsigned long flags;
0252     int ret;
0253
0254     spin_lock_irqsave(&ssbi->lock, flags);
0255     ret = ssbi->write(ssbi, addr, buf, len);
0256     spin_unlock_irqrestore(&ssbi->lock, flags);
0257
0258     return ret;
0259 }
0260 EXPORT_SYMBOL_GPL(ssbi_write);
0261
0262 static int ssbi_probe(struct platform_device *pdev)
0263 {
0264     struct device_node *np = pdev->dev.of_node;
0265     struct resource *mem_res;
0266     struct ssbi *ssbi;
0267     const char *type;
0268
0269     ssbi = devm_kzalloc(&pdev->dev, sizeof(*ssbi), GFP_KERNEL);
0270     if (!ssbi)
0271         return -ENOMEM;
0272
0273     mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0274     ssbi->base = devm_ioremap_resource(&pdev->dev, mem_res);
0275     if (IS_ERR(ssbi->base))
0276         return PTR_ERR(ssbi->base);
0277
0278     platform_set_drvdata(pdev, ssbi);
0279
0280     type = of_get_property(np, "qcom,controller-type", NULL);
0281     if (type == NULL) {
0282         dev_err(&pdev->dev, "Missing qcom,controller-type property\n");
0283         return -EINVAL;
0284     }
0285     dev_info(&pdev->dev, "SSBI controller type: '%s'\n", type);
0286     if (strcmp(type, "ssbi") == 0)
0287         ssbi->controller_type = MSM_SBI_CTRL_SSBI;
0288     else if (strcmp(type, "ssbi2") == 0)
0289         ssbi->controller_type = MSM_SBI_CTRL_SSBI2;
0290     else if (strcmp(type, "pmic-arbiter") == 0)
0291         ssbi->controller_type = MSM_SBI_CTRL_PMIC_ARBITER;
0292     else {
0293         dev_err(&pdev->dev, "Unknown qcom,controller-type\n");
0294         return -EINVAL;
0295     }
0296
0297     if (ssbi->controller_type == MSM_SBI_CTRL_PMIC_ARBITER) {
0298         ssbi->read = ssbi_pa_read_bytes;
0299         ssbi->write = ssbi_pa_write_bytes;
0300     } else {
0301         ssbi->read = ssbi_read_bytes;
0302         ssbi->write = ssbi_write_bytes;
0303     }
0304
0305     spin_lock_init(&ssbi->lock);
0306
0307     return devm_of_platform_populate(&pdev->dev);
0308 }
0309
0310 static const struct of_device_id ssbi_match_table[] = {
0311     { .compatible = "qcom,ssbi" },
0312     {}
0313 };
0314 MODULE_DEVICE_TABLE(of, ssbi_match_table);
0315
0316 static struct platform_driver ssbi_driver = {
0317     .probe      = ssbi_probe,
0318     .driver     = {
0319         .name   = "ssbi",
0320         .of_match_table = ssbi_match_table,
0321     },
0322 };
0323 module_platform_driver(ssbi_driver);
0324
0325 MODULE_LICENSE("GPL v2");
0326 MODULE_VERSION("1.0");
0327 MODULE_ALIAS("platform:ssbi");
0328 MODULE_AUTHOR("Dima Zavin <dima@android.com>");