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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* linux/drivers/mfd/sm501.c
0003  *
0004  * Copyright (C) 2006 Simtec Electronics
0005  *  Ben Dooks <ben@simtec.co.uk>
0006  *  Vincent Sanders <vince@simtec.co.uk>
0007  *
0008  * SM501 MFD driver
0009 */
0010 
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/delay.h>
0014 #include <linux/init.h>
0015 #include <linux/list.h>
0016 #include <linux/device.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/pci.h>
0019 #include <linux/platform_data/i2c-gpio.h>
0020 #include <linux/gpio/driver.h>
0021 #include <linux/gpio/machine.h>
0022 #include <linux/slab.h>
0023 
0024 #include <linux/sm501.h>
0025 #include <linux/sm501-regs.h>
0026 #include <linux/serial_8250.h>
0027 
0028 #include <linux/io.h>
0029 
0030 struct sm501_device {
0031     struct list_head        list;
0032     struct platform_device      pdev;
0033 };
0034 
0035 struct sm501_gpio;
0036 
0037 #ifdef CONFIG_MFD_SM501_GPIO
0038 #include <linux/gpio.h>
0039 
0040 struct sm501_gpio_chip {
0041     struct gpio_chip    gpio;
0042     struct sm501_gpio   *ourgpio;   /* to get back to parent. */
0043     void __iomem        *regbase;
0044     void __iomem        *control;   /* address of control reg. */
0045 };
0046 
0047 struct sm501_gpio {
0048     struct sm501_gpio_chip  low;
0049     struct sm501_gpio_chip  high;
0050     spinlock_t      lock;
0051 
0052     unsigned int         registered : 1;
0053     void __iomem        *regs;
0054     struct resource     *regs_res;
0055 };
0056 #else
0057 struct sm501_gpio {
0058     /* no gpio support, empty definition for sm501_devdata. */
0059 };
0060 #endif
0061 
0062 struct sm501_devdata {
0063     spinlock_t           reg_lock;
0064     struct mutex             clock_lock;
0065     struct list_head         devices;
0066     struct sm501_gpio        gpio;
0067 
0068     struct device           *dev;
0069     struct resource         *io_res;
0070     struct resource         *mem_res;
0071     struct resource         *regs_claim;
0072     struct sm501_platdata       *platdata;
0073 
0074 
0075     unsigned int             in_suspend;
0076     unsigned long            pm_misc;
0077 
0078     int              unit_power[20];
0079     unsigned int             pdev_id;
0080     unsigned int             irq;
0081     void __iomem            *regs;
0082     unsigned int             rev;
0083 };
0084 
0085 
0086 #define MHZ (1000 * 1000)
0087 
0088 #ifdef DEBUG
0089 static const unsigned int div_tab[] = {
0090     [0]     = 1,
0091     [1]     = 2,
0092     [2]     = 4,
0093     [3]     = 8,
0094     [4]     = 16,
0095     [5]     = 32,
0096     [6]     = 64,
0097     [7]     = 128,
0098     [8]     = 3,
0099     [9]     = 6,
0100     [10]            = 12,
0101     [11]        = 24,
0102     [12]        = 48,
0103     [13]        = 96,
0104     [14]        = 192,
0105     [15]        = 384,
0106     [16]        = 5,
0107     [17]        = 10,
0108     [18]        = 20,
0109     [19]        = 40,
0110     [20]        = 80,
0111     [21]        = 160,
0112     [22]        = 320,
0113     [23]        = 604,
0114 };
0115 
0116 static unsigned long decode_div(unsigned long pll2, unsigned long val,
0117                 unsigned int lshft, unsigned int selbit,
0118                 unsigned long mask)
0119 {
0120     if (val & selbit)
0121         pll2 = 288 * MHZ;
0122 
0123     return pll2 / div_tab[(val >> lshft) & mask];
0124 }
0125 
0126 #define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
0127 
0128 /* sm501_dump_clk
0129  *
0130  * Print out the current clock configuration for the device
0131 */
0132 
0133 static void sm501_dump_clk(struct sm501_devdata *sm)
0134 {
0135     unsigned long misct = smc501_readl(sm->regs + SM501_MISC_TIMING);
0136     unsigned long pm0 = smc501_readl(sm->regs + SM501_POWER_MODE_0_CLOCK);
0137     unsigned long pm1 = smc501_readl(sm->regs + SM501_POWER_MODE_1_CLOCK);
0138     unsigned long pmc = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
0139     unsigned long sdclk0, sdclk1;
0140     unsigned long pll2 = 0;
0141 
0142     switch (misct & 0x30) {
0143     case 0x00:
0144         pll2 = 336 * MHZ;
0145         break;
0146     case 0x10:
0147         pll2 = 288 * MHZ;
0148         break;
0149     case 0x20:
0150         pll2 = 240 * MHZ;
0151         break;
0152     case 0x30:
0153         pll2 = 192 * MHZ;
0154         break;
0155     }
0156 
0157     sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;
0158     sdclk0 /= div_tab[((misct >> 8) & 0xf)];
0159 
0160     sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;
0161     sdclk1 /= div_tab[((misct >> 16) & 0xf)];
0162 
0163     dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n",
0164         misct, pm0, pm1);
0165 
0166     dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n",
0167         fmt_freq(pll2), sdclk0, sdclk1);
0168 
0169     dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1);
0170 
0171     dev_dbg(sm->dev, "PM0[%c]: "
0172          "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
0173          "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
0174          (pmc & 3 ) == 0 ? '*' : '-',
0175          fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)),
0176          fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)),
0177          fmt_freq(decode_div(pll2, pm0, 8,  1<<12, 15)),
0178          fmt_freq(decode_div(pll2, pm0, 0,  1<<4,  15)));
0179 
0180     dev_dbg(sm->dev, "PM1[%c]: "
0181         "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
0182         "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
0183         (pmc & 3 ) == 1 ? '*' : '-',
0184         fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)),
0185         fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)),
0186         fmt_freq(decode_div(pll2, pm1, 8,  1<<12, 15)),
0187         fmt_freq(decode_div(pll2, pm1, 0,  1<<4,  15)));
0188 }
0189 
0190 static void sm501_dump_regs(struct sm501_devdata *sm)
0191 {
0192     void __iomem *regs = sm->regs;
0193 
0194     dev_info(sm->dev, "System Control   %08x\n",
0195             smc501_readl(regs + SM501_SYSTEM_CONTROL));
0196     dev_info(sm->dev, "Misc Control     %08x\n",
0197             smc501_readl(regs + SM501_MISC_CONTROL));
0198     dev_info(sm->dev, "GPIO Control Low %08x\n",
0199             smc501_readl(regs + SM501_GPIO31_0_CONTROL));
0200     dev_info(sm->dev, "GPIO Control Hi  %08x\n",
0201             smc501_readl(regs + SM501_GPIO63_32_CONTROL));
0202     dev_info(sm->dev, "DRAM Control     %08x\n",
0203             smc501_readl(regs + SM501_DRAM_CONTROL));
0204     dev_info(sm->dev, "Arbitration Ctrl %08x\n",
0205             smc501_readl(regs + SM501_ARBTRTN_CONTROL));
0206     dev_info(sm->dev, "Misc Timing      %08x\n",
0207             smc501_readl(regs + SM501_MISC_TIMING));
0208 }
0209 
0210 static void sm501_dump_gate(struct sm501_devdata *sm)
0211 {
0212     dev_info(sm->dev, "CurrentGate      %08x\n",
0213             smc501_readl(sm->regs + SM501_CURRENT_GATE));
0214     dev_info(sm->dev, "CurrentClock     %08x\n",
0215             smc501_readl(sm->regs + SM501_CURRENT_CLOCK));
0216     dev_info(sm->dev, "PowerModeControl %08x\n",
0217             smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL));
0218 }
0219 
0220 #else
0221 static inline void sm501_dump_gate(struct sm501_devdata *sm) { }
0222 static inline void sm501_dump_regs(struct sm501_devdata *sm) { }
0223 static inline void sm501_dump_clk(struct sm501_devdata *sm) { }
0224 #endif
0225 
0226 /* sm501_sync_regs
0227  *
0228  * ensure the
0229 */
0230 
0231 static void sm501_sync_regs(struct sm501_devdata *sm)
0232 {
0233     smc501_readl(sm->regs);
0234 }
0235 
0236 static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay)
0237 {
0238     /* during suspend/resume, we are currently not allowed to sleep,
0239      * so change to using mdelay() instead of msleep() if we
0240      * are in one of these paths */
0241 
0242     if (sm->in_suspend)
0243         mdelay(delay);
0244     else
0245         msleep(delay);
0246 }
0247 
0248 /* sm501_misc_control
0249  *
0250  * alters the miscellaneous control parameters
0251 */
0252 
0253 int sm501_misc_control(struct device *dev,
0254                unsigned long set, unsigned long clear)
0255 {
0256     struct sm501_devdata *sm = dev_get_drvdata(dev);
0257     unsigned long misc;
0258     unsigned long save;
0259     unsigned long to;
0260 
0261     spin_lock_irqsave(&sm->reg_lock, save);
0262 
0263     misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);
0264     to = (misc & ~clear) | set;
0265 
0266     if (to != misc) {
0267         smc501_writel(to, sm->regs + SM501_MISC_CONTROL);
0268         sm501_sync_regs(sm);
0269 
0270         dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc);
0271     }
0272 
0273     spin_unlock_irqrestore(&sm->reg_lock, save);
0274     return to;
0275 }
0276 
0277 EXPORT_SYMBOL_GPL(sm501_misc_control);
0278 
0279 /* sm501_modify_reg
0280  *
0281  * Modify a register in the SM501 which may be shared with other
0282  * drivers.
0283 */
0284 
0285 unsigned long sm501_modify_reg(struct device *dev,
0286                    unsigned long reg,
0287                    unsigned long set,
0288                    unsigned long clear)
0289 {
0290     struct sm501_devdata *sm = dev_get_drvdata(dev);
0291     unsigned long data;
0292     unsigned long save;
0293 
0294     spin_lock_irqsave(&sm->reg_lock, save);
0295 
0296     data = smc501_readl(sm->regs + reg);
0297     data |= set;
0298     data &= ~clear;
0299 
0300     smc501_writel(data, sm->regs + reg);
0301     sm501_sync_regs(sm);
0302 
0303     spin_unlock_irqrestore(&sm->reg_lock, save);
0304 
0305     return data;
0306 }
0307 
0308 EXPORT_SYMBOL_GPL(sm501_modify_reg);
0309 
0310 /* sm501_unit_power
0311  *
0312  * alters the power active gate to set specific units on or off
0313  */
0314 
0315 int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to)
0316 {
0317     struct sm501_devdata *sm = dev_get_drvdata(dev);
0318     unsigned long mode;
0319     unsigned long gate;
0320     unsigned long clock;
0321 
0322     mutex_lock(&sm->clock_lock);
0323 
0324     mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
0325     gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
0326     clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
0327 
0328     mode &= 3;      /* get current power mode */
0329 
0330     if (unit >= ARRAY_SIZE(sm->unit_power)) {
0331         dev_err(dev, "%s: bad unit %d\n", __func__, unit);
0332         goto already;
0333     }
0334 
0335     dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit,
0336         sm->unit_power[unit], to);
0337 
0338     if (to == 0 && sm->unit_power[unit] == 0) {
0339         dev_err(sm->dev, "unit %d is already shutdown\n", unit);
0340         goto already;
0341     }
0342 
0343     sm->unit_power[unit] += to ? 1 : -1;
0344     to = sm->unit_power[unit] ? 1 : 0;
0345 
0346     if (to) {
0347         if (gate & (1 << unit))
0348             goto already;
0349         gate |= (1 << unit);
0350     } else {
0351         if (!(gate & (1 << unit)))
0352             goto already;
0353         gate &= ~(1 << unit);
0354     }
0355 
0356     switch (mode) {
0357     case 1:
0358         smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
0359         smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
0360         mode = 0;
0361         break;
0362     case 2:
0363     case 0:
0364         smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
0365         smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
0366         mode = 1;
0367         break;
0368 
0369     default:
0370         gate = -1;
0371         goto already;
0372     }
0373 
0374     smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
0375     sm501_sync_regs(sm);
0376 
0377     dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
0378         gate, clock, mode);
0379 
0380     sm501_mdelay(sm, 16);
0381 
0382  already:
0383     mutex_unlock(&sm->clock_lock);
0384     return gate;
0385 }
0386 
0387 EXPORT_SYMBOL_GPL(sm501_unit_power);
0388 
0389 /* clock value structure. */
0390 struct sm501_clock {
0391     unsigned long mclk;
0392     int divider;
0393     int shift;
0394     unsigned int m, n, k;
0395 };
0396 
0397 /* sm501_calc_clock
0398  *
0399  * Calculates the nearest discrete clock frequency that
0400  * can be achieved with the specified input clock.
0401  *   the maximum divisor is 3 or 5
0402  */
0403 
0404 static int sm501_calc_clock(unsigned long freq,
0405                 struct sm501_clock *clock,
0406                 int max_div,
0407                 unsigned long mclk,
0408                 long *best_diff)
0409 {
0410     int ret = 0;
0411     int divider;
0412     int shift;
0413     long diff;
0414 
0415     /* try dividers 1 and 3 for CRT and for panel,
0416        try divider 5 for panel only.*/
0417 
0418     for (divider = 1; divider <= max_div; divider += 2) {
0419         /* try all 8 shift values.*/
0420         for (shift = 0; shift < 8; shift++) {
0421             /* Calculate difference to requested clock */
0422             diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq;
0423             if (diff < 0)
0424                 diff = -diff;
0425 
0426             /* If it is less than the current, use it */
0427             if (diff < *best_diff) {
0428                 *best_diff = diff;
0429 
0430                 clock->mclk = mclk;
0431                 clock->divider = divider;
0432                 clock->shift = shift;
0433                 ret = 1;
0434             }
0435         }
0436     }
0437 
0438     return ret;
0439 }
0440 
0441 /* sm501_calc_pll
0442  *
0443  * Calculates the nearest discrete clock frequency that can be
0444  * achieved using the programmable PLL.
0445  *   the maximum divisor is 3 or 5
0446  */
0447 
0448 static unsigned long sm501_calc_pll(unsigned long freq,
0449                     struct sm501_clock *clock,
0450                     int max_div)
0451 {
0452     unsigned long mclk;
0453     unsigned int m, n, k;
0454     long best_diff = 999999999;
0455 
0456     /*
0457      * The SM502 datasheet doesn't specify the min/max values for M and N.
0458      * N = 1 at least doesn't work in practice.
0459      */
0460     for (m = 2; m <= 255; m++) {
0461         for (n = 2; n <= 127; n++) {
0462             for (k = 0; k <= 1; k++) {
0463                 mclk = (24000000UL * m / n) >> k;
0464 
0465                 if (sm501_calc_clock(freq, clock, max_div,
0466                              mclk, &best_diff)) {
0467                     clock->m = m;
0468                     clock->n = n;
0469                     clock->k = k;
0470                 }
0471             }
0472         }
0473     }
0474 
0475     /* Return best clock. */
0476     return clock->mclk / (clock->divider << clock->shift);
0477 }
0478 
0479 /* sm501_select_clock
0480  *
0481  * Calculates the nearest discrete clock frequency that can be
0482  * achieved using the 288MHz and 336MHz PLLs.
0483  *   the maximum divisor is 3 or 5
0484  */
0485 
0486 static unsigned long sm501_select_clock(unsigned long freq,
0487                     struct sm501_clock *clock,
0488                     int max_div)
0489 {
0490     unsigned long mclk;
0491     long best_diff = 999999999;
0492 
0493     /* Try 288MHz and 336MHz clocks. */
0494     for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
0495         sm501_calc_clock(freq, clock, max_div, mclk, &best_diff);
0496     }
0497 
0498     /* Return best clock. */
0499     return clock->mclk / (clock->divider << clock->shift);
0500 }
0501 
0502 /* sm501_set_clock
0503  *
0504  * set one of the four clock sources to the closest available frequency to
0505  *  the one specified
0506 */
0507 
0508 unsigned long sm501_set_clock(struct device *dev,
0509                   int clksrc,
0510                   unsigned long req_freq)
0511 {
0512     struct sm501_devdata *sm = dev_get_drvdata(dev);
0513     unsigned long mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
0514     unsigned long gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
0515     unsigned long clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
0516     unsigned int pll_reg = 0;
0517     unsigned long sm501_freq; /* the actual frequency achieved */
0518     u64 reg;
0519 
0520     struct sm501_clock to;
0521 
0522     /* find achivable discrete frequency and setup register value
0523      * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK
0524      * has an extra bit for the divider */
0525 
0526     switch (clksrc) {
0527     case SM501_CLOCK_P2XCLK:
0528         /* This clock is divided in half so to achieve the
0529          * requested frequency the value must be multiplied by
0530          * 2. This clock also has an additional pre divisor */
0531 
0532         if (sm->rev >= 0xC0) {
0533             /* SM502 -> use the programmable PLL */
0534             sm501_freq = (sm501_calc_pll(2 * req_freq,
0535                              &to, 5) / 2);
0536             reg = to.shift & 0x07;/* bottom 3 bits are shift */
0537             if (to.divider == 3)
0538                 reg |= 0x08; /* /3 divider required */
0539             else if (to.divider == 5)
0540                 reg |= 0x10; /* /5 divider required */
0541             reg |= 0x40; /* select the programmable PLL */
0542             pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m;
0543         } else {
0544             sm501_freq = (sm501_select_clock(2 * req_freq,
0545                              &to, 5) / 2);
0546             reg = to.shift & 0x07;/* bottom 3 bits are shift */
0547             if (to.divider == 3)
0548                 reg |= 0x08; /* /3 divider required */
0549             else if (to.divider == 5)
0550                 reg |= 0x10; /* /5 divider required */
0551             if (to.mclk != 288000000)
0552                 reg |= 0x20; /* which mclk pll is source */
0553         }
0554         break;
0555 
0556     case SM501_CLOCK_V2XCLK:
0557         /* This clock is divided in half so to achieve the
0558          * requested frequency the value must be multiplied by 2. */
0559 
0560         sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
0561         reg=to.shift & 0x07;    /* bottom 3 bits are shift */
0562         if (to.divider == 3)
0563             reg |= 0x08;    /* /3 divider required */
0564         if (to.mclk != 288000000)
0565             reg |= 0x10;    /* which mclk pll is source */
0566         break;
0567 
0568     case SM501_CLOCK_MCLK:
0569     case SM501_CLOCK_M1XCLK:
0570         /* These clocks are the same and not further divided */
0571 
0572         sm501_freq = sm501_select_clock( req_freq, &to, 3);
0573         reg=to.shift & 0x07;    /* bottom 3 bits are shift */
0574         if (to.divider == 3)
0575             reg |= 0x08;    /* /3 divider required */
0576         if (to.mclk != 288000000)
0577             reg |= 0x10;    /* which mclk pll is source */
0578         break;
0579 
0580     default:
0581         return 0; /* this is bad */
0582     }
0583 
0584     mutex_lock(&sm->clock_lock);
0585 
0586     mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
0587     gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
0588     clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
0589 
0590     clock = clock & ~(0xFF << clksrc);
0591     clock |= reg<<clksrc;
0592 
0593     mode &= 3;  /* find current mode */
0594 
0595     switch (mode) {
0596     case 1:
0597         smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
0598         smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
0599         mode = 0;
0600         break;
0601     case 2:
0602     case 0:
0603         smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
0604         smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
0605         mode = 1;
0606         break;
0607 
0608     default:
0609         mutex_unlock(&sm->clock_lock);
0610         return -1;
0611     }
0612 
0613     smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
0614 
0615     if (pll_reg)
0616         smc501_writel(pll_reg,
0617                 sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL);
0618 
0619     sm501_sync_regs(sm);
0620 
0621     dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
0622         gate, clock, mode);
0623 
0624     sm501_mdelay(sm, 16);
0625     mutex_unlock(&sm->clock_lock);
0626 
0627     sm501_dump_clk(sm);
0628 
0629     return sm501_freq;
0630 }
0631 
0632 EXPORT_SYMBOL_GPL(sm501_set_clock);
0633 
0634 /* sm501_find_clock
0635  *
0636  * finds the closest available frequency for a given clock
0637 */
0638 
0639 unsigned long sm501_find_clock(struct device *dev,
0640                    int clksrc,
0641                    unsigned long req_freq)
0642 {
0643     struct sm501_devdata *sm = dev_get_drvdata(dev);
0644     unsigned long sm501_freq; /* the frequency achieveable by the 501 */
0645     struct sm501_clock to;
0646 
0647     switch (clksrc) {
0648     case SM501_CLOCK_P2XCLK:
0649         if (sm->rev >= 0xC0) {
0650             /* SM502 -> use the programmable PLL */
0651             sm501_freq = (sm501_calc_pll(2 * req_freq,
0652                              &to, 5) / 2);
0653         } else {
0654             sm501_freq = (sm501_select_clock(2 * req_freq,
0655                              &to, 5) / 2);
0656         }
0657         break;
0658 
0659     case SM501_CLOCK_V2XCLK:
0660         sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
0661         break;
0662 
0663     case SM501_CLOCK_MCLK:
0664     case SM501_CLOCK_M1XCLK:
0665         sm501_freq = sm501_select_clock(req_freq, &to, 3);
0666         break;
0667 
0668     default:
0669         sm501_freq = 0;     /* error */
0670     }
0671 
0672     return sm501_freq;
0673 }
0674 
0675 EXPORT_SYMBOL_GPL(sm501_find_clock);
0676 
0677 static struct sm501_device *to_sm_device(struct platform_device *pdev)
0678 {
0679     return container_of(pdev, struct sm501_device, pdev);
0680 }
0681 
0682 /* sm501_device_release
0683  *
0684  * A release function for the platform devices we create to allow us to
0685  * free any items we allocated
0686 */
0687 
0688 static void sm501_device_release(struct device *dev)
0689 {
0690     kfree(to_sm_device(to_platform_device(dev)));
0691 }
0692 
0693 /* sm501_create_subdev
0694  *
0695  * Create a skeleton platform device with resources for passing to a
0696  * sub-driver
0697 */
0698 
0699 static struct platform_device *
0700 sm501_create_subdev(struct sm501_devdata *sm, char *name,
0701             unsigned int res_count, unsigned int platform_data_size)
0702 {
0703     struct sm501_device *smdev;
0704 
0705     smdev = kzalloc(sizeof(struct sm501_device) +
0706             (sizeof(struct resource) * res_count) +
0707             platform_data_size, GFP_KERNEL);
0708     if (!smdev)
0709         return NULL;
0710 
0711     smdev->pdev.dev.release = sm501_device_release;
0712 
0713     smdev->pdev.name = name;
0714     smdev->pdev.id = sm->pdev_id;
0715     smdev->pdev.dev.parent = sm->dev;
0716     smdev->pdev.dev.coherent_dma_mask = 0xffffffff;
0717 
0718     if (res_count) {
0719         smdev->pdev.resource = (struct resource *)(smdev+1);
0720         smdev->pdev.num_resources = res_count;
0721     }
0722     if (platform_data_size)
0723         smdev->pdev.dev.platform_data = (void *)(smdev+1);
0724 
0725     return &smdev->pdev;
0726 }
0727 
0728 /* sm501_register_device
0729  *
0730  * Register a platform device created with sm501_create_subdev()
0731 */
0732 
0733 static int sm501_register_device(struct sm501_devdata *sm,
0734                  struct platform_device *pdev)
0735 {
0736     struct sm501_device *smdev = to_sm_device(pdev);
0737     int ptr;
0738     int ret;
0739 
0740     for (ptr = 0; ptr < pdev->num_resources; ptr++) {
0741         printk(KERN_DEBUG "%s[%d] %pR\n",
0742                pdev->name, ptr, &pdev->resource[ptr]);
0743     }
0744 
0745     ret = platform_device_register(pdev);
0746 
0747     if (ret >= 0) {
0748         dev_dbg(sm->dev, "registered %s\n", pdev->name);
0749         list_add_tail(&smdev->list, &sm->devices);
0750     } else
0751         dev_err(sm->dev, "error registering %s (%d)\n",
0752             pdev->name, ret);
0753 
0754     return ret;
0755 }
0756 
0757 /* sm501_create_subio
0758  *
0759  * Fill in an IO resource for a sub device
0760 */
0761 
0762 static void sm501_create_subio(struct sm501_devdata *sm,
0763                    struct resource *res,
0764                    resource_size_t offs,
0765                    resource_size_t size)
0766 {
0767     res->flags = IORESOURCE_MEM;
0768     res->parent = sm->io_res;
0769     res->start = sm->io_res->start + offs;
0770     res->end = res->start + size - 1;
0771 }
0772 
0773 /* sm501_create_mem
0774  *
0775  * Fill in an MEM resource for a sub device
0776 */
0777 
0778 static void sm501_create_mem(struct sm501_devdata *sm,
0779                  struct resource *res,
0780                  resource_size_t *offs,
0781                  resource_size_t size)
0782 {
0783     *offs -= size;      /* adjust memory size */
0784 
0785     res->flags = IORESOURCE_MEM;
0786     res->parent = sm->mem_res;
0787     res->start = sm->mem_res->start + *offs;
0788     res->end = res->start + size - 1;
0789 }
0790 
0791 /* sm501_create_irq
0792  *
0793  * Fill in an IRQ resource for a sub device
0794 */
0795 
0796 static void sm501_create_irq(struct sm501_devdata *sm,
0797                  struct resource *res)
0798 {
0799     res->flags = IORESOURCE_IRQ;
0800     res->parent = NULL;
0801     res->start = res->end = sm->irq;
0802 }
0803 
0804 static int sm501_register_usbhost(struct sm501_devdata *sm,
0805                   resource_size_t *mem_avail)
0806 {
0807     struct platform_device *pdev;
0808 
0809     pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0);
0810     if (!pdev)
0811         return -ENOMEM;
0812 
0813     sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000);
0814     sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024);
0815     sm501_create_irq(sm, &pdev->resource[2]);
0816 
0817     return sm501_register_device(sm, pdev);
0818 }
0819 
0820 static void sm501_setup_uart_data(struct sm501_devdata *sm,
0821                   struct plat_serial8250_port *uart_data,
0822                   unsigned int offset)
0823 {
0824     uart_data->membase = sm->regs + offset;
0825     uart_data->mapbase = sm->io_res->start + offset;
0826     uart_data->iotype = UPIO_MEM;
0827     uart_data->irq = sm->irq;
0828     uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
0829     uart_data->regshift = 2;
0830     uart_data->uartclk = (9600 * 16);
0831 }
0832 
0833 static int sm501_register_uart(struct sm501_devdata *sm, int devices)
0834 {
0835     struct platform_device *pdev;
0836     struct plat_serial8250_port *uart_data;
0837 
0838     pdev = sm501_create_subdev(sm, "serial8250", 0,
0839                    sizeof(struct plat_serial8250_port) * 3);
0840     if (!pdev)
0841         return -ENOMEM;
0842 
0843     uart_data = dev_get_platdata(&pdev->dev);
0844 
0845     if (devices & SM501_USE_UART0) {
0846         sm501_setup_uart_data(sm, uart_data++, 0x30000);
0847         sm501_unit_power(sm->dev, SM501_GATE_UART0, 1);
0848         sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0);
0849         sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0);
0850     }
0851     if (devices & SM501_USE_UART1) {
0852         sm501_setup_uart_data(sm, uart_data++, 0x30020);
0853         sm501_unit_power(sm->dev, SM501_GATE_UART1, 1);
0854         sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0);
0855         sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0);
0856     }
0857 
0858     pdev->id = PLAT8250_DEV_SM501;
0859 
0860     return sm501_register_device(sm, pdev);
0861 }
0862 
0863 static int sm501_register_display(struct sm501_devdata *sm,
0864                   resource_size_t *mem_avail)
0865 {
0866     struct platform_device *pdev;
0867 
0868     pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0);
0869     if (!pdev)
0870         return -ENOMEM;
0871 
0872     sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);
0873     sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000);
0874     sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail);
0875     sm501_create_irq(sm, &pdev->resource[3]);
0876 
0877     return sm501_register_device(sm, pdev);
0878 }
0879 
0880 #ifdef CONFIG_MFD_SM501_GPIO
0881 
0882 static inline struct sm501_devdata *sm501_gpio_to_dev(struct sm501_gpio *gpio)
0883 {
0884     return container_of(gpio, struct sm501_devdata, gpio);
0885 }
0886 
0887 static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset)
0888 
0889 {
0890     struct sm501_gpio_chip *smgpio = gpiochip_get_data(chip);
0891     unsigned long result;
0892 
0893     result = smc501_readl(smgpio->regbase + SM501_GPIO_DATA_LOW);
0894     result >>= offset;
0895 
0896     return result & 1UL;
0897 }
0898 
0899 static void sm501_gpio_ensure_gpio(struct sm501_gpio_chip *smchip,
0900                    unsigned long bit)
0901 {
0902     unsigned long ctrl;
0903 
0904     /* check and modify if this pin is not set as gpio. */
0905 
0906     if (smc501_readl(smchip->control) & bit) {
0907         dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev,
0908              "changing mode of gpio, bit %08lx\n", bit);
0909 
0910         ctrl = smc501_readl(smchip->control);
0911         ctrl &= ~bit;
0912         smc501_writel(ctrl, smchip->control);
0913 
0914         sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio));
0915     }
0916 }
0917 
0918 static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
0919 
0920 {
0921     struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);
0922     struct sm501_gpio *smgpio = smchip->ourgpio;
0923     unsigned long bit = 1 << offset;
0924     void __iomem *regs = smchip->regbase;
0925     unsigned long save;
0926     unsigned long val;
0927 
0928     dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
0929         __func__, chip, offset);
0930 
0931     spin_lock_irqsave(&smgpio->lock, save);
0932 
0933     val = smc501_readl(regs + SM501_GPIO_DATA_LOW) & ~bit;
0934     if (value)
0935         val |= bit;
0936     smc501_writel(val, regs);
0937 
0938     sm501_sync_regs(sm501_gpio_to_dev(smgpio));
0939     sm501_gpio_ensure_gpio(smchip, bit);
0940 
0941     spin_unlock_irqrestore(&smgpio->lock, save);
0942 }
0943 
0944 static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset)
0945 {
0946     struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);
0947     struct sm501_gpio *smgpio = smchip->ourgpio;
0948     void __iomem *regs = smchip->regbase;
0949     unsigned long bit = 1 << offset;
0950     unsigned long save;
0951     unsigned long ddr;
0952 
0953     dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
0954         __func__, chip, offset);
0955 
0956     spin_lock_irqsave(&smgpio->lock, save);
0957 
0958     ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);
0959     smc501_writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW);
0960 
0961     sm501_sync_regs(sm501_gpio_to_dev(smgpio));
0962     sm501_gpio_ensure_gpio(smchip, bit);
0963 
0964     spin_unlock_irqrestore(&smgpio->lock, save);
0965 
0966     return 0;
0967 }
0968 
0969 static int sm501_gpio_output(struct gpio_chip *chip,
0970                  unsigned offset, int value)
0971 {
0972     struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);
0973     struct sm501_gpio *smgpio = smchip->ourgpio;
0974     unsigned long bit = 1 << offset;
0975     void __iomem *regs = smchip->regbase;
0976     unsigned long save;
0977     unsigned long val;
0978     unsigned long ddr;
0979 
0980     dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d,%d)\n",
0981         __func__, chip, offset, value);
0982 
0983     spin_lock_irqsave(&smgpio->lock, save);
0984 
0985     val = smc501_readl(regs + SM501_GPIO_DATA_LOW);
0986     if (value)
0987         val |= bit;
0988     else
0989         val &= ~bit;
0990     smc501_writel(val, regs);
0991 
0992     ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);
0993     smc501_writel(ddr | bit, regs + SM501_GPIO_DDR_LOW);
0994 
0995     sm501_sync_regs(sm501_gpio_to_dev(smgpio));
0996     smc501_writel(val, regs + SM501_GPIO_DATA_LOW);
0997 
0998     sm501_sync_regs(sm501_gpio_to_dev(smgpio));
0999     spin_unlock_irqrestore(&smgpio->lock, save);
1000 
1001     return 0;
1002 }
1003 
1004 static const struct gpio_chip gpio_chip_template = {
1005     .ngpio          = 32,
1006     .direction_input    = sm501_gpio_input,
1007     .direction_output   = sm501_gpio_output,
1008     .set            = sm501_gpio_set,
1009     .get            = sm501_gpio_get,
1010 };
1011 
1012 static int sm501_gpio_register_chip(struct sm501_devdata *sm,
1013                           struct sm501_gpio *gpio,
1014                           struct sm501_gpio_chip *chip)
1015 {
1016     struct sm501_platdata *pdata = sm->platdata;
1017     struct gpio_chip *gchip = &chip->gpio;
1018     int base = pdata->gpio_base;
1019 
1020     chip->gpio = gpio_chip_template;
1021 
1022     if (chip == &gpio->high) {
1023         if (base > 0)
1024             base += 32;
1025         chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH;
1026         chip->control = sm->regs + SM501_GPIO63_32_CONTROL;
1027         gchip->label  = "SM501-HIGH";
1028     } else {
1029         chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW;
1030         chip->control = sm->regs + SM501_GPIO31_0_CONTROL;
1031         gchip->label  = "SM501-LOW";
1032     }
1033 
1034     gchip->base   = base;
1035     chip->ourgpio = gpio;
1036 
1037     return gpiochip_add_data(gchip, chip);
1038 }
1039 
1040 static int sm501_register_gpio(struct sm501_devdata *sm)
1041 {
1042     struct sm501_gpio *gpio = &sm->gpio;
1043     resource_size_t iobase = sm->io_res->start + SM501_GPIO;
1044     int ret;
1045 
1046     dev_dbg(sm->dev, "registering gpio block %08llx\n",
1047         (unsigned long long)iobase);
1048 
1049     spin_lock_init(&gpio->lock);
1050 
1051     gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio");
1052     if (!gpio->regs_res) {
1053         dev_err(sm->dev, "gpio: failed to request region\n");
1054         return -ENXIO;
1055     }
1056 
1057     gpio->regs = ioremap(iobase, 0x20);
1058     if (!gpio->regs) {
1059         dev_err(sm->dev, "gpio: failed to remap registers\n");
1060         ret = -ENXIO;
1061         goto err_claimed;
1062     }
1063 
1064     /* Register both our chips. */
1065 
1066     ret = sm501_gpio_register_chip(sm, gpio, &gpio->low);
1067     if (ret) {
1068         dev_err(sm->dev, "failed to add low chip\n");
1069         goto err_mapped;
1070     }
1071 
1072     ret = sm501_gpio_register_chip(sm, gpio, &gpio->high);
1073     if (ret) {
1074         dev_err(sm->dev, "failed to add high chip\n");
1075         goto err_low_chip;
1076     }
1077 
1078     gpio->registered = 1;
1079 
1080     return 0;
1081 
1082  err_low_chip:
1083     gpiochip_remove(&gpio->low.gpio);
1084 
1085  err_mapped:
1086     iounmap(gpio->regs);
1087 
1088  err_claimed:
1089     release_mem_region(iobase, 0x20);
1090 
1091     return ret;
1092 }
1093 
1094 static void sm501_gpio_remove(struct sm501_devdata *sm)
1095 {
1096     struct sm501_gpio *gpio = &sm->gpio;
1097     resource_size_t iobase = sm->io_res->start + SM501_GPIO;
1098 
1099     if (!sm->gpio.registered)
1100         return;
1101 
1102     gpiochip_remove(&gpio->low.gpio);
1103     gpiochip_remove(&gpio->high.gpio);
1104 
1105     iounmap(gpio->regs);
1106     release_mem_region(iobase, 0x20);
1107 }
1108 
1109 static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1110 {
1111     return sm->gpio.registered;
1112 }
1113 #else
1114 static inline int sm501_register_gpio(struct sm501_devdata *sm)
1115 {
1116     return 0;
1117 }
1118 
1119 static inline void sm501_gpio_remove(struct sm501_devdata *sm)
1120 {
1121 }
1122 
1123 static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1124 {
1125     return 0;
1126 }
1127 #endif
1128 
1129 static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm,
1130                         struct sm501_platdata_gpio_i2c *iic)
1131 {
1132     struct i2c_gpio_platform_data *icd;
1133     struct platform_device *pdev;
1134     struct gpiod_lookup_table *lookup;
1135 
1136     pdev = sm501_create_subdev(sm, "i2c-gpio", 0,
1137                    sizeof(struct i2c_gpio_platform_data));
1138     if (!pdev)
1139         return -ENOMEM;
1140 
1141     /* Create a gpiod lookup using gpiochip-local offsets */
1142     lookup = devm_kzalloc(&pdev->dev, struct_size(lookup, table, 3),
1143                   GFP_KERNEL);
1144     if (!lookup)
1145         return -ENOMEM;
1146 
1147     lookup->dev_id = "i2c-gpio";
1148     lookup->table[0] = (struct gpiod_lookup)
1149         GPIO_LOOKUP_IDX(iic->pin_sda < 32 ? "SM501-LOW" : "SM501-HIGH",
1150                 iic->pin_sda % 32, NULL, 0,
1151                 GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN);
1152     lookup->table[1] = (struct gpiod_lookup)
1153         GPIO_LOOKUP_IDX(iic->pin_scl < 32 ? "SM501-LOW" : "SM501-HIGH",
1154                 iic->pin_scl % 32, NULL, 1,
1155                 GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN);
1156     gpiod_add_lookup_table(lookup);
1157 
1158     icd = dev_get_platdata(&pdev->dev);
1159     icd->timeout = iic->timeout;
1160     icd->udelay = iic->udelay;
1161 
1162     /* note, we can't use either of the pin numbers, as the i2c-gpio
1163      * driver uses the platform.id field to generate the bus number
1164      * to register with the i2c core; The i2c core doesn't have enough
1165      * entries to deal with anything we currently use.
1166     */
1167 
1168     pdev->id = iic->bus_num;
1169 
1170     dev_info(sm->dev, "registering i2c-%d: sda=%d, scl=%d\n",
1171          iic->bus_num,
1172          iic->pin_sda, iic->pin_scl);
1173 
1174     return sm501_register_device(sm, pdev);
1175 }
1176 
1177 static int sm501_register_gpio_i2c(struct sm501_devdata *sm,
1178                    struct sm501_platdata *pdata)
1179 {
1180     struct sm501_platdata_gpio_i2c *iic = pdata->gpio_i2c;
1181     int index;
1182     int ret;
1183 
1184     for (index = 0; index < pdata->gpio_i2c_nr; index++, iic++) {
1185         ret = sm501_register_gpio_i2c_instance(sm, iic);
1186         if (ret < 0)
1187             return ret;
1188     }
1189 
1190     return 0;
1191 }
1192 
1193 /* dbg_regs_show
1194  *
1195  * Debug attribute to attach to parent device to show core registers
1196 */
1197 
1198 static ssize_t dbg_regs_show(struct device *dev,
1199                  struct device_attribute *attr, char *buff)
1200 {
1201     struct sm501_devdata *sm = dev_get_drvdata(dev) ;
1202     unsigned int reg;
1203     char *ptr = buff;
1204     int ret;
1205 
1206     for (reg = 0x00; reg < 0x70; reg += 4) {
1207         ret = sprintf(ptr, "%08x = %08x\n",
1208                   reg, smc501_readl(sm->regs + reg));
1209         ptr += ret;
1210     }
1211 
1212     return ptr - buff;
1213 }
1214 
1215 
1216 static DEVICE_ATTR_RO(dbg_regs);
1217 
1218 /* sm501_init_reg
1219  *
1220  * Helper function for the init code to setup a register
1221  *
1222  * clear the bits which are set in r->mask, and then set
1223  * the bits set in r->set.
1224 */
1225 
1226 static inline void sm501_init_reg(struct sm501_devdata *sm,
1227                   unsigned long reg,
1228                   struct sm501_reg_init *r)
1229 {
1230     unsigned long tmp;
1231 
1232     tmp = smc501_readl(sm->regs + reg);
1233     tmp &= ~r->mask;
1234     tmp |= r->set;
1235     smc501_writel(tmp, sm->regs + reg);
1236 }
1237 
1238 /* sm501_init_regs
1239  *
1240  * Setup core register values
1241 */
1242 
1243 static void sm501_init_regs(struct sm501_devdata *sm,
1244                 struct sm501_initdata *init)
1245 {
1246     sm501_misc_control(sm->dev,
1247                init->misc_control.set,
1248                init->misc_control.mask);
1249 
1250     sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing);
1251     sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low);
1252     sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high);
1253 
1254     if (init->m1xclk) {
1255         dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk);
1256         sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk);
1257     }
1258 
1259     if (init->mclk) {
1260         dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk);
1261         sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk);
1262     }
1263 
1264 }
1265 
1266 /* Check the PLL sources for the M1CLK and M1XCLK
1267  *
1268  * If the M1CLK and M1XCLKs are not sourced from the same PLL, then
1269  * there is a risk (see errata AB-5) that the SM501 will cease proper
1270  * function. If this happens, then it is likely the SM501 will
1271  * hang the system.
1272 */
1273 
1274 static int sm501_check_clocks(struct sm501_devdata *sm)
1275 {
1276     unsigned long pwrmode = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
1277     unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC);
1278     unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC);
1279 
1280     return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0));
1281 }
1282 
1283 static unsigned int sm501_mem_local[] = {
1284     [0] = 4*1024*1024,
1285     [1] = 8*1024*1024,
1286     [2] = 16*1024*1024,
1287     [3] = 32*1024*1024,
1288     [4] = 64*1024*1024,
1289     [5] = 2*1024*1024,
1290 };
1291 
1292 /* sm501_init_dev
1293  *
1294  * Common init code for an SM501
1295 */
1296 
1297 static int sm501_init_dev(struct sm501_devdata *sm)
1298 {
1299     struct sm501_initdata *idata;
1300     struct sm501_platdata *pdata;
1301     resource_size_t mem_avail;
1302     unsigned long dramctrl;
1303     unsigned long devid;
1304     int ret;
1305 
1306     mutex_init(&sm->clock_lock);
1307     spin_lock_init(&sm->reg_lock);
1308 
1309     INIT_LIST_HEAD(&sm->devices);
1310 
1311     devid = smc501_readl(sm->regs + SM501_DEVICEID);
1312 
1313     if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) {
1314         dev_err(sm->dev, "incorrect device id %08lx\n", devid);
1315         return -EINVAL;
1316     }
1317 
1318     /* disable irqs */
1319     smc501_writel(0, sm->regs + SM501_IRQ_MASK);
1320 
1321     dramctrl = smc501_readl(sm->regs + SM501_DRAM_CONTROL);
1322     mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7];
1323 
1324     dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n",
1325          sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq);
1326 
1327     sm->rev = devid & SM501_DEVICEID_REVMASK;
1328 
1329     sm501_dump_gate(sm);
1330 
1331     ret = device_create_file(sm->dev, &dev_attr_dbg_regs);
1332     if (ret)
1333         dev_err(sm->dev, "failed to create debug regs file\n");
1334 
1335     sm501_dump_clk(sm);
1336 
1337     /* check to see if we have some device initialisation */
1338 
1339     pdata = sm->platdata;
1340     idata = pdata ? pdata->init : NULL;
1341 
1342     if (idata) {
1343         sm501_init_regs(sm, idata);
1344 
1345         if (idata->devices & SM501_USE_USB_HOST)
1346             sm501_register_usbhost(sm, &mem_avail);
1347         if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1))
1348             sm501_register_uart(sm, idata->devices);
1349         if (idata->devices & SM501_USE_GPIO)
1350             sm501_register_gpio(sm);
1351     }
1352 
1353     if (pdata && pdata->gpio_i2c && pdata->gpio_i2c_nr > 0) {
1354         if (!sm501_gpio_isregistered(sm))
1355             dev_err(sm->dev, "no gpio available for i2c gpio.\n");
1356         else
1357             sm501_register_gpio_i2c(sm, pdata);
1358     }
1359 
1360     ret = sm501_check_clocks(sm);
1361     if (ret) {
1362         dev_err(sm->dev, "M1X and M clocks sourced from different "
1363                     "PLLs\n");
1364         return -EINVAL;
1365     }
1366 
1367     /* always create a framebuffer */
1368     sm501_register_display(sm, &mem_avail);
1369 
1370     return 0;
1371 }
1372 
1373 static int sm501_plat_probe(struct platform_device *dev)
1374 {
1375     struct sm501_devdata *sm;
1376     int ret;
1377 
1378     sm = kzalloc(sizeof(*sm), GFP_KERNEL);
1379     if (!sm) {
1380         ret = -ENOMEM;
1381         goto err1;
1382     }
1383 
1384     sm->dev = &dev->dev;
1385     sm->pdev_id = dev->id;
1386     sm->platdata = dev_get_platdata(&dev->dev);
1387 
1388     ret = platform_get_irq(dev, 0);
1389     if (ret < 0)
1390         goto err_res;
1391     sm->irq = ret;
1392 
1393     sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
1394     sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1395     if (!sm->io_res || !sm->mem_res) {
1396         dev_err(&dev->dev, "failed to get IO resource\n");
1397         ret = -ENOENT;
1398         goto err_res;
1399     }
1400 
1401     sm->regs_claim = request_mem_region(sm->io_res->start,
1402                         0x100, "sm501");
1403     if (!sm->regs_claim) {
1404         dev_err(&dev->dev, "cannot claim registers\n");
1405         ret = -EBUSY;
1406         goto err_res;
1407     }
1408 
1409     platform_set_drvdata(dev, sm);
1410 
1411     sm->regs = ioremap(sm->io_res->start, resource_size(sm->io_res));
1412     if (!sm->regs) {
1413         dev_err(&dev->dev, "cannot remap registers\n");
1414         ret = -EIO;
1415         goto err_claim;
1416     }
1417 
1418     ret = sm501_init_dev(sm);
1419     if (ret)
1420         goto err_unmap;
1421 
1422     return 0;
1423 
1424  err_unmap:
1425     iounmap(sm->regs);
1426  err_claim:
1427     release_mem_region(sm->io_res->start, 0x100);
1428  err_res:
1429     kfree(sm);
1430  err1:
1431     return ret;
1432 
1433 }
1434 
1435 #ifdef CONFIG_PM
1436 
1437 /* power management support */
1438 
1439 static void sm501_set_power(struct sm501_devdata *sm, int on)
1440 {
1441     struct sm501_platdata *pd = sm->platdata;
1442 
1443     if (!pd)
1444         return;
1445 
1446     if (pd->get_power) {
1447         if (pd->get_power(sm->dev) == on) {
1448             dev_dbg(sm->dev, "is already %d\n", on);
1449             return;
1450         }
1451     }
1452 
1453     if (pd->set_power) {
1454         dev_dbg(sm->dev, "setting power to %d\n", on);
1455 
1456         pd->set_power(sm->dev, on);
1457         sm501_mdelay(sm, 10);
1458     }
1459 }
1460 
1461 static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state)
1462 {
1463     struct sm501_devdata *sm = platform_get_drvdata(pdev);
1464 
1465     sm->in_suspend = 1;
1466     sm->pm_misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);
1467 
1468     sm501_dump_regs(sm);
1469 
1470     if (sm->platdata) {
1471         if (sm->platdata->flags & SM501_FLAG_SUSPEND_OFF)
1472             sm501_set_power(sm, 0);
1473     }
1474 
1475     return 0;
1476 }
1477 
1478 static int sm501_plat_resume(struct platform_device *pdev)
1479 {
1480     struct sm501_devdata *sm = platform_get_drvdata(pdev);
1481 
1482     sm501_set_power(sm, 1);
1483 
1484     sm501_dump_regs(sm);
1485     sm501_dump_gate(sm);
1486     sm501_dump_clk(sm);
1487 
1488     /* check to see if we are in the same state as when suspended */
1489 
1490     if (smc501_readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) {
1491         dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n");
1492         smc501_writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL);
1493 
1494         /* our suspend causes the controller state to change,
1495          * either by something attempting setup, power loss,
1496          * or an external reset event on power change */
1497 
1498         if (sm->platdata && sm->platdata->init) {
1499             sm501_init_regs(sm, sm->platdata->init);
1500         }
1501     }
1502 
1503     /* dump our state from resume */
1504 
1505     sm501_dump_regs(sm);
1506     sm501_dump_clk(sm);
1507 
1508     sm->in_suspend = 0;
1509 
1510     return 0;
1511 }
1512 #else
1513 #define sm501_plat_suspend NULL
1514 #define sm501_plat_resume NULL
1515 #endif
1516 
1517 /* Initialisation data for PCI devices */
1518 
1519 static struct sm501_initdata sm501_pci_initdata = {
1520     .gpio_high  = {
1521         .set    = 0x3F000000,       /* 24bit panel */
1522         .mask   = 0x0,
1523     },
1524     .misc_timing    = {
1525         .set    = 0x010100,     /* SDRAM timing */
1526         .mask   = 0x1F1F00,
1527     },
1528     .misc_control   = {
1529         .set    = SM501_MISC_PNL_24BIT,
1530         .mask   = 0,
1531     },
1532 
1533     .devices    = SM501_USE_ALL,
1534 
1535     /* Errata AB-3 says that 72MHz is the fastest available
1536      * for 33MHZ PCI with proper bus-mastering operation */
1537 
1538     .mclk       = 72 * MHZ,
1539     .m1xclk     = 144 * MHZ,
1540 };
1541 
1542 static struct sm501_platdata_fbsub sm501_pdata_fbsub = {
1543     .flags      = (SM501FB_FLAG_USE_INIT_MODE |
1544                SM501FB_FLAG_USE_HWCURSOR |
1545                SM501FB_FLAG_USE_HWACCEL |
1546                SM501FB_FLAG_DISABLE_AT_EXIT),
1547 };
1548 
1549 static struct sm501_platdata_fb sm501_fb_pdata = {
1550     .fb_route   = SM501_FB_OWN,
1551     .fb_crt     = &sm501_pdata_fbsub,
1552     .fb_pnl     = &sm501_pdata_fbsub,
1553 };
1554 
1555 static struct sm501_platdata sm501_pci_platdata = {
1556     .init       = &sm501_pci_initdata,
1557     .fb     = &sm501_fb_pdata,
1558     .gpio_base  = -1,
1559 };
1560 
1561 static int sm501_pci_probe(struct pci_dev *dev,
1562                      const struct pci_device_id *id)
1563 {
1564     struct sm501_devdata *sm;
1565     int err;
1566 
1567     sm = kzalloc(sizeof(*sm), GFP_KERNEL);
1568     if (!sm) {
1569         err = -ENOMEM;
1570         goto err1;
1571     }
1572 
1573     /* set a default set of platform data */
1574     dev->dev.platform_data = sm->platdata = &sm501_pci_platdata;
1575 
1576     /* set a hopefully unique id for our child platform devices */
1577     sm->pdev_id = 32 + dev->devfn;
1578 
1579     pci_set_drvdata(dev, sm);
1580 
1581     err = pci_enable_device(dev);
1582     if (err) {
1583         dev_err(&dev->dev, "cannot enable device\n");
1584         goto err2;
1585     }
1586 
1587     sm->dev = &dev->dev;
1588     sm->irq = dev->irq;
1589 
1590 #ifdef __BIG_ENDIAN
1591     /* if the system is big-endian, we most probably have a
1592      * translation in the IO layer making the PCI bus little endian
1593      * so make the framebuffer swapped pixels */
1594 
1595     sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN;
1596 #endif
1597 
1598     /* check our resources */
1599 
1600     if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) {
1601         dev_err(&dev->dev, "region #0 is not memory?\n");
1602         err = -EINVAL;
1603         goto err3;
1604     }
1605 
1606     if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) {
1607         dev_err(&dev->dev, "region #1 is not memory?\n");
1608         err = -EINVAL;
1609         goto err3;
1610     }
1611 
1612     /* make our resources ready for sharing */
1613 
1614     sm->io_res = &dev->resource[1];
1615     sm->mem_res = &dev->resource[0];
1616 
1617     sm->regs_claim = request_mem_region(sm->io_res->start,
1618                         0x100, "sm501");
1619     if (!sm->regs_claim) {
1620         dev_err(&dev->dev, "cannot claim registers\n");
1621         err= -EBUSY;
1622         goto err3;
1623     }
1624 
1625     sm->regs = pci_ioremap_bar(dev, 1);
1626     if (!sm->regs) {
1627         dev_err(&dev->dev, "cannot remap registers\n");
1628         err = -EIO;
1629         goto err4;
1630     }
1631 
1632     sm501_init_dev(sm);
1633     return 0;
1634 
1635  err4:
1636     release_mem_region(sm->io_res->start, 0x100);
1637  err3:
1638     pci_disable_device(dev);
1639  err2:
1640     kfree(sm);
1641  err1:
1642     return err;
1643 }
1644 
1645 static void sm501_remove_sub(struct sm501_devdata *sm,
1646                  struct sm501_device *smdev)
1647 {
1648     list_del(&smdev->list);
1649     platform_device_unregister(&smdev->pdev);
1650 }
1651 
1652 static void sm501_dev_remove(struct sm501_devdata *sm)
1653 {
1654     struct sm501_device *smdev, *tmp;
1655 
1656     list_for_each_entry_safe(smdev, tmp, &sm->devices, list)
1657         sm501_remove_sub(sm, smdev);
1658 
1659     device_remove_file(sm->dev, &dev_attr_dbg_regs);
1660 
1661     sm501_gpio_remove(sm);
1662 }
1663 
1664 static void sm501_pci_remove(struct pci_dev *dev)
1665 {
1666     struct sm501_devdata *sm = pci_get_drvdata(dev);
1667 
1668     sm501_dev_remove(sm);
1669     iounmap(sm->regs);
1670 
1671     release_mem_region(sm->io_res->start, 0x100);
1672 
1673     pci_disable_device(dev);
1674 }
1675 
1676 static int sm501_plat_remove(struct platform_device *dev)
1677 {
1678     struct sm501_devdata *sm = platform_get_drvdata(dev);
1679 
1680     sm501_dev_remove(sm);
1681     iounmap(sm->regs);
1682 
1683     release_mem_region(sm->io_res->start, 0x100);
1684 
1685     return 0;
1686 }
1687 
1688 static const struct pci_device_id sm501_pci_tbl[] = {
1689     { 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1690     { 0, },
1691 };
1692 
1693 MODULE_DEVICE_TABLE(pci, sm501_pci_tbl);
1694 
1695 static struct pci_driver sm501_pci_driver = {
1696     .name       = "sm501",
1697     .id_table   = sm501_pci_tbl,
1698     .probe      = sm501_pci_probe,
1699     .remove     = sm501_pci_remove,
1700 };
1701 
1702 MODULE_ALIAS("platform:sm501");
1703 
1704 static const struct of_device_id of_sm501_match_tbl[] = {
1705     { .compatible = "smi,sm501", },
1706     { /* end */ }
1707 };
1708 MODULE_DEVICE_TABLE(of, of_sm501_match_tbl);
1709 
1710 static struct platform_driver sm501_plat_driver = {
1711     .driver     = {
1712         .name   = "sm501",
1713         .of_match_table = of_sm501_match_tbl,
1714     },
1715     .probe      = sm501_plat_probe,
1716     .remove     = sm501_plat_remove,
1717     .suspend    = sm501_plat_suspend,
1718     .resume     = sm501_plat_resume,
1719 };
1720 
1721 static int __init sm501_base_init(void)
1722 {
1723     platform_driver_register(&sm501_plat_driver);
1724     return pci_register_driver(&sm501_pci_driver);
1725 }
1726 
1727 static void __exit sm501_base_exit(void)
1728 {
1729     platform_driver_unregister(&sm501_plat_driver);
1730     pci_unregister_driver(&sm501_pci_driver);
1731 }
1732 
1733 module_init(sm501_base_init);
1734 module_exit(sm501_base_exit);
1735 
1736 MODULE_DESCRIPTION("SM501 Core Driver");
1737 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders");
1738 MODULE_LICENSE("GPL v2");
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