drivers/mfd/rc5t583.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Core driver access RC5T583 power management chip.
0004  *
0005  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
0006  * Author: Laxman dewangan <ldewangan@nvidia.com>
0007  *
0008  * Based on code
0009  *  Copyright (C) 2011 RICOH COMPANY,LTD
0010  */
0011 #include <linux/interrupt.h>
0012 #include <linux/irq.h>
0013 #include <linux/kernel.h>
0014 #include <linux/init.h>
0015 #include <linux/err.h>
0016 #include <linux/slab.h>
0017 #include <linux/i2c.h>
0018 #include <linux/mfd/core.h>
0019 #include <linux/mfd/rc5t583.h>
0020 #include <linux/regmap.h>
0021
0022 #define RICOH_ONOFFSEL_REG  0x10
0023 #define RICOH_SWCTL_REG     0x5E
0024
0025 struct deepsleep_control_data {
0026     u8 reg_add;
0027     u8 ds_pos_bit;
0028 };
0029
0030 #define DEEPSLEEP_INIT(_id, _reg, _pos)     \
0031     {                   \
0032         .reg_add = RC5T583_##_reg,  \
0033         .ds_pos_bit = _pos,     \
0034     }
0035
0036 static struct deepsleep_control_data deepsleep_data[] = {
0037     DEEPSLEEP_INIT(DC0, SLPSEQ1, 0),
0038     DEEPSLEEP_INIT(DC1, SLPSEQ1, 4),
0039     DEEPSLEEP_INIT(DC2, SLPSEQ2, 0),
0040     DEEPSLEEP_INIT(DC3, SLPSEQ2, 4),
0041     DEEPSLEEP_INIT(LDO0, SLPSEQ3, 0),
0042     DEEPSLEEP_INIT(LDO1, SLPSEQ3, 4),
0043     DEEPSLEEP_INIT(LDO2, SLPSEQ4, 0),
0044     DEEPSLEEP_INIT(LDO3, SLPSEQ4, 4),
0045     DEEPSLEEP_INIT(LDO4, SLPSEQ5, 0),
0046     DEEPSLEEP_INIT(LDO5, SLPSEQ5, 4),
0047     DEEPSLEEP_INIT(LDO6, SLPSEQ6, 0),
0048     DEEPSLEEP_INIT(LDO7, SLPSEQ6, 4),
0049     DEEPSLEEP_INIT(LDO8, SLPSEQ7, 0),
0050     DEEPSLEEP_INIT(LDO9, SLPSEQ7, 4),
0051     DEEPSLEEP_INIT(PSO0, SLPSEQ8, 0),
0052     DEEPSLEEP_INIT(PSO1, SLPSEQ8, 4),
0053     DEEPSLEEP_INIT(PSO2, SLPSEQ9, 0),
0054     DEEPSLEEP_INIT(PSO3, SLPSEQ9, 4),
0055     DEEPSLEEP_INIT(PSO4, SLPSEQ10, 0),
0056     DEEPSLEEP_INIT(PSO5, SLPSEQ10, 4),
0057     DEEPSLEEP_INIT(PSO6, SLPSEQ11, 0),
0058     DEEPSLEEP_INIT(PSO7, SLPSEQ11, 4),
0059 };
0060
0061 #define EXT_PWR_REQ     \
0062     (RC5T583_EXT_PWRREQ1_CONTROL | RC5T583_EXT_PWRREQ2_CONTROL)
0063
0064 static const struct mfd_cell rc5t583_subdevs[] = {
0065     {.name = "rc5t583-gpio",},
0066     {.name = "rc5t583-regulator",},
0067     {.name = "rc5t583-rtc",      },
0068     {.name = "rc5t583-key",      }
0069 };
0070
0071 static int __rc5t583_set_ext_pwrreq1_control(struct device *dev,
0072     int id, int ext_pwr, int slots)
0073 {
0074     int ret;
0075     uint8_t sleepseq_val = 0;
0076     unsigned int en_bit;
0077     unsigned int slot_bit;
0078
0079     if (id == RC5T583_DS_DC0) {
0080         dev_err(dev, "PWRREQ1 is invalid control for rail %d\n", id);
0081         return -EINVAL;
0082     }
0083
0084     en_bit = deepsleep_data[id].ds_pos_bit;
0085     slot_bit = en_bit + 1;
0086     ret = rc5t583_read(dev, deepsleep_data[id].reg_add, &sleepseq_val);
0087     if (ret < 0) {
0088         dev_err(dev, "Error in reading reg 0x%x\n",
0089                 deepsleep_data[id].reg_add);
0090         return ret;
0091     }
0092
0093     sleepseq_val &= ~(0xF << en_bit);
0094     sleepseq_val |= BIT(en_bit);
0095     sleepseq_val |= ((slots & 0x7) << slot_bit);
0096     ret = rc5t583_set_bits(dev, RICOH_ONOFFSEL_REG, BIT(1));
0097     if (ret < 0) {
0098         dev_err(dev, "Error in updating the 0x%02x register\n",
0099                 RICOH_ONOFFSEL_REG);
0100         return ret;
0101     }
0102
0103     ret = rc5t583_write(dev, deepsleep_data[id].reg_add, sleepseq_val);
0104     if (ret < 0) {
0105         dev_err(dev, "Error in writing reg 0x%x\n",
0106                 deepsleep_data[id].reg_add);
0107         return ret;
0108     }
0109
0110     if (id == RC5T583_DS_LDO4) {
0111         ret = rc5t583_write(dev, RICOH_SWCTL_REG, 0x1);
0112         if (ret < 0)
0113             dev_err(dev, "Error in writing reg 0x%x\n",
0114                 RICOH_SWCTL_REG);
0115     }
0116     return ret;
0117 }
0118
0119 static int __rc5t583_set_ext_pwrreq2_control(struct device *dev,
0120     int id, int ext_pwr)
0121 {
0122     int ret;
0123
0124     if (id != RC5T583_DS_DC0) {
0125         dev_err(dev, "PWRREQ2 is invalid control for rail %d\n", id);
0126         return -EINVAL;
0127     }
0128
0129     ret = rc5t583_set_bits(dev, RICOH_ONOFFSEL_REG, BIT(2));
0130     if (ret < 0)
0131         dev_err(dev, "Error in updating the ONOFFSEL 0x10 register\n");
0132     return ret;
0133 }
0134
0135 int rc5t583_ext_power_req_config(struct device *dev, int ds_id,
0136     int ext_pwr_req, int deepsleep_slot_nr)
0137 {
0138     if ((ext_pwr_req & EXT_PWR_REQ) == EXT_PWR_REQ)
0139         return -EINVAL;
0140
0141     if (ext_pwr_req & RC5T583_EXT_PWRREQ1_CONTROL)
0142         return __rc5t583_set_ext_pwrreq1_control(dev, ds_id,
0143                 ext_pwr_req, deepsleep_slot_nr);
0144
0145     if (ext_pwr_req & RC5T583_EXT_PWRREQ2_CONTROL)
0146         return __rc5t583_set_ext_pwrreq2_control(dev,
0147             ds_id, ext_pwr_req);
0148     return 0;
0149 }
0150 EXPORT_SYMBOL(rc5t583_ext_power_req_config);
0151
0152 static int rc5t583_clear_ext_power_req(struct rc5t583 *rc5t583,
0153     struct rc5t583_platform_data *pdata)
0154 {
0155     int ret;
0156     int i;
0157     uint8_t on_off_val = 0;
0158
0159     /*  Clear ONOFFSEL register */
0160     if (pdata->enable_shutdown)
0161         on_off_val = 0x1;
0162
0163     ret = rc5t583_write(rc5t583->dev, RICOH_ONOFFSEL_REG, on_off_val);
0164     if (ret < 0)
0165         dev_warn(rc5t583->dev, "Error in writing reg %d error: %d\n",
0166                     RICOH_ONOFFSEL_REG, ret);
0167
0168     ret = rc5t583_write(rc5t583->dev, RICOH_SWCTL_REG, 0x0);
0169     if (ret < 0)
0170         dev_warn(rc5t583->dev, "Error in writing reg %d error: %d\n",
0171                     RICOH_SWCTL_REG, ret);
0172
0173     /* Clear sleep sequence register */
0174     for (i = RC5T583_SLPSEQ1; i <= RC5T583_SLPSEQ11; ++i) {
0175         ret = rc5t583_write(rc5t583->dev, i, 0x0);
0176         if (ret < 0)
0177             dev_warn(rc5t583->dev,
0178                 "Error in writing reg 0x%02x error: %d\n",
0179                 i, ret);
0180     }
0181     return 0;
0182 }
0183
0184 static bool volatile_reg(struct device *dev, unsigned int reg)
0185 {
0186     /* Enable caching in interrupt registers */
0187     switch (reg) {
0188     case RC5T583_INT_EN_SYS1:
0189     case RC5T583_INT_EN_SYS2:
0190     case RC5T583_INT_EN_DCDC:
0191     case RC5T583_INT_EN_RTC:
0192     case RC5T583_INT_EN_ADC1:
0193     case RC5T583_INT_EN_ADC2:
0194     case RC5T583_INT_EN_ADC3:
0195     case RC5T583_GPIO_GPEDGE1:
0196     case RC5T583_GPIO_GPEDGE2:
0197     case RC5T583_GPIO_EN_INT:
0198         return false;
0199
0200     case RC5T583_GPIO_MON_IOIN:
0201         /* This is gpio input register */
0202         return true;
0203
0204     default:
0205         /* Enable caching in gpio registers */
0206         if ((reg >= RC5T583_GPIO_IOSEL) &&
0207                 (reg <= RC5T583_GPIO_GPOFUNC))
0208             return false;
0209
0210         /* Enable caching in sleep seq registers */
0211         if ((reg >= RC5T583_SLPSEQ1) && (reg <= RC5T583_SLPSEQ11))
0212             return false;
0213
0214         /* Enable caching of regulator registers */
0215         if ((reg >= RC5T583_REG_DC0CTL) && (reg <= RC5T583_REG_SR3CTL))
0216             return false;
0217         if ((reg >= RC5T583_REG_LDOEN1) &&
0218                     (reg <= RC5T583_REG_LDO9DAC_DS))
0219             return false;
0220
0221         break;
0222     }
0223
0224     return true;
0225 }
0226
0227 static const struct regmap_config rc5t583_regmap_config = {
0228     .reg_bits = 8,
0229     .val_bits = 8,
0230     .volatile_reg = volatile_reg,
0231     .max_register = RC5T583_MAX_REG,
0232     .num_reg_defaults_raw = RC5T583_NUM_REGS,
0233     .cache_type = REGCACHE_RBTREE,
0234 };
0235
0236 static int rc5t583_i2c_probe(struct i2c_client *i2c,
0237                   const struct i2c_device_id *id)
0238 {
0239     struct rc5t583 *rc5t583;
0240     struct rc5t583_platform_data *pdata = dev_get_platdata(&i2c->dev);
0241     int ret;
0242
0243     if (!pdata) {
0244         dev_err(&i2c->dev, "Err: Platform data not found\n");
0245         return -EINVAL;
0246     }
0247
0248     rc5t583 = devm_kzalloc(&i2c->dev, sizeof(*rc5t583), GFP_KERNEL);
0249     if (!rc5t583)
0250         return -ENOMEM;
0251
0252     rc5t583->dev = &i2c->dev;
0253     i2c_set_clientdata(i2c, rc5t583);
0254
0255     rc5t583->regmap = devm_regmap_init_i2c(i2c, &rc5t583_regmap_config);
0256     if (IS_ERR(rc5t583->regmap)) {
0257         ret = PTR_ERR(rc5t583->regmap);
0258         dev_err(&i2c->dev, "regmap initialization failed: %d\n", ret);
0259         return ret;
0260     }
0261
0262     ret = rc5t583_clear_ext_power_req(rc5t583, pdata);
0263     if (ret < 0)
0264         return ret;
0265
0266     if (i2c->irq) {
0267         ret = rc5t583_irq_init(rc5t583, i2c->irq, pdata->irq_base);
0268         /* Still continue with warning, if irq init fails */
0269         if (ret)
0270             dev_warn(&i2c->dev, "IRQ init failed: %d\n", ret);
0271     }
0272
0273     ret = devm_mfd_add_devices(rc5t583->dev, -1, rc5t583_subdevs,
0274                    ARRAY_SIZE(rc5t583_subdevs), NULL, 0, NULL);
0275     if (ret) {
0276         dev_err(&i2c->dev, "add mfd devices failed: %d\n", ret);
0277         return ret;
0278     }
0279
0280     return 0;
0281 }
0282
0283 static const struct i2c_device_id rc5t583_i2c_id[] = {
0284     {.name = "rc5t583", .driver_data = 0},
0285     {}
0286 };
0287
0288 static struct i2c_driver rc5t583_i2c_driver = {
0289     .driver = {
0290            .name = "rc5t583",
0291            },
0292     .probe = rc5t583_i2c_probe,
0293     .id_table = rc5t583_i2c_id,
0294 };
0295
0296 static int __init rc5t583_i2c_init(void)
0297 {
0298     return i2c_add_driver(&rc5t583_i2c_driver);
0299 }
0300 subsys_initcall(rc5t583_i2c_init);