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0008 #include <linux/module.h>
0009 #include <linux/platform_device.h>
0010 #include <linux/of_platform.h>
0011 #include <linux/io.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/mfd/qcom_rpm.h>
0014 #include <linux/mfd/syscon.h>
0015 #include <linux/regmap.h>
0016 #include <linux/clk.h>
0017
0018 #include <dt-bindings/mfd/qcom-rpm.h>
0019
0020 struct qcom_rpm_resource {
0021 unsigned target_id;
0022 unsigned status_id;
0023 unsigned select_id;
0024 unsigned size;
0025 };
0026
0027 struct qcom_rpm_data {
0028 u32 version;
0029 const struct qcom_rpm_resource *resource_table;
0030 unsigned int n_resources;
0031 unsigned int req_ctx_off;
0032 unsigned int req_sel_off;
0033 unsigned int ack_ctx_off;
0034 unsigned int ack_sel_off;
0035 unsigned int req_sel_size;
0036 unsigned int ack_sel_size;
0037 };
0038
0039 struct qcom_rpm {
0040 struct device *dev;
0041 struct regmap *ipc_regmap;
0042 unsigned ipc_offset;
0043 unsigned ipc_bit;
0044 struct clk *ramclk;
0045
0046 struct completion ack;
0047 struct mutex lock;
0048
0049 void __iomem *status_regs;
0050 void __iomem *ctrl_regs;
0051 void __iomem *req_regs;
0052
0053 u32 ack_status;
0054
0055 const struct qcom_rpm_data *data;
0056 };
0057
0058 #define RPM_STATUS_REG(rpm, i) ((rpm)->status_regs + (i) * 4)
0059 #define RPM_CTRL_REG(rpm, i) ((rpm)->ctrl_regs + (i) * 4)
0060 #define RPM_REQ_REG(rpm, i) ((rpm)->req_regs + (i) * 4)
0061
0062 #define RPM_REQUEST_TIMEOUT (5 * HZ)
0063
0064 #define RPM_MAX_SEL_SIZE 7
0065
0066 #define RPM_NOTIFICATION BIT(30)
0067 #define RPM_REJECTED BIT(31)
0068
0069 static const struct qcom_rpm_resource apq8064_rpm_resource_table[] = {
0070 [QCOM_RPM_CXO_CLK] = { 25, 9, 5, 1 },
0071 [QCOM_RPM_PXO_CLK] = { 26, 10, 6, 1 },
0072 [QCOM_RPM_APPS_FABRIC_CLK] = { 27, 11, 8, 1 },
0073 [QCOM_RPM_SYS_FABRIC_CLK] = { 28, 12, 9, 1 },
0074 [QCOM_RPM_MM_FABRIC_CLK] = { 29, 13, 10, 1 },
0075 [QCOM_RPM_DAYTONA_FABRIC_CLK] = { 30, 14, 11, 1 },
0076 [QCOM_RPM_SFPB_CLK] = { 31, 15, 12, 1 },
0077 [QCOM_RPM_CFPB_CLK] = { 32, 16, 13, 1 },
0078 [QCOM_RPM_MMFPB_CLK] = { 33, 17, 14, 1 },
0079 [QCOM_RPM_EBI1_CLK] = { 34, 18, 16, 1 },
0080 [QCOM_RPM_APPS_FABRIC_HALT] = { 35, 19, 18, 1 },
0081 [QCOM_RPM_APPS_FABRIC_MODE] = { 37, 20, 19, 1 },
0082 [QCOM_RPM_APPS_FABRIC_IOCTL] = { 40, 21, 20, 1 },
0083 [QCOM_RPM_APPS_FABRIC_ARB] = { 41, 22, 21, 12 },
0084 [QCOM_RPM_SYS_FABRIC_HALT] = { 53, 23, 22, 1 },
0085 [QCOM_RPM_SYS_FABRIC_MODE] = { 55, 24, 23, 1 },
0086 [QCOM_RPM_SYS_FABRIC_IOCTL] = { 58, 25, 24, 1 },
0087 [QCOM_RPM_SYS_FABRIC_ARB] = { 59, 26, 25, 30 },
0088 [QCOM_RPM_MM_FABRIC_HALT] = { 89, 27, 26, 1 },
0089 [QCOM_RPM_MM_FABRIC_MODE] = { 91, 28, 27, 1 },
0090 [QCOM_RPM_MM_FABRIC_IOCTL] = { 94, 29, 28, 1 },
0091 [QCOM_RPM_MM_FABRIC_ARB] = { 95, 30, 29, 21 },
0092 [QCOM_RPM_PM8921_SMPS1] = { 116, 31, 30, 2 },
0093 [QCOM_RPM_PM8921_SMPS2] = { 118, 33, 31, 2 },
0094 [QCOM_RPM_PM8921_SMPS3] = { 120, 35, 32, 2 },
0095 [QCOM_RPM_PM8921_SMPS4] = { 122, 37, 33, 2 },
0096 [QCOM_RPM_PM8921_SMPS5] = { 124, 39, 34, 2 },
0097 [QCOM_RPM_PM8921_SMPS6] = { 126, 41, 35, 2 },
0098 [QCOM_RPM_PM8921_SMPS7] = { 128, 43, 36, 2 },
0099 [QCOM_RPM_PM8921_SMPS8] = { 130, 45, 37, 2 },
0100 [QCOM_RPM_PM8921_LDO1] = { 132, 47, 38, 2 },
0101 [QCOM_RPM_PM8921_LDO2] = { 134, 49, 39, 2 },
0102 [QCOM_RPM_PM8921_LDO3] = { 136, 51, 40, 2 },
0103 [QCOM_RPM_PM8921_LDO4] = { 138, 53, 41, 2 },
0104 [QCOM_RPM_PM8921_LDO5] = { 140, 55, 42, 2 },
0105 [QCOM_RPM_PM8921_LDO6] = { 142, 57, 43, 2 },
0106 [QCOM_RPM_PM8921_LDO7] = { 144, 59, 44, 2 },
0107 [QCOM_RPM_PM8921_LDO8] = { 146, 61, 45, 2 },
0108 [QCOM_RPM_PM8921_LDO9] = { 148, 63, 46, 2 },
0109 [QCOM_RPM_PM8921_LDO10] = { 150, 65, 47, 2 },
0110 [QCOM_RPM_PM8921_LDO11] = { 152, 67, 48, 2 },
0111 [QCOM_RPM_PM8921_LDO12] = { 154, 69, 49, 2 },
0112 [QCOM_RPM_PM8921_LDO13] = { 156, 71, 50, 2 },
0113 [QCOM_RPM_PM8921_LDO14] = { 158, 73, 51, 2 },
0114 [QCOM_RPM_PM8921_LDO15] = { 160, 75, 52, 2 },
0115 [QCOM_RPM_PM8921_LDO16] = { 162, 77, 53, 2 },
0116 [QCOM_RPM_PM8921_LDO17] = { 164, 79, 54, 2 },
0117 [QCOM_RPM_PM8921_LDO18] = { 166, 81, 55, 2 },
0118 [QCOM_RPM_PM8921_LDO19] = { 168, 83, 56, 2 },
0119 [QCOM_RPM_PM8921_LDO20] = { 170, 85, 57, 2 },
0120 [QCOM_RPM_PM8921_LDO21] = { 172, 87, 58, 2 },
0121 [QCOM_RPM_PM8921_LDO22] = { 174, 89, 59, 2 },
0122 [QCOM_RPM_PM8921_LDO23] = { 176, 91, 60, 2 },
0123 [QCOM_RPM_PM8921_LDO24] = { 178, 93, 61, 2 },
0124 [QCOM_RPM_PM8921_LDO25] = { 180, 95, 62, 2 },
0125 [QCOM_RPM_PM8921_LDO26] = { 182, 97, 63, 2 },
0126 [QCOM_RPM_PM8921_LDO27] = { 184, 99, 64, 2 },
0127 [QCOM_RPM_PM8921_LDO28] = { 186, 101, 65, 2 },
0128 [QCOM_RPM_PM8921_LDO29] = { 188, 103, 66, 2 },
0129 [QCOM_RPM_PM8921_CLK1] = { 190, 105, 67, 2 },
0130 [QCOM_RPM_PM8921_CLK2] = { 192, 107, 68, 2 },
0131 [QCOM_RPM_PM8921_LVS1] = { 194, 109, 69, 1 },
0132 [QCOM_RPM_PM8921_LVS2] = { 195, 110, 70, 1 },
0133 [QCOM_RPM_PM8921_LVS3] = { 196, 111, 71, 1 },
0134 [QCOM_RPM_PM8921_LVS4] = { 197, 112, 72, 1 },
0135 [QCOM_RPM_PM8921_LVS5] = { 198, 113, 73, 1 },
0136 [QCOM_RPM_PM8921_LVS6] = { 199, 114, 74, 1 },
0137 [QCOM_RPM_PM8921_LVS7] = { 200, 115, 75, 1 },
0138 [QCOM_RPM_PM8821_SMPS1] = { 201, 116, 76, 2 },
0139 [QCOM_RPM_PM8821_SMPS2] = { 203, 118, 77, 2 },
0140 [QCOM_RPM_PM8821_LDO1] = { 205, 120, 78, 2 },
0141 [QCOM_RPM_PM8921_NCP] = { 207, 122, 80, 2 },
0142 [QCOM_RPM_CXO_BUFFERS] = { 209, 124, 81, 1 },
0143 [QCOM_RPM_USB_OTG_SWITCH] = { 210, 125, 82, 1 },
0144 [QCOM_RPM_HDMI_SWITCH] = { 211, 126, 83, 1 },
0145 [QCOM_RPM_DDR_DMM] = { 212, 127, 84, 2 },
0146 [QCOM_RPM_QDSS_CLK] = { 214, ~0, 7, 1 },
0147 [QCOM_RPM_VDDMIN_GPIO] = { 215, 131, 89, 1 },
0148 };
0149
0150 static const struct qcom_rpm_data apq8064_template = {
0151 .version = 3,
0152 .resource_table = apq8064_rpm_resource_table,
0153 .n_resources = ARRAY_SIZE(apq8064_rpm_resource_table),
0154 .req_ctx_off = 3,
0155 .req_sel_off = 11,
0156 .ack_ctx_off = 15,
0157 .ack_sel_off = 23,
0158 .req_sel_size = 4,
0159 .ack_sel_size = 7,
0160 };
0161
0162 static const struct qcom_rpm_resource msm8660_rpm_resource_table[] = {
0163 [QCOM_RPM_CXO_CLK] = { 32, 12, 5, 1 },
0164 [QCOM_RPM_PXO_CLK] = { 33, 13, 6, 1 },
0165 [QCOM_RPM_PLL_4] = { 34, 14, 7, 1 },
0166 [QCOM_RPM_APPS_FABRIC_CLK] = { 35, 15, 8, 1 },
0167 [QCOM_RPM_SYS_FABRIC_CLK] = { 36, 16, 9, 1 },
0168 [QCOM_RPM_MM_FABRIC_CLK] = { 37, 17, 10, 1 },
0169 [QCOM_RPM_DAYTONA_FABRIC_CLK] = { 38, 18, 11, 1 },
0170 [QCOM_RPM_SFPB_CLK] = { 39, 19, 12, 1 },
0171 [QCOM_RPM_CFPB_CLK] = { 40, 20, 13, 1 },
0172 [QCOM_RPM_MMFPB_CLK] = { 41, 21, 14, 1 },
0173 [QCOM_RPM_SMI_CLK] = { 42, 22, 15, 1 },
0174 [QCOM_RPM_EBI1_CLK] = { 43, 23, 16, 1 },
0175 [QCOM_RPM_APPS_L2_CACHE_CTL] = { 44, 24, 17, 1 },
0176 [QCOM_RPM_APPS_FABRIC_HALT] = { 45, 25, 18, 2 },
0177 [QCOM_RPM_APPS_FABRIC_MODE] = { 47, 26, 19, 3 },
0178 [QCOM_RPM_APPS_FABRIC_ARB] = { 51, 28, 21, 6 },
0179 [QCOM_RPM_SYS_FABRIC_HALT] = { 63, 29, 22, 2 },
0180 [QCOM_RPM_SYS_FABRIC_MODE] = { 65, 30, 23, 3 },
0181 [QCOM_RPM_SYS_FABRIC_ARB] = { 69, 32, 25, 22 },
0182 [QCOM_RPM_MM_FABRIC_HALT] = { 105, 33, 26, 2 },
0183 [QCOM_RPM_MM_FABRIC_MODE] = { 107, 34, 27, 3 },
0184 [QCOM_RPM_MM_FABRIC_ARB] = { 111, 36, 29, 23 },
0185 [QCOM_RPM_PM8901_SMPS0] = { 134, 37, 30, 2 },
0186 [QCOM_RPM_PM8901_SMPS1] = { 136, 39, 31, 2 },
0187 [QCOM_RPM_PM8901_SMPS2] = { 138, 41, 32, 2 },
0188 [QCOM_RPM_PM8901_SMPS3] = { 140, 43, 33, 2 },
0189 [QCOM_RPM_PM8901_SMPS4] = { 142, 45, 34, 2 },
0190 [QCOM_RPM_PM8901_LDO0] = { 144, 47, 35, 2 },
0191 [QCOM_RPM_PM8901_LDO1] = { 146, 49, 36, 2 },
0192 [QCOM_RPM_PM8901_LDO2] = { 148, 51, 37, 2 },
0193 [QCOM_RPM_PM8901_LDO3] = { 150, 53, 38, 2 },
0194 [QCOM_RPM_PM8901_LDO4] = { 152, 55, 39, 2 },
0195 [QCOM_RPM_PM8901_LDO5] = { 154, 57, 40, 2 },
0196 [QCOM_RPM_PM8901_LDO6] = { 156, 59, 41, 2 },
0197 [QCOM_RPM_PM8901_LVS0] = { 158, 61, 42, 1 },
0198 [QCOM_RPM_PM8901_LVS1] = { 159, 62, 43, 1 },
0199 [QCOM_RPM_PM8901_LVS2] = { 160, 63, 44, 1 },
0200 [QCOM_RPM_PM8901_LVS3] = { 161, 64, 45, 1 },
0201 [QCOM_RPM_PM8901_MVS] = { 162, 65, 46, 1 },
0202 [QCOM_RPM_PM8058_SMPS0] = { 163, 66, 47, 2 },
0203 [QCOM_RPM_PM8058_SMPS1] = { 165, 68, 48, 2 },
0204 [QCOM_RPM_PM8058_SMPS2] = { 167, 70, 49, 2 },
0205 [QCOM_RPM_PM8058_SMPS3] = { 169, 72, 50, 2 },
0206 [QCOM_RPM_PM8058_SMPS4] = { 171, 74, 51, 2 },
0207 [QCOM_RPM_PM8058_LDO0] = { 173, 76, 52, 2 },
0208 [QCOM_RPM_PM8058_LDO1] = { 175, 78, 53, 2 },
0209 [QCOM_RPM_PM8058_LDO2] = { 177, 80, 54, 2 },
0210 [QCOM_RPM_PM8058_LDO3] = { 179, 82, 55, 2 },
0211 [QCOM_RPM_PM8058_LDO4] = { 181, 84, 56, 2 },
0212 [QCOM_RPM_PM8058_LDO5] = { 183, 86, 57, 2 },
0213 [QCOM_RPM_PM8058_LDO6] = { 185, 88, 58, 2 },
0214 [QCOM_RPM_PM8058_LDO7] = { 187, 90, 59, 2 },
0215 [QCOM_RPM_PM8058_LDO8] = { 189, 92, 60, 2 },
0216 [QCOM_RPM_PM8058_LDO9] = { 191, 94, 61, 2 },
0217 [QCOM_RPM_PM8058_LDO10] = { 193, 96, 62, 2 },
0218 [QCOM_RPM_PM8058_LDO11] = { 195, 98, 63, 2 },
0219 [QCOM_RPM_PM8058_LDO12] = { 197, 100, 64, 2 },
0220 [QCOM_RPM_PM8058_LDO13] = { 199, 102, 65, 2 },
0221 [QCOM_RPM_PM8058_LDO14] = { 201, 104, 66, 2 },
0222 [QCOM_RPM_PM8058_LDO15] = { 203, 106, 67, 2 },
0223 [QCOM_RPM_PM8058_LDO16] = { 205, 108, 68, 2 },
0224 [QCOM_RPM_PM8058_LDO17] = { 207, 110, 69, 2 },
0225 [QCOM_RPM_PM8058_LDO18] = { 209, 112, 70, 2 },
0226 [QCOM_RPM_PM8058_LDO19] = { 211, 114, 71, 2 },
0227 [QCOM_RPM_PM8058_LDO20] = { 213, 116, 72, 2 },
0228 [QCOM_RPM_PM8058_LDO21] = { 215, 118, 73, 2 },
0229 [QCOM_RPM_PM8058_LDO22] = { 217, 120, 74, 2 },
0230 [QCOM_RPM_PM8058_LDO23] = { 219, 122, 75, 2 },
0231 [QCOM_RPM_PM8058_LDO24] = { 221, 124, 76, 2 },
0232 [QCOM_RPM_PM8058_LDO25] = { 223, 126, 77, 2 },
0233 [QCOM_RPM_PM8058_LVS0] = { 225, 128, 78, 1 },
0234 [QCOM_RPM_PM8058_LVS1] = { 226, 129, 79, 1 },
0235 [QCOM_RPM_PM8058_NCP] = { 227, 130, 80, 2 },
0236 [QCOM_RPM_CXO_BUFFERS] = { 229, 132, 81, 1 },
0237 };
0238
0239 static const struct qcom_rpm_data msm8660_template = {
0240 .version = 2,
0241 .resource_table = msm8660_rpm_resource_table,
0242 .n_resources = ARRAY_SIZE(msm8660_rpm_resource_table),
0243 .req_ctx_off = 3,
0244 .req_sel_off = 11,
0245 .ack_ctx_off = 19,
0246 .ack_sel_off = 27,
0247 .req_sel_size = 7,
0248 .ack_sel_size = 7,
0249 };
0250
0251 static const struct qcom_rpm_resource msm8960_rpm_resource_table[] = {
0252 [QCOM_RPM_CXO_CLK] = { 25, 9, 5, 1 },
0253 [QCOM_RPM_PXO_CLK] = { 26, 10, 6, 1 },
0254 [QCOM_RPM_APPS_FABRIC_CLK] = { 27, 11, 8, 1 },
0255 [QCOM_RPM_SYS_FABRIC_CLK] = { 28, 12, 9, 1 },
0256 [QCOM_RPM_MM_FABRIC_CLK] = { 29, 13, 10, 1 },
0257 [QCOM_RPM_DAYTONA_FABRIC_CLK] = { 30, 14, 11, 1 },
0258 [QCOM_RPM_SFPB_CLK] = { 31, 15, 12, 1 },
0259 [QCOM_RPM_CFPB_CLK] = { 32, 16, 13, 1 },
0260 [QCOM_RPM_MMFPB_CLK] = { 33, 17, 14, 1 },
0261 [QCOM_RPM_EBI1_CLK] = { 34, 18, 16, 1 },
0262 [QCOM_RPM_APPS_FABRIC_HALT] = { 35, 19, 18, 1 },
0263 [QCOM_RPM_APPS_FABRIC_MODE] = { 37, 20, 19, 1 },
0264 [QCOM_RPM_APPS_FABRIC_IOCTL] = { 40, 21, 20, 1 },
0265 [QCOM_RPM_APPS_FABRIC_ARB] = { 41, 22, 21, 12 },
0266 [QCOM_RPM_SYS_FABRIC_HALT] = { 53, 23, 22, 1 },
0267 [QCOM_RPM_SYS_FABRIC_MODE] = { 55, 24, 23, 1 },
0268 [QCOM_RPM_SYS_FABRIC_IOCTL] = { 58, 25, 24, 1 },
0269 [QCOM_RPM_SYS_FABRIC_ARB] = { 59, 26, 25, 29 },
0270 [QCOM_RPM_MM_FABRIC_HALT] = { 88, 27, 26, 1 },
0271 [QCOM_RPM_MM_FABRIC_MODE] = { 90, 28, 27, 1 },
0272 [QCOM_RPM_MM_FABRIC_IOCTL] = { 93, 29, 28, 1 },
0273 [QCOM_RPM_MM_FABRIC_ARB] = { 94, 30, 29, 23 },
0274 [QCOM_RPM_PM8921_SMPS1] = { 117, 31, 30, 2 },
0275 [QCOM_RPM_PM8921_SMPS2] = { 119, 33, 31, 2 },
0276 [QCOM_RPM_PM8921_SMPS3] = { 121, 35, 32, 2 },
0277 [QCOM_RPM_PM8921_SMPS4] = { 123, 37, 33, 2 },
0278 [QCOM_RPM_PM8921_SMPS5] = { 125, 39, 34, 2 },
0279 [QCOM_RPM_PM8921_SMPS6] = { 127, 41, 35, 2 },
0280 [QCOM_RPM_PM8921_SMPS7] = { 129, 43, 36, 2 },
0281 [QCOM_RPM_PM8921_SMPS8] = { 131, 45, 37, 2 },
0282 [QCOM_RPM_PM8921_LDO1] = { 133, 47, 38, 2 },
0283 [QCOM_RPM_PM8921_LDO2] = { 135, 49, 39, 2 },
0284 [QCOM_RPM_PM8921_LDO3] = { 137, 51, 40, 2 },
0285 [QCOM_RPM_PM8921_LDO4] = { 139, 53, 41, 2 },
0286 [QCOM_RPM_PM8921_LDO5] = { 141, 55, 42, 2 },
0287 [QCOM_RPM_PM8921_LDO6] = { 143, 57, 43, 2 },
0288 [QCOM_RPM_PM8921_LDO7] = { 145, 59, 44, 2 },
0289 [QCOM_RPM_PM8921_LDO8] = { 147, 61, 45, 2 },
0290 [QCOM_RPM_PM8921_LDO9] = { 149, 63, 46, 2 },
0291 [QCOM_RPM_PM8921_LDO10] = { 151, 65, 47, 2 },
0292 [QCOM_RPM_PM8921_LDO11] = { 153, 67, 48, 2 },
0293 [QCOM_RPM_PM8921_LDO12] = { 155, 69, 49, 2 },
0294 [QCOM_RPM_PM8921_LDO13] = { 157, 71, 50, 2 },
0295 [QCOM_RPM_PM8921_LDO14] = { 159, 73, 51, 2 },
0296 [QCOM_RPM_PM8921_LDO15] = { 161, 75, 52, 2 },
0297 [QCOM_RPM_PM8921_LDO16] = { 163, 77, 53, 2 },
0298 [QCOM_RPM_PM8921_LDO17] = { 165, 79, 54, 2 },
0299 [QCOM_RPM_PM8921_LDO18] = { 167, 81, 55, 2 },
0300 [QCOM_RPM_PM8921_LDO19] = { 169, 83, 56, 2 },
0301 [QCOM_RPM_PM8921_LDO20] = { 171, 85, 57, 2 },
0302 [QCOM_RPM_PM8921_LDO21] = { 173, 87, 58, 2 },
0303 [QCOM_RPM_PM8921_LDO22] = { 175, 89, 59, 2 },
0304 [QCOM_RPM_PM8921_LDO23] = { 177, 91, 60, 2 },
0305 [QCOM_RPM_PM8921_LDO24] = { 179, 93, 61, 2 },
0306 [QCOM_RPM_PM8921_LDO25] = { 181, 95, 62, 2 },
0307 [QCOM_RPM_PM8921_LDO26] = { 183, 97, 63, 2 },
0308 [QCOM_RPM_PM8921_LDO27] = { 185, 99, 64, 2 },
0309 [QCOM_RPM_PM8921_LDO28] = { 187, 101, 65, 2 },
0310 [QCOM_RPM_PM8921_LDO29] = { 189, 103, 66, 2 },
0311 [QCOM_RPM_PM8921_CLK1] = { 191, 105, 67, 2 },
0312 [QCOM_RPM_PM8921_CLK2] = { 193, 107, 68, 2 },
0313 [QCOM_RPM_PM8921_LVS1] = { 195, 109, 69, 1 },
0314 [QCOM_RPM_PM8921_LVS2] = { 196, 110, 70, 1 },
0315 [QCOM_RPM_PM8921_LVS3] = { 197, 111, 71, 1 },
0316 [QCOM_RPM_PM8921_LVS4] = { 198, 112, 72, 1 },
0317 [QCOM_RPM_PM8921_LVS5] = { 199, 113, 73, 1 },
0318 [QCOM_RPM_PM8921_LVS6] = { 200, 114, 74, 1 },
0319 [QCOM_RPM_PM8921_LVS7] = { 201, 115, 75, 1 },
0320 [QCOM_RPM_PM8921_NCP] = { 202, 116, 80, 2 },
0321 [QCOM_RPM_CXO_BUFFERS] = { 204, 118, 81, 1 },
0322 [QCOM_RPM_USB_OTG_SWITCH] = { 205, 119, 82, 1 },
0323 [QCOM_RPM_HDMI_SWITCH] = { 206, 120, 83, 1 },
0324 [QCOM_RPM_DDR_DMM] = { 207, 121, 84, 2 },
0325 };
0326
0327 static const struct qcom_rpm_data msm8960_template = {
0328 .version = 3,
0329 .resource_table = msm8960_rpm_resource_table,
0330 .n_resources = ARRAY_SIZE(msm8960_rpm_resource_table),
0331 .req_ctx_off = 3,
0332 .req_sel_off = 11,
0333 .ack_ctx_off = 15,
0334 .ack_sel_off = 23,
0335 .req_sel_size = 4,
0336 .ack_sel_size = 7,
0337 };
0338
0339 static const struct qcom_rpm_resource ipq806x_rpm_resource_table[] = {
0340 [QCOM_RPM_CXO_CLK] = { 25, 9, 5, 1 },
0341 [QCOM_RPM_PXO_CLK] = { 26, 10, 6, 1 },
0342 [QCOM_RPM_APPS_FABRIC_CLK] = { 27, 11, 8, 1 },
0343 [QCOM_RPM_SYS_FABRIC_CLK] = { 28, 12, 9, 1 },
0344 [QCOM_RPM_NSS_FABRIC_0_CLK] = { 29, 13, 10, 1 },
0345 [QCOM_RPM_DAYTONA_FABRIC_CLK] = { 30, 14, 11, 1 },
0346 [QCOM_RPM_SFPB_CLK] = { 31, 15, 12, 1 },
0347 [QCOM_RPM_CFPB_CLK] = { 32, 16, 13, 1 },
0348 [QCOM_RPM_NSS_FABRIC_1_CLK] = { 33, 17, 14, 1 },
0349 [QCOM_RPM_EBI1_CLK] = { 34, 18, 16, 1 },
0350 [QCOM_RPM_APPS_FABRIC_HALT] = { 35, 19, 18, 2 },
0351 [QCOM_RPM_APPS_FABRIC_MODE] = { 37, 20, 19, 3 },
0352 [QCOM_RPM_APPS_FABRIC_IOCTL] = { 40, 21, 20, 1 },
0353 [QCOM_RPM_APPS_FABRIC_ARB] = { 41, 22, 21, 12 },
0354 [QCOM_RPM_SYS_FABRIC_HALT] = { 53, 23, 22, 2 },
0355 [QCOM_RPM_SYS_FABRIC_MODE] = { 55, 24, 23, 3 },
0356 [QCOM_RPM_SYS_FABRIC_IOCTL] = { 58, 25, 24, 1 },
0357 [QCOM_RPM_SYS_FABRIC_ARB] = { 59, 26, 25, 30 },
0358 [QCOM_RPM_MM_FABRIC_HALT] = { 89, 27, 26, 2 },
0359 [QCOM_RPM_MM_FABRIC_MODE] = { 91, 28, 27, 3 },
0360 [QCOM_RPM_MM_FABRIC_IOCTL] = { 94, 29, 28, 1 },
0361 [QCOM_RPM_MM_FABRIC_ARB] = { 95, 30, 29, 2 },
0362 [QCOM_RPM_CXO_BUFFERS] = { 209, 33, 31, 1 },
0363 [QCOM_RPM_USB_OTG_SWITCH] = { 210, 34, 32, 1 },
0364 [QCOM_RPM_HDMI_SWITCH] = { 211, 35, 33, 1 },
0365 [QCOM_RPM_DDR_DMM] = { 212, 36, 34, 2 },
0366 [QCOM_RPM_VDDMIN_GPIO] = { 215, 40, 39, 1 },
0367 [QCOM_RPM_SMB208_S1a] = { 216, 41, 90, 2 },
0368 [QCOM_RPM_SMB208_S1b] = { 218, 43, 91, 2 },
0369 [QCOM_RPM_SMB208_S2a] = { 220, 45, 92, 2 },
0370 [QCOM_RPM_SMB208_S2b] = { 222, 47, 93, 2 },
0371 };
0372
0373 static const struct qcom_rpm_data ipq806x_template = {
0374 .version = 3,
0375 .resource_table = ipq806x_rpm_resource_table,
0376 .n_resources = ARRAY_SIZE(ipq806x_rpm_resource_table),
0377 .req_ctx_off = 3,
0378 .req_sel_off = 11,
0379 .ack_ctx_off = 15,
0380 .ack_sel_off = 23,
0381 .req_sel_size = 4,
0382 .ack_sel_size = 7,
0383 };
0384
0385 static const struct qcom_rpm_resource mdm9615_rpm_resource_table[] = {
0386 [QCOM_RPM_CXO_CLK] = { 25, 9, 5, 1 },
0387 [QCOM_RPM_SYS_FABRIC_CLK] = { 26, 10, 9, 1 },
0388 [QCOM_RPM_DAYTONA_FABRIC_CLK] = { 27, 11, 11, 1 },
0389 [QCOM_RPM_SFPB_CLK] = { 28, 12, 12, 1 },
0390 [QCOM_RPM_CFPB_CLK] = { 29, 13, 13, 1 },
0391 [QCOM_RPM_EBI1_CLK] = { 30, 14, 16, 1 },
0392 [QCOM_RPM_APPS_FABRIC_HALT] = { 31, 15, 22, 2 },
0393 [QCOM_RPM_APPS_FABRIC_MODE] = { 33, 16, 23, 3 },
0394 [QCOM_RPM_APPS_FABRIC_IOCTL] = { 36, 17, 24, 1 },
0395 [QCOM_RPM_APPS_FABRIC_ARB] = { 37, 18, 25, 27 },
0396 [QCOM_RPM_PM8018_SMPS1] = { 64, 19, 30, 2 },
0397 [QCOM_RPM_PM8018_SMPS2] = { 66, 21, 31, 2 },
0398 [QCOM_RPM_PM8018_SMPS3] = { 68, 23, 32, 2 },
0399 [QCOM_RPM_PM8018_SMPS4] = { 70, 25, 33, 2 },
0400 [QCOM_RPM_PM8018_SMPS5] = { 72, 27, 34, 2 },
0401 [QCOM_RPM_PM8018_LDO1] = { 74, 29, 35, 2 },
0402 [QCOM_RPM_PM8018_LDO2] = { 76, 31, 36, 2 },
0403 [QCOM_RPM_PM8018_LDO3] = { 78, 33, 37, 2 },
0404 [QCOM_RPM_PM8018_LDO4] = { 80, 35, 38, 2 },
0405 [QCOM_RPM_PM8018_LDO5] = { 82, 37, 39, 2 },
0406 [QCOM_RPM_PM8018_LDO6] = { 84, 39, 40, 2 },
0407 [QCOM_RPM_PM8018_LDO7] = { 86, 41, 41, 2 },
0408 [QCOM_RPM_PM8018_LDO8] = { 88, 43, 42, 2 },
0409 [QCOM_RPM_PM8018_LDO9] = { 90, 45, 43, 2 },
0410 [QCOM_RPM_PM8018_LDO10] = { 92, 47, 44, 2 },
0411 [QCOM_RPM_PM8018_LDO11] = { 94, 49, 45, 2 },
0412 [QCOM_RPM_PM8018_LDO12] = { 96, 51, 46, 2 },
0413 [QCOM_RPM_PM8018_LDO13] = { 98, 53, 47, 2 },
0414 [QCOM_RPM_PM8018_LDO14] = { 100, 55, 48, 2 },
0415 [QCOM_RPM_PM8018_LVS1] = { 102, 57, 49, 1 },
0416 [QCOM_RPM_PM8018_NCP] = { 103, 58, 80, 2 },
0417 [QCOM_RPM_CXO_BUFFERS] = { 105, 60, 81, 1 },
0418 [QCOM_RPM_USB_OTG_SWITCH] = { 106, 61, 82, 1 },
0419 [QCOM_RPM_HDMI_SWITCH] = { 107, 62, 83, 1 },
0420 [QCOM_RPM_VOLTAGE_CORNER] = { 109, 64, 87, 1 },
0421 };
0422
0423 static const struct qcom_rpm_data mdm9615_template = {
0424 .version = 3,
0425 .resource_table = mdm9615_rpm_resource_table,
0426 .n_resources = ARRAY_SIZE(mdm9615_rpm_resource_table),
0427 .req_ctx_off = 3,
0428 .req_sel_off = 11,
0429 .ack_ctx_off = 15,
0430 .ack_sel_off = 23,
0431 .req_sel_size = 4,
0432 .ack_sel_size = 7,
0433 };
0434
0435 static const struct of_device_id qcom_rpm_of_match[] = {
0436 { .compatible = "qcom,rpm-apq8064", .data = &apq8064_template },
0437 { .compatible = "qcom,rpm-msm8660", .data = &msm8660_template },
0438 { .compatible = "qcom,rpm-msm8960", .data = &msm8960_template },
0439 { .compatible = "qcom,rpm-ipq8064", .data = &ipq806x_template },
0440 { .compatible = "qcom,rpm-mdm9615", .data = &mdm9615_template },
0441 { }
0442 };
0443 MODULE_DEVICE_TABLE(of, qcom_rpm_of_match);
0444
0445 int qcom_rpm_write(struct qcom_rpm *rpm,
0446 int state,
0447 int resource,
0448 u32 *buf, size_t count)
0449 {
0450 const struct qcom_rpm_resource *res;
0451 const struct qcom_rpm_data *data = rpm->data;
0452 u32 sel_mask[RPM_MAX_SEL_SIZE] = { 0 };
0453 int left;
0454 int ret = 0;
0455 int i;
0456
0457 if (WARN_ON(resource < 0 || resource >= data->n_resources))
0458 return -EINVAL;
0459
0460 res = &data->resource_table[resource];
0461 if (WARN_ON(res->size != count))
0462 return -EINVAL;
0463
0464 mutex_lock(&rpm->lock);
0465
0466 for (i = 0; i < res->size; i++)
0467 writel_relaxed(buf[i], RPM_REQ_REG(rpm, res->target_id + i));
0468
0469 bitmap_set((unsigned long *)sel_mask, res->select_id, 1);
0470 for (i = 0; i < rpm->data->req_sel_size; i++) {
0471 writel_relaxed(sel_mask[i],
0472 RPM_CTRL_REG(rpm, rpm->data->req_sel_off + i));
0473 }
0474
0475 writel_relaxed(BIT(state), RPM_CTRL_REG(rpm, rpm->data->req_ctx_off));
0476
0477 reinit_completion(&rpm->ack);
0478 regmap_write(rpm->ipc_regmap, rpm->ipc_offset, BIT(rpm->ipc_bit));
0479
0480 left = wait_for_completion_timeout(&rpm->ack, RPM_REQUEST_TIMEOUT);
0481 if (!left)
0482 ret = -ETIMEDOUT;
0483 else if (rpm->ack_status & RPM_REJECTED)
0484 ret = -EIO;
0485
0486 mutex_unlock(&rpm->lock);
0487
0488 return ret;
0489 }
0490 EXPORT_SYMBOL(qcom_rpm_write);
0491
0492 static irqreturn_t qcom_rpm_ack_interrupt(int irq, void *dev)
0493 {
0494 struct qcom_rpm *rpm = dev;
0495 u32 ack;
0496 int i;
0497
0498 ack = readl_relaxed(RPM_CTRL_REG(rpm, rpm->data->ack_ctx_off));
0499 for (i = 0; i < rpm->data->ack_sel_size; i++)
0500 writel_relaxed(0,
0501 RPM_CTRL_REG(rpm, rpm->data->ack_sel_off + i));
0502 writel(0, RPM_CTRL_REG(rpm, rpm->data->ack_ctx_off));
0503
0504 if (ack & RPM_NOTIFICATION) {
0505 dev_warn(rpm->dev, "ignoring notification!\n");
0506 } else {
0507 rpm->ack_status = ack;
0508 complete(&rpm->ack);
0509 }
0510
0511 return IRQ_HANDLED;
0512 }
0513
0514 static irqreturn_t qcom_rpm_err_interrupt(int irq, void *dev)
0515 {
0516 struct qcom_rpm *rpm = dev;
0517
0518 regmap_write(rpm->ipc_regmap, rpm->ipc_offset, BIT(rpm->ipc_bit));
0519 dev_err(rpm->dev, "RPM triggered fatal error\n");
0520
0521 return IRQ_HANDLED;
0522 }
0523
0524 static irqreturn_t qcom_rpm_wakeup_interrupt(int irq, void *dev)
0525 {
0526 return IRQ_HANDLED;
0527 }
0528
0529 static int qcom_rpm_probe(struct platform_device *pdev)
0530 {
0531 const struct of_device_id *match;
0532 struct device_node *syscon_np;
0533 struct resource *res;
0534 struct qcom_rpm *rpm;
0535 u32 fw_version[3];
0536 int irq_wakeup;
0537 int irq_ack;
0538 int irq_err;
0539 int ret;
0540
0541 rpm = devm_kzalloc(&pdev->dev, sizeof(*rpm), GFP_KERNEL);
0542 if (!rpm)
0543 return -ENOMEM;
0544
0545 rpm->dev = &pdev->dev;
0546 mutex_init(&rpm->lock);
0547 init_completion(&rpm->ack);
0548
0549
0550 rpm->ramclk = devm_clk_get(&pdev->dev, "ram");
0551 if (IS_ERR(rpm->ramclk)) {
0552 ret = PTR_ERR(rpm->ramclk);
0553 if (ret == -EPROBE_DEFER)
0554 return ret;
0555
0556
0557
0558
0559 rpm->ramclk = NULL;
0560 }
0561 clk_prepare_enable(rpm->ramclk);
0562
0563 irq_ack = platform_get_irq_byname(pdev, "ack");
0564 if (irq_ack < 0)
0565 return irq_ack;
0566
0567 irq_err = platform_get_irq_byname(pdev, "err");
0568 if (irq_err < 0)
0569 return irq_err;
0570
0571 irq_wakeup = platform_get_irq_byname(pdev, "wakeup");
0572 if (irq_wakeup < 0)
0573 return irq_wakeup;
0574
0575 match = of_match_device(qcom_rpm_of_match, &pdev->dev);
0576 if (!match)
0577 return -ENODEV;
0578 rpm->data = match->data;
0579
0580 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0581 rpm->status_regs = devm_ioremap_resource(&pdev->dev, res);
0582 if (IS_ERR(rpm->status_regs))
0583 return PTR_ERR(rpm->status_regs);
0584 rpm->ctrl_regs = rpm->status_regs + 0x400;
0585 rpm->req_regs = rpm->status_regs + 0x600;
0586
0587 syscon_np = of_parse_phandle(pdev->dev.of_node, "qcom,ipc", 0);
0588 if (!syscon_np) {
0589 dev_err(&pdev->dev, "no qcom,ipc node\n");
0590 return -ENODEV;
0591 }
0592
0593 rpm->ipc_regmap = syscon_node_to_regmap(syscon_np);
0594 of_node_put(syscon_np);
0595 if (IS_ERR(rpm->ipc_regmap))
0596 return PTR_ERR(rpm->ipc_regmap);
0597
0598 ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,ipc", 1,
0599 &rpm->ipc_offset);
0600 if (ret < 0) {
0601 dev_err(&pdev->dev, "no offset in qcom,ipc\n");
0602 return -EINVAL;
0603 }
0604
0605 ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,ipc", 2,
0606 &rpm->ipc_bit);
0607 if (ret < 0) {
0608 dev_err(&pdev->dev, "no bit in qcom,ipc\n");
0609 return -EINVAL;
0610 }
0611
0612 dev_set_drvdata(&pdev->dev, rpm);
0613
0614 fw_version[0] = readl(RPM_STATUS_REG(rpm, 0));
0615 fw_version[1] = readl(RPM_STATUS_REG(rpm, 1));
0616 fw_version[2] = readl(RPM_STATUS_REG(rpm, 2));
0617 if (fw_version[0] != rpm->data->version) {
0618 dev_err(&pdev->dev,
0619 "RPM version %u.%u.%u incompatible with driver version %u",
0620 fw_version[0],
0621 fw_version[1],
0622 fw_version[2],
0623 rpm->data->version);
0624 return -EFAULT;
0625 }
0626
0627 writel(fw_version[0], RPM_CTRL_REG(rpm, 0));
0628 writel(fw_version[1], RPM_CTRL_REG(rpm, 1));
0629 writel(fw_version[2], RPM_CTRL_REG(rpm, 2));
0630
0631 dev_info(&pdev->dev, "RPM firmware %u.%u.%u\n", fw_version[0],
0632 fw_version[1],
0633 fw_version[2]);
0634
0635 ret = devm_request_irq(&pdev->dev,
0636 irq_ack,
0637 qcom_rpm_ack_interrupt,
0638 IRQF_TRIGGER_RISING,
0639 "qcom_rpm_ack",
0640 rpm);
0641 if (ret) {
0642 dev_err(&pdev->dev, "failed to request ack interrupt\n");
0643 return ret;
0644 }
0645
0646 ret = irq_set_irq_wake(irq_ack, 1);
0647 if (ret)
0648 dev_warn(&pdev->dev, "failed to mark ack irq as wakeup\n");
0649
0650 ret = devm_request_irq(&pdev->dev,
0651 irq_err,
0652 qcom_rpm_err_interrupt,
0653 IRQF_TRIGGER_RISING,
0654 "qcom_rpm_err",
0655 rpm);
0656 if (ret) {
0657 dev_err(&pdev->dev, "failed to request err interrupt\n");
0658 return ret;
0659 }
0660
0661 ret = devm_request_irq(&pdev->dev,
0662 irq_wakeup,
0663 qcom_rpm_wakeup_interrupt,
0664 IRQF_TRIGGER_RISING,
0665 "qcom_rpm_wakeup",
0666 rpm);
0667 if (ret) {
0668 dev_err(&pdev->dev, "failed to request wakeup interrupt\n");
0669 return ret;
0670 }
0671
0672 ret = irq_set_irq_wake(irq_wakeup, 1);
0673 if (ret)
0674 dev_warn(&pdev->dev, "failed to mark wakeup irq as wakeup\n");
0675
0676 return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
0677 }
0678
0679 static int qcom_rpm_remove(struct platform_device *pdev)
0680 {
0681 struct qcom_rpm *rpm = dev_get_drvdata(&pdev->dev);
0682
0683 of_platform_depopulate(&pdev->dev);
0684 clk_disable_unprepare(rpm->ramclk);
0685
0686 return 0;
0687 }
0688
0689 static struct platform_driver qcom_rpm_driver = {
0690 .probe = qcom_rpm_probe,
0691 .remove = qcom_rpm_remove,
0692 .driver = {
0693 .name = "qcom_rpm",
0694 .of_match_table = qcom_rpm_of_match,
0695 },
0696 };
0697
0698 static int __init qcom_rpm_init(void)
0699 {
0700 return platform_driver_register(&qcom_rpm_driver);
0701 }
0702 arch_initcall(qcom_rpm_init);
0703
0704 static void __exit qcom_rpm_exit(void)
0705 {
0706 platform_driver_unregister(&qcom_rpm_driver);
0707 }
0708 module_exit(qcom_rpm_exit)
0709
0710 MODULE_DESCRIPTION("Qualcomm Resource Power Manager driver");
0711 MODULE_LICENSE("GPL v2");
0712 MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
