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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
0004  */
0005 
0006 #define pr_fmt(fmt) "%s: " fmt, __func__
0007 
0008 #include <linux/kernel.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/irqchip/chained_irq.h>
0011 #include <linux/irq.h>
0012 #include <linux/irqdomain.h>
0013 #include <linux/module.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/slab.h>
0016 #include <linux/err.h>
0017 #include <linux/ssbi.h>
0018 #include <linux/regmap.h>
0019 #include <linux/of_platform.h>
0020 #include <linux/mfd/core.h>
0021 
0022 #define SSBI_REG_ADDR_IRQ_BASE      0x1BB
0023 
0024 #define SSBI_REG_ADDR_IRQ_ROOT      (SSBI_REG_ADDR_IRQ_BASE + 0)
0025 #define SSBI_REG_ADDR_IRQ_M_STATUS1 (SSBI_REG_ADDR_IRQ_BASE + 1)
0026 #define SSBI_REG_ADDR_IRQ_M_STATUS2 (SSBI_REG_ADDR_IRQ_BASE + 2)
0027 #define SSBI_REG_ADDR_IRQ_M_STATUS3 (SSBI_REG_ADDR_IRQ_BASE + 3)
0028 #define SSBI_REG_ADDR_IRQ_M_STATUS4 (SSBI_REG_ADDR_IRQ_BASE + 4)
0029 #define SSBI_REG_ADDR_IRQ_BLK_SEL   (SSBI_REG_ADDR_IRQ_BASE + 5)
0030 #define SSBI_REG_ADDR_IRQ_IT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 6)
0031 #define SSBI_REG_ADDR_IRQ_CONFIG    (SSBI_REG_ADDR_IRQ_BASE + 7)
0032 #define SSBI_REG_ADDR_IRQ_RT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 8)
0033 
0034 #define PM8821_SSBI_REG_ADDR_IRQ_BASE   0x100
0035 #define PM8821_SSBI_REG_ADDR_IRQ_MASTER0 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0x30)
0036 #define PM8821_SSBI_REG_ADDR_IRQ_MASTER1 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0xb0)
0037 #define PM8821_SSBI_REG(m, b, offset) \
0038             ((m == 0) ? \
0039             (PM8821_SSBI_REG_ADDR_IRQ_MASTER0 + b + offset) : \
0040             (PM8821_SSBI_REG_ADDR_IRQ_MASTER1 + b + offset))
0041 #define PM8821_SSBI_ADDR_IRQ_ROOT(m, b)     PM8821_SSBI_REG(m, b, 0x0)
0042 #define PM8821_SSBI_ADDR_IRQ_CLEAR(m, b)    PM8821_SSBI_REG(m, b, 0x01)
0043 #define PM8821_SSBI_ADDR_IRQ_MASK(m, b)     PM8821_SSBI_REG(m, b, 0x08)
0044 #define PM8821_SSBI_ADDR_IRQ_RT_STATUS(m, b)    PM8821_SSBI_REG(m, b, 0x0f)
0045 
0046 #define PM8821_BLOCKS_PER_MASTER    7
0047 
0048 #define PM_IRQF_LVL_SEL         0x01    /* level select */
0049 #define PM_IRQF_MASK_FE         0x02    /* mask falling edge */
0050 #define PM_IRQF_MASK_RE         0x04    /* mask rising edge */
0051 #define PM_IRQF_CLR         0x08    /* clear interrupt */
0052 #define PM_IRQF_BITS_MASK       0x70
0053 #define PM_IRQF_BITS_SHIFT      4
0054 #define PM_IRQF_WRITE           0x80
0055 
0056 #define PM_IRQF_MASK_ALL        (PM_IRQF_MASK_FE | \
0057                     PM_IRQF_MASK_RE)
0058 
0059 #define REG_HWREV       0x002  /* PMIC4 revision */
0060 #define REG_HWREV_2     0x0E8  /* PMIC4 revision 2 */
0061 
0062 #define PM8XXX_NR_IRQS      256
0063 #define PM8821_NR_IRQS      112
0064 
0065 struct pm_irq_data {
0066     int num_irqs;
0067     struct irq_chip *irq_chip;
0068     irq_handler_t irq_handler;
0069 };
0070 
0071 struct pm_irq_chip {
0072     struct regmap       *regmap;
0073     spinlock_t      pm_irq_lock;
0074     struct irq_domain   *irqdomain;
0075     unsigned int        num_blocks;
0076     unsigned int        num_masters;
0077     const struct pm_irq_data *pm_irq_data;
0078     /* MUST BE AT THE END OF THIS STRUCT */
0079     u8          config[];
0080 };
0081 
0082 static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, unsigned int bp,
0083                  unsigned int *ip)
0084 {
0085     int rc;
0086 
0087     spin_lock(&chip->pm_irq_lock);
0088     rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
0089     if (rc) {
0090         pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
0091         goto bail;
0092     }
0093 
0094     rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
0095     if (rc)
0096         pr_err("Failed Reading Status rc=%d\n", rc);
0097 bail:
0098     spin_unlock(&chip->pm_irq_lock);
0099     return rc;
0100 }
0101 
0102 static int
0103 pm8xxx_config_irq(struct pm_irq_chip *chip, unsigned int bp, unsigned int cp)
0104 {
0105     int rc;
0106 
0107     spin_lock(&chip->pm_irq_lock);
0108     rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
0109     if (rc) {
0110         pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
0111         goto bail;
0112     }
0113 
0114     cp |= PM_IRQF_WRITE;
0115     rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_CONFIG, cp);
0116     if (rc)
0117         pr_err("Failed Configuring IRQ rc=%d\n", rc);
0118 bail:
0119     spin_unlock(&chip->pm_irq_lock);
0120     return rc;
0121 }
0122 
0123 static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block)
0124 {
0125     int pmirq, i, ret = 0;
0126     unsigned int bits;
0127 
0128     ret = pm8xxx_read_block_irq(chip, block, &bits);
0129     if (ret) {
0130         pr_err("Failed reading %d block ret=%d", block, ret);
0131         return ret;
0132     }
0133     if (!bits) {
0134         pr_err("block bit set in master but no irqs: %d", block);
0135         return 0;
0136     }
0137 
0138     /* Check IRQ bits */
0139     for (i = 0; i < 8; i++) {
0140         if (bits & (1 << i)) {
0141             pmirq = block * 8 + i;
0142             generic_handle_domain_irq(chip->irqdomain, pmirq);
0143         }
0144     }
0145     return 0;
0146 }
0147 
0148 static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip, int master)
0149 {
0150     unsigned int blockbits;
0151     int block_number, i, ret = 0;
0152 
0153     ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_M_STATUS1 + master,
0154               &blockbits);
0155     if (ret) {
0156         pr_err("Failed to read master %d ret=%d\n", master, ret);
0157         return ret;
0158     }
0159     if (!blockbits) {
0160         pr_err("master bit set in root but no blocks: %d", master);
0161         return 0;
0162     }
0163 
0164     for (i = 0; i < 8; i++)
0165         if (blockbits & (1 << i)) {
0166             block_number = master * 8 + i;  /* block # */
0167             ret |= pm8xxx_irq_block_handler(chip, block_number);
0168         }
0169     return ret;
0170 }
0171 
0172 static irqreturn_t pm8xxx_irq_handler(int irq, void *data)
0173 {
0174     struct pm_irq_chip *chip = data;
0175     unsigned int root;
0176     int i, ret, masters = 0;
0177 
0178     ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_ROOT, &root);
0179     if (ret) {
0180         pr_err("Can't read root status ret=%d\n", ret);
0181         return IRQ_NONE;
0182     }
0183 
0184     /* on pm8xxx series masters start from bit 1 of the root */
0185     masters = root >> 1;
0186 
0187     /* Read allowed masters for blocks. */
0188     for (i = 0; i < chip->num_masters; i++)
0189         if (masters & (1 << i))
0190             pm8xxx_irq_master_handler(chip, i);
0191 
0192     return IRQ_HANDLED;
0193 }
0194 
0195 static void pm8821_irq_block_handler(struct pm_irq_chip *chip,
0196                      int master, int block)
0197 {
0198     int pmirq, i, ret;
0199     unsigned int bits;
0200 
0201     ret = regmap_read(chip->regmap,
0202               PM8821_SSBI_ADDR_IRQ_ROOT(master, block), &bits);
0203     if (ret) {
0204         pr_err("Reading block %d failed ret=%d", block, ret);
0205         return;
0206     }
0207 
0208     /* Convert block offset to global block number */
0209     block += (master * PM8821_BLOCKS_PER_MASTER) - 1;
0210 
0211     /* Check IRQ bits */
0212     for (i = 0; i < 8; i++) {
0213         if (bits & BIT(i)) {
0214             pmirq = block * 8 + i;
0215             generic_handle_domain_irq(chip->irqdomain, pmirq);
0216         }
0217     }
0218 }
0219 
0220 static inline void pm8821_irq_master_handler(struct pm_irq_chip *chip,
0221                          int master, u8 master_val)
0222 {
0223     int block;
0224 
0225     for (block = 1; block < 8; block++)
0226         if (master_val & BIT(block))
0227             pm8821_irq_block_handler(chip, master, block);
0228 }
0229 
0230 static irqreturn_t pm8821_irq_handler(int irq, void *data)
0231 {
0232     struct pm_irq_chip *chip = data;
0233     unsigned int master;
0234     int ret;
0235 
0236     ret = regmap_read(chip->regmap,
0237               PM8821_SSBI_REG_ADDR_IRQ_MASTER0, &master);
0238     if (ret) {
0239         pr_err("Failed to read master 0 ret=%d\n", ret);
0240         return IRQ_NONE;
0241     }
0242 
0243     /* bits 1 through 7 marks the first 7 blocks in master 0 */
0244     if (master & GENMASK(7, 1))
0245         pm8821_irq_master_handler(chip, 0, master);
0246 
0247     /* bit 0 marks if master 1 contains any bits */
0248     if (!(master & BIT(0)))
0249         return IRQ_NONE;
0250 
0251     ret = regmap_read(chip->regmap,
0252               PM8821_SSBI_REG_ADDR_IRQ_MASTER1, &master);
0253     if (ret) {
0254         pr_err("Failed to read master 1 ret=%d\n", ret);
0255         return IRQ_NONE;
0256     }
0257 
0258     pm8821_irq_master_handler(chip, 1, master);
0259 
0260     return IRQ_HANDLED;
0261 }
0262 
0263 static void pm8xxx_irq_mask_ack(struct irq_data *d)
0264 {
0265     struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
0266     unsigned int pmirq = irqd_to_hwirq(d);
0267     u8  block, config;
0268 
0269     block = pmirq / 8;
0270 
0271     config = chip->config[pmirq] | PM_IRQF_MASK_ALL | PM_IRQF_CLR;
0272     pm8xxx_config_irq(chip, block, config);
0273 }
0274 
0275 static void pm8xxx_irq_unmask(struct irq_data *d)
0276 {
0277     struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
0278     unsigned int pmirq = irqd_to_hwirq(d);
0279     u8  block, config;
0280 
0281     block = pmirq / 8;
0282 
0283     config = chip->config[pmirq];
0284     pm8xxx_config_irq(chip, block, config);
0285 }
0286 
0287 static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
0288 {
0289     struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
0290     unsigned int pmirq = irqd_to_hwirq(d);
0291     int irq_bit;
0292     u8 block, config;
0293 
0294     block = pmirq / 8;
0295     irq_bit  = pmirq % 8;
0296 
0297     chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT)
0298                             | PM_IRQF_MASK_ALL;
0299     if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
0300         if (flow_type & IRQF_TRIGGER_RISING)
0301             chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
0302         if (flow_type & IRQF_TRIGGER_FALLING)
0303             chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
0304     } else {
0305         chip->config[pmirq] |= PM_IRQF_LVL_SEL;
0306 
0307         if (flow_type & IRQF_TRIGGER_HIGH)
0308             chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
0309         else
0310             chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
0311     }
0312 
0313     config = chip->config[pmirq] | PM_IRQF_CLR;
0314     return pm8xxx_config_irq(chip, block, config);
0315 }
0316 
0317 static int pm8xxx_irq_get_irqchip_state(struct irq_data *d,
0318                     enum irqchip_irq_state which,
0319                     bool *state)
0320 {
0321     struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
0322     unsigned int pmirq = irqd_to_hwirq(d);
0323     unsigned int bits;
0324     int irq_bit;
0325     u8 block;
0326     int rc;
0327 
0328     if (which != IRQCHIP_STATE_LINE_LEVEL)
0329         return -EINVAL;
0330 
0331     block = pmirq / 8;
0332     irq_bit = pmirq % 8;
0333 
0334     spin_lock(&chip->pm_irq_lock);
0335     rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, block);
0336     if (rc) {
0337         pr_err("Failed Selecting Block %d rc=%d\n", block, rc);
0338         goto bail;
0339     }
0340 
0341     rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_RT_STATUS, &bits);
0342     if (rc) {
0343         pr_err("Failed Reading Status rc=%d\n", rc);
0344         goto bail;
0345     }
0346 
0347     *state = !!(bits & BIT(irq_bit));
0348 bail:
0349     spin_unlock(&chip->pm_irq_lock);
0350 
0351     return rc;
0352 }
0353 
0354 static struct irq_chip pm8xxx_irq_chip = {
0355     .name       = "pm8xxx",
0356     .irq_mask_ack   = pm8xxx_irq_mask_ack,
0357     .irq_unmask = pm8xxx_irq_unmask,
0358     .irq_set_type   = pm8xxx_irq_set_type,
0359     .irq_get_irqchip_state = pm8xxx_irq_get_irqchip_state,
0360     .flags      = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
0361 };
0362 
0363 static void pm8xxx_irq_domain_map(struct pm_irq_chip *chip,
0364                   struct irq_domain *domain, unsigned int irq,
0365                   irq_hw_number_t hwirq, unsigned int type)
0366 {
0367     irq_domain_set_info(domain, irq, hwirq, chip->pm_irq_data->irq_chip,
0368                 chip, handle_level_irq, NULL, NULL);
0369     irq_set_noprobe(irq);
0370 }
0371 
0372 static int pm8xxx_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
0373                    unsigned int nr_irqs, void *data)
0374 {
0375     struct pm_irq_chip *chip = domain->host_data;
0376     struct irq_fwspec *fwspec = data;
0377     irq_hw_number_t hwirq;
0378     unsigned int type;
0379     int ret, i;
0380 
0381     ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
0382     if (ret)
0383         return ret;
0384 
0385     for (i = 0; i < nr_irqs; i++)
0386         pm8xxx_irq_domain_map(chip, domain, virq + i, hwirq + i, type);
0387 
0388     return 0;
0389 }
0390 
0391 static const struct irq_domain_ops pm8xxx_irq_domain_ops = {
0392     .alloc = pm8xxx_irq_domain_alloc,
0393     .free = irq_domain_free_irqs_common,
0394     .translate = irq_domain_translate_twocell,
0395 };
0396 
0397 static void pm8821_irq_mask_ack(struct irq_data *d)
0398 {
0399     struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
0400     unsigned int pmirq = irqd_to_hwirq(d);
0401     u8 block, master;
0402     int irq_bit, rc;
0403 
0404     block = pmirq / 8;
0405     master = block / PM8821_BLOCKS_PER_MASTER;
0406     irq_bit = pmirq % 8;
0407     block %= PM8821_BLOCKS_PER_MASTER;
0408 
0409     rc = regmap_update_bits(chip->regmap,
0410                 PM8821_SSBI_ADDR_IRQ_MASK(master, block),
0411                 BIT(irq_bit), BIT(irq_bit));
0412     if (rc) {
0413         pr_err("Failed to mask IRQ:%d rc=%d\n", pmirq, rc);
0414         return;
0415     }
0416 
0417     rc = regmap_update_bits(chip->regmap,
0418                 PM8821_SSBI_ADDR_IRQ_CLEAR(master, block),
0419                 BIT(irq_bit), BIT(irq_bit));
0420     if (rc)
0421         pr_err("Failed to CLEAR IRQ:%d rc=%d\n", pmirq, rc);
0422 }
0423 
0424 static void pm8821_irq_unmask(struct irq_data *d)
0425 {
0426     struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
0427     unsigned int pmirq = irqd_to_hwirq(d);
0428     int irq_bit, rc;
0429     u8 block, master;
0430 
0431     block = pmirq / 8;
0432     master = block / PM8821_BLOCKS_PER_MASTER;
0433     irq_bit = pmirq % 8;
0434     block %= PM8821_BLOCKS_PER_MASTER;
0435 
0436     rc = regmap_update_bits(chip->regmap,
0437                 PM8821_SSBI_ADDR_IRQ_MASK(master, block),
0438                 BIT(irq_bit), ~BIT(irq_bit));
0439     if (rc)
0440         pr_err("Failed to read/write unmask IRQ:%d rc=%d\n", pmirq, rc);
0441 
0442 }
0443 
0444 static int pm8821_irq_get_irqchip_state(struct irq_data *d,
0445                     enum irqchip_irq_state which,
0446                     bool *state)
0447 {
0448     struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
0449     int rc, pmirq = irqd_to_hwirq(d);
0450     u8 block, irq_bit, master;
0451     unsigned int bits;
0452 
0453     block = pmirq / 8;
0454     master = block / PM8821_BLOCKS_PER_MASTER;
0455     irq_bit = pmirq % 8;
0456     block %= PM8821_BLOCKS_PER_MASTER;
0457 
0458     rc = regmap_read(chip->regmap,
0459         PM8821_SSBI_ADDR_IRQ_RT_STATUS(master, block), &bits);
0460     if (rc) {
0461         pr_err("Reading Status of IRQ %d failed rc=%d\n", pmirq, rc);
0462         return rc;
0463     }
0464 
0465     *state = !!(bits & BIT(irq_bit));
0466 
0467     return rc;
0468 }
0469 
0470 static struct irq_chip pm8821_irq_chip = {
0471     .name       = "pm8821",
0472     .irq_mask_ack   = pm8821_irq_mask_ack,
0473     .irq_unmask = pm8821_irq_unmask,
0474     .irq_get_irqchip_state = pm8821_irq_get_irqchip_state,
0475     .flags      = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
0476 };
0477 
0478 static const struct regmap_config ssbi_regmap_config = {
0479     .reg_bits = 16,
0480     .val_bits = 8,
0481     .max_register = 0x3ff,
0482     .fast_io = true,
0483     .reg_read = ssbi_reg_read,
0484     .reg_write = ssbi_reg_write
0485 };
0486 
0487 static const struct pm_irq_data pm8xxx_data = {
0488     .num_irqs = PM8XXX_NR_IRQS,
0489     .irq_chip = &pm8xxx_irq_chip,
0490     .irq_handler = pm8xxx_irq_handler,
0491 };
0492 
0493 static const struct pm_irq_data pm8821_data = {
0494     .num_irqs = PM8821_NR_IRQS,
0495     .irq_chip = &pm8821_irq_chip,
0496     .irq_handler = pm8821_irq_handler,
0497 };
0498 
0499 static const struct of_device_id pm8xxx_id_table[] = {
0500     { .compatible = "qcom,pm8018", .data = &pm8xxx_data},
0501     { .compatible = "qcom,pm8058", .data = &pm8xxx_data},
0502     { .compatible = "qcom,pm8821", .data = &pm8821_data},
0503     { .compatible = "qcom,pm8921", .data = &pm8xxx_data},
0504     { }
0505 };
0506 MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
0507 
0508 static int pm8xxx_probe(struct platform_device *pdev)
0509 {
0510     const struct pm_irq_data *data;
0511     struct regmap *regmap;
0512     int irq, rc;
0513     unsigned int val;
0514     u32 rev;
0515     struct pm_irq_chip *chip;
0516 
0517     data = of_device_get_match_data(&pdev->dev);
0518     if (!data) {
0519         dev_err(&pdev->dev, "No matching driver data found\n");
0520         return -EINVAL;
0521     }
0522 
0523     irq = platform_get_irq(pdev, 0);
0524     if (irq < 0)
0525         return irq;
0526 
0527     regmap = devm_regmap_init(&pdev->dev, NULL, pdev->dev.parent,
0528                   &ssbi_regmap_config);
0529     if (IS_ERR(regmap))
0530         return PTR_ERR(regmap);
0531 
0532     /* Read PMIC chip revision */
0533     rc = regmap_read(regmap, REG_HWREV, &val);
0534     if (rc) {
0535         pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc);
0536         return rc;
0537     }
0538     pr_info("PMIC revision 1: %02X\n", val);
0539     rev = val;
0540 
0541     /* Read PMIC chip revision 2 */
0542     rc = regmap_read(regmap, REG_HWREV_2, &val);
0543     if (rc) {
0544         pr_err("Failed to read hw rev 2 reg %d:rc=%d\n",
0545             REG_HWREV_2, rc);
0546         return rc;
0547     }
0548     pr_info("PMIC revision 2: %02X\n", val);
0549     rev |= val << BITS_PER_BYTE;
0550 
0551     chip = devm_kzalloc(&pdev->dev,
0552                 struct_size(chip, config, data->num_irqs),
0553                 GFP_KERNEL);
0554     if (!chip)
0555         return -ENOMEM;
0556 
0557     platform_set_drvdata(pdev, chip);
0558     chip->regmap = regmap;
0559     chip->num_blocks = DIV_ROUND_UP(data->num_irqs, 8);
0560     chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
0561     chip->pm_irq_data = data;
0562     spin_lock_init(&chip->pm_irq_lock);
0563 
0564     chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node,
0565                         data->num_irqs,
0566                         &pm8xxx_irq_domain_ops,
0567                         chip);
0568     if (!chip->irqdomain)
0569         return -ENODEV;
0570 
0571     rc = devm_request_irq(&pdev->dev, irq, data->irq_handler, 0, dev_name(&pdev->dev), chip);
0572     if (rc)
0573         return rc;
0574 
0575     irq_set_irq_wake(irq, 1);
0576 
0577     rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
0578     if (rc)
0579         irq_domain_remove(chip->irqdomain);
0580 
0581     return rc;
0582 }
0583 
0584 static int pm8xxx_remove_child(struct device *dev, void *unused)
0585 {
0586     platform_device_unregister(to_platform_device(dev));
0587     return 0;
0588 }
0589 
0590 static int pm8xxx_remove(struct platform_device *pdev)
0591 {
0592     struct pm_irq_chip *chip = platform_get_drvdata(pdev);
0593 
0594     device_for_each_child(&pdev->dev, NULL, pm8xxx_remove_child);
0595     irq_domain_remove(chip->irqdomain);
0596 
0597     return 0;
0598 }
0599 
0600 static struct platform_driver pm8xxx_driver = {
0601     .probe      = pm8xxx_probe,
0602     .remove     = pm8xxx_remove,
0603     .driver     = {
0604         .name   = "pm8xxx-core",
0605         .of_match_table = pm8xxx_id_table,
0606     },
0607 };
0608 
0609 static int __init pm8xxx_init(void)
0610 {
0611     return platform_driver_register(&pm8xxx_driver);
0612 }
0613 subsys_initcall(pm8xxx_init);
0614 
0615 static void __exit pm8xxx_exit(void)
0616 {
0617     platform_driver_unregister(&pm8xxx_driver);
0618 }
0619 module_exit(pm8xxx_exit);
0620 
0621 MODULE_LICENSE("GPL v2");
0622 MODULE_DESCRIPTION("PMIC 8xxx core driver");
0623 MODULE_VERSION("1.0");
0624 MODULE_ALIAS("platform:pm8xxx-core");
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