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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * TI Palmas MFD Driver
0004  *
0005  * Copyright 2011-2012 Texas Instruments Inc.
0006  *
0007  * Author: Graeme Gregory <gg@slimlogic.co.uk>
0008  */
0009 
0010 #include <linux/module.h>
0011 #include <linux/moduleparam.h>
0012 #include <linux/init.h>
0013 #include <linux/slab.h>
0014 #include <linux/i2c.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/irq.h>
0017 #include <linux/regmap.h>
0018 #include <linux/err.h>
0019 #include <linux/mfd/core.h>
0020 #include <linux/mfd/palmas.h>
0021 #include <linux/of_device.h>
0022 
0023 static const struct regmap_config palmas_regmap_config[PALMAS_NUM_CLIENTS] = {
0024     {
0025         .reg_bits = 8,
0026         .val_bits = 8,
0027         .max_register = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
0028                     PALMAS_PRIMARY_SECONDARY_PAD3),
0029     },
0030     {
0031         .reg_bits = 8,
0032         .val_bits = 8,
0033         .max_register = PALMAS_BASE_TO_REG(PALMAS_GPADC_BASE,
0034                     PALMAS_GPADC_SMPS_VSEL_MONITORING),
0035     },
0036     {
0037         .reg_bits = 8,
0038         .val_bits = 8,
0039         .max_register = PALMAS_BASE_TO_REG(PALMAS_TRIM_GPADC_BASE,
0040                     PALMAS_GPADC_TRIM16),
0041     },
0042 };
0043 
0044 static const struct regmap_irq tps65917_irqs[] = {
0045     /* INT1 IRQs */
0046     [TPS65917_RESERVED1] = {
0047         .mask = TPS65917_RESERVED,
0048     },
0049     [TPS65917_PWRON_IRQ] = {
0050         .mask = TPS65917_INT1_STATUS_PWRON,
0051     },
0052     [TPS65917_LONG_PRESS_KEY_IRQ] = {
0053         .mask = TPS65917_INT1_STATUS_LONG_PRESS_KEY,
0054     },
0055     [TPS65917_RESERVED2] = {
0056         .mask = TPS65917_RESERVED,
0057     },
0058     [TPS65917_PWRDOWN_IRQ] = {
0059         .mask = TPS65917_INT1_STATUS_PWRDOWN,
0060     },
0061     [TPS65917_HOTDIE_IRQ] = {
0062         .mask = TPS65917_INT1_STATUS_HOTDIE,
0063     },
0064     [TPS65917_VSYS_MON_IRQ] = {
0065         .mask = TPS65917_INT1_STATUS_VSYS_MON,
0066     },
0067     [TPS65917_RESERVED3] = {
0068         .mask = TPS65917_RESERVED,
0069     },
0070     /* INT2 IRQs*/
0071     [TPS65917_RESERVED4] = {
0072         .mask = TPS65917_RESERVED,
0073         .reg_offset = 1,
0074     },
0075     [TPS65917_OTP_ERROR_IRQ] = {
0076         .mask = TPS65917_INT2_STATUS_OTP_ERROR,
0077         .reg_offset = 1,
0078     },
0079     [TPS65917_WDT_IRQ] = {
0080         .mask = TPS65917_INT2_STATUS_WDT,
0081         .reg_offset = 1,
0082     },
0083     [TPS65917_RESERVED5] = {
0084         .mask = TPS65917_RESERVED,
0085         .reg_offset = 1,
0086     },
0087     [TPS65917_RESET_IN_IRQ] = {
0088         .mask = TPS65917_INT2_STATUS_RESET_IN,
0089         .reg_offset = 1,
0090     },
0091     [TPS65917_FSD_IRQ] = {
0092         .mask = TPS65917_INT2_STATUS_FSD,
0093         .reg_offset = 1,
0094     },
0095     [TPS65917_SHORT_IRQ] = {
0096         .mask = TPS65917_INT2_STATUS_SHORT,
0097         .reg_offset = 1,
0098     },
0099     [TPS65917_RESERVED6] = {
0100         .mask = TPS65917_RESERVED,
0101         .reg_offset = 1,
0102     },
0103     /* INT3 IRQs */
0104     [TPS65917_GPADC_AUTO_0_IRQ] = {
0105         .mask = TPS65917_INT3_STATUS_GPADC_AUTO_0,
0106         .reg_offset = 2,
0107     },
0108     [TPS65917_GPADC_AUTO_1_IRQ] = {
0109         .mask = TPS65917_INT3_STATUS_GPADC_AUTO_1,
0110         .reg_offset = 2,
0111     },
0112     [TPS65917_GPADC_EOC_SW_IRQ] = {
0113         .mask = TPS65917_INT3_STATUS_GPADC_EOC_SW,
0114         .reg_offset = 2,
0115     },
0116     [TPS65917_RESREVED6] = {
0117         .mask = TPS65917_RESERVED6,
0118         .reg_offset = 2,
0119     },
0120     [TPS65917_RESERVED7] = {
0121         .mask = TPS65917_RESERVED,
0122         .reg_offset = 2,
0123     },
0124     [TPS65917_RESERVED8] = {
0125         .mask = TPS65917_RESERVED,
0126         .reg_offset = 2,
0127     },
0128     [TPS65917_RESERVED9] = {
0129         .mask = TPS65917_RESERVED,
0130         .reg_offset = 2,
0131     },
0132     [TPS65917_VBUS_IRQ] = {
0133         .mask = TPS65917_INT3_STATUS_VBUS,
0134         .reg_offset = 2,
0135     },
0136     /* INT4 IRQs */
0137     [TPS65917_GPIO_0_IRQ] = {
0138         .mask = TPS65917_INT4_STATUS_GPIO_0,
0139         .reg_offset = 3,
0140     },
0141     [TPS65917_GPIO_1_IRQ] = {
0142         .mask = TPS65917_INT4_STATUS_GPIO_1,
0143         .reg_offset = 3,
0144     },
0145     [TPS65917_GPIO_2_IRQ] = {
0146         .mask = TPS65917_INT4_STATUS_GPIO_2,
0147         .reg_offset = 3,
0148     },
0149     [TPS65917_GPIO_3_IRQ] = {
0150         .mask = TPS65917_INT4_STATUS_GPIO_3,
0151         .reg_offset = 3,
0152     },
0153     [TPS65917_GPIO_4_IRQ] = {
0154         .mask = TPS65917_INT4_STATUS_GPIO_4,
0155         .reg_offset = 3,
0156     },
0157     [TPS65917_GPIO_5_IRQ] = {
0158         .mask = TPS65917_INT4_STATUS_GPIO_5,
0159         .reg_offset = 3,
0160     },
0161     [TPS65917_GPIO_6_IRQ] = {
0162         .mask = TPS65917_INT4_STATUS_GPIO_6,
0163         .reg_offset = 3,
0164     },
0165     [TPS65917_RESERVED10] = {
0166         .mask = TPS65917_RESERVED10,
0167         .reg_offset = 3,
0168     },
0169 };
0170 
0171 static const struct regmap_irq palmas_irqs[] = {
0172     /* INT1 IRQs */
0173     [PALMAS_CHARG_DET_N_VBUS_OVV_IRQ] = {
0174         .mask = PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV,
0175     },
0176     [PALMAS_PWRON_IRQ] = {
0177         .mask = PALMAS_INT1_STATUS_PWRON,
0178     },
0179     [PALMAS_LONG_PRESS_KEY_IRQ] = {
0180         .mask = PALMAS_INT1_STATUS_LONG_PRESS_KEY,
0181     },
0182     [PALMAS_RPWRON_IRQ] = {
0183         .mask = PALMAS_INT1_STATUS_RPWRON,
0184     },
0185     [PALMAS_PWRDOWN_IRQ] = {
0186         .mask = PALMAS_INT1_STATUS_PWRDOWN,
0187     },
0188     [PALMAS_HOTDIE_IRQ] = {
0189         .mask = PALMAS_INT1_STATUS_HOTDIE,
0190     },
0191     [PALMAS_VSYS_MON_IRQ] = {
0192         .mask = PALMAS_INT1_STATUS_VSYS_MON,
0193     },
0194     [PALMAS_VBAT_MON_IRQ] = {
0195         .mask = PALMAS_INT1_STATUS_VBAT_MON,
0196     },
0197     /* INT2 IRQs*/
0198     [PALMAS_RTC_ALARM_IRQ] = {
0199         .mask = PALMAS_INT2_STATUS_RTC_ALARM,
0200         .reg_offset = 1,
0201     },
0202     [PALMAS_RTC_TIMER_IRQ] = {
0203         .mask = PALMAS_INT2_STATUS_RTC_TIMER,
0204         .reg_offset = 1,
0205     },
0206     [PALMAS_WDT_IRQ] = {
0207         .mask = PALMAS_INT2_STATUS_WDT,
0208         .reg_offset = 1,
0209     },
0210     [PALMAS_BATREMOVAL_IRQ] = {
0211         .mask = PALMAS_INT2_STATUS_BATREMOVAL,
0212         .reg_offset = 1,
0213     },
0214     [PALMAS_RESET_IN_IRQ] = {
0215         .mask = PALMAS_INT2_STATUS_RESET_IN,
0216         .reg_offset = 1,
0217     },
0218     [PALMAS_FBI_BB_IRQ] = {
0219         .mask = PALMAS_INT2_STATUS_FBI_BB,
0220         .reg_offset = 1,
0221     },
0222     [PALMAS_SHORT_IRQ] = {
0223         .mask = PALMAS_INT2_STATUS_SHORT,
0224         .reg_offset = 1,
0225     },
0226     [PALMAS_VAC_ACOK_IRQ] = {
0227         .mask = PALMAS_INT2_STATUS_VAC_ACOK,
0228         .reg_offset = 1,
0229     },
0230     /* INT3 IRQs */
0231     [PALMAS_GPADC_AUTO_0_IRQ] = {
0232         .mask = PALMAS_INT3_STATUS_GPADC_AUTO_0,
0233         .reg_offset = 2,
0234     },
0235     [PALMAS_GPADC_AUTO_1_IRQ] = {
0236         .mask = PALMAS_INT3_STATUS_GPADC_AUTO_1,
0237         .reg_offset = 2,
0238     },
0239     [PALMAS_GPADC_EOC_SW_IRQ] = {
0240         .mask = PALMAS_INT3_STATUS_GPADC_EOC_SW,
0241         .reg_offset = 2,
0242     },
0243     [PALMAS_GPADC_EOC_RT_IRQ] = {
0244         .mask = PALMAS_INT3_STATUS_GPADC_EOC_RT,
0245         .reg_offset = 2,
0246     },
0247     [PALMAS_ID_OTG_IRQ] = {
0248         .mask = PALMAS_INT3_STATUS_ID_OTG,
0249         .reg_offset = 2,
0250     },
0251     [PALMAS_ID_IRQ] = {
0252         .mask = PALMAS_INT3_STATUS_ID,
0253         .reg_offset = 2,
0254     },
0255     [PALMAS_VBUS_OTG_IRQ] = {
0256         .mask = PALMAS_INT3_STATUS_VBUS_OTG,
0257         .reg_offset = 2,
0258     },
0259     [PALMAS_VBUS_IRQ] = {
0260         .mask = PALMAS_INT3_STATUS_VBUS,
0261         .reg_offset = 2,
0262     },
0263     /* INT4 IRQs */
0264     [PALMAS_GPIO_0_IRQ] = {
0265         .mask = PALMAS_INT4_STATUS_GPIO_0,
0266         .reg_offset = 3,
0267     },
0268     [PALMAS_GPIO_1_IRQ] = {
0269         .mask = PALMAS_INT4_STATUS_GPIO_1,
0270         .reg_offset = 3,
0271     },
0272     [PALMAS_GPIO_2_IRQ] = {
0273         .mask = PALMAS_INT4_STATUS_GPIO_2,
0274         .reg_offset = 3,
0275     },
0276     [PALMAS_GPIO_3_IRQ] = {
0277         .mask = PALMAS_INT4_STATUS_GPIO_3,
0278         .reg_offset = 3,
0279     },
0280     [PALMAS_GPIO_4_IRQ] = {
0281         .mask = PALMAS_INT4_STATUS_GPIO_4,
0282         .reg_offset = 3,
0283     },
0284     [PALMAS_GPIO_5_IRQ] = {
0285         .mask = PALMAS_INT4_STATUS_GPIO_5,
0286         .reg_offset = 3,
0287     },
0288     [PALMAS_GPIO_6_IRQ] = {
0289         .mask = PALMAS_INT4_STATUS_GPIO_6,
0290         .reg_offset = 3,
0291     },
0292     [PALMAS_GPIO_7_IRQ] = {
0293         .mask = PALMAS_INT4_STATUS_GPIO_7,
0294         .reg_offset = 3,
0295     },
0296 };
0297 
0298 static struct regmap_irq_chip palmas_irq_chip = {
0299     .name = "palmas",
0300     .irqs = palmas_irqs,
0301     .num_irqs = ARRAY_SIZE(palmas_irqs),
0302 
0303     .num_regs = 4,
0304     .irq_reg_stride = 5,
0305     .status_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
0306             PALMAS_INT1_STATUS),
0307     .mask_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
0308             PALMAS_INT1_MASK),
0309 };
0310 
0311 static struct regmap_irq_chip tps65917_irq_chip = {
0312     .name = "tps65917",
0313     .irqs = tps65917_irqs,
0314     .num_irqs = ARRAY_SIZE(tps65917_irqs),
0315 
0316     .num_regs = 4,
0317     .irq_reg_stride = 5,
0318     .status_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
0319             PALMAS_INT1_STATUS),
0320     .mask_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
0321             PALMAS_INT1_MASK),
0322 };
0323 
0324 int palmas_ext_control_req_config(struct palmas *palmas,
0325     enum palmas_external_requestor_id id,  int ext_ctrl, bool enable)
0326 {
0327     struct palmas_pmic_driver_data *pmic_ddata = palmas->pmic_ddata;
0328     int preq_mask_bit = 0;
0329     int reg_add = 0;
0330     int bit_pos, ret;
0331 
0332     if (!(ext_ctrl & PALMAS_EXT_REQ))
0333         return 0;
0334 
0335     if (id >= PALMAS_EXTERNAL_REQSTR_ID_MAX)
0336         return 0;
0337 
0338     if (ext_ctrl & PALMAS_EXT_CONTROL_NSLEEP) {
0339         reg_add = PALMAS_NSLEEP_RES_ASSIGN;
0340         preq_mask_bit = 0;
0341     } else if (ext_ctrl & PALMAS_EXT_CONTROL_ENABLE1) {
0342         reg_add = PALMAS_ENABLE1_RES_ASSIGN;
0343         preq_mask_bit = 1;
0344     } else if (ext_ctrl & PALMAS_EXT_CONTROL_ENABLE2) {
0345         reg_add = PALMAS_ENABLE2_RES_ASSIGN;
0346         preq_mask_bit = 2;
0347     }
0348 
0349     bit_pos = pmic_ddata->sleep_req_info[id].bit_pos;
0350     reg_add += pmic_ddata->sleep_req_info[id].reg_offset;
0351     if (enable)
0352         ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
0353                 reg_add, BIT(bit_pos), BIT(bit_pos));
0354     else
0355         ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
0356                 reg_add, BIT(bit_pos), 0);
0357     if (ret < 0) {
0358         dev_err(palmas->dev, "Resource reg 0x%02x update failed %d\n",
0359             reg_add, ret);
0360         return ret;
0361     }
0362 
0363     /* Unmask the PREQ */
0364     ret = palmas_update_bits(palmas, PALMAS_PMU_CONTROL_BASE,
0365             PALMAS_POWER_CTRL, BIT(preq_mask_bit), 0);
0366     if (ret < 0) {
0367         dev_err(palmas->dev, "POWER_CTRL register update failed %d\n",
0368             ret);
0369         return ret;
0370     }
0371     return ret;
0372 }
0373 EXPORT_SYMBOL_GPL(palmas_ext_control_req_config);
0374 
0375 static int palmas_set_pdata_irq_flag(struct i2c_client *i2c,
0376         struct palmas_platform_data *pdata)
0377 {
0378     struct irq_data *irq_data = irq_get_irq_data(i2c->irq);
0379     if (!irq_data) {
0380         dev_err(&i2c->dev, "Invalid IRQ: %d\n", i2c->irq);
0381         return -EINVAL;
0382     }
0383 
0384     pdata->irq_flags = irqd_get_trigger_type(irq_data);
0385     dev_info(&i2c->dev, "Irq flag is 0x%08x\n", pdata->irq_flags);
0386     return 0;
0387 }
0388 
0389 static void palmas_dt_to_pdata(struct i2c_client *i2c,
0390         struct palmas_platform_data *pdata)
0391 {
0392     struct device_node *node = i2c->dev.of_node;
0393     int ret;
0394     u32 prop;
0395 
0396     ret = of_property_read_u32(node, "ti,mux-pad1", &prop);
0397     if (!ret) {
0398         pdata->mux_from_pdata = 1;
0399         pdata->pad1 = prop;
0400     }
0401 
0402     ret = of_property_read_u32(node, "ti,mux-pad2", &prop);
0403     if (!ret) {
0404         pdata->mux_from_pdata = 1;
0405         pdata->pad2 = prop;
0406     }
0407 
0408     /* The default for this register is all masked */
0409     ret = of_property_read_u32(node, "ti,power-ctrl", &prop);
0410     if (!ret)
0411         pdata->power_ctrl = prop;
0412     else
0413         pdata->power_ctrl = PALMAS_POWER_CTRL_NSLEEP_MASK |
0414                     PALMAS_POWER_CTRL_ENABLE1_MASK |
0415                     PALMAS_POWER_CTRL_ENABLE2_MASK;
0416     if (i2c->irq)
0417         palmas_set_pdata_irq_flag(i2c, pdata);
0418 
0419     pdata->pm_off = of_property_read_bool(node,
0420             "ti,system-power-controller");
0421 }
0422 
0423 static struct palmas *palmas_dev;
0424 static void palmas_power_off(void)
0425 {
0426     unsigned int addr;
0427     int ret, slave;
0428     u8 powerhold_mask;
0429     struct device_node *np = palmas_dev->dev->of_node;
0430 
0431     if (of_property_read_bool(np, "ti,palmas-override-powerhold")) {
0432         addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
0433                       PALMAS_PRIMARY_SECONDARY_PAD2);
0434         slave = PALMAS_BASE_TO_SLAVE(PALMAS_PU_PD_OD_BASE);
0435 
0436         if (of_device_is_compatible(np, "ti,tps65917"))
0437             powerhold_mask =
0438                 TPS65917_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK;
0439         else
0440             powerhold_mask =
0441                 PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK;
0442 
0443         ret = regmap_update_bits(palmas_dev->regmap[slave], addr,
0444                      powerhold_mask, 0);
0445         if (ret)
0446             dev_err(palmas_dev->dev,
0447                 "Unable to write PRIMARY_SECONDARY_PAD2 %d\n",
0448                 ret);
0449     }
0450 
0451     slave = PALMAS_BASE_TO_SLAVE(PALMAS_PMU_CONTROL_BASE);
0452     addr = PALMAS_BASE_TO_REG(PALMAS_PMU_CONTROL_BASE, PALMAS_DEV_CTRL);
0453 
0454     ret = regmap_update_bits(
0455             palmas_dev->regmap[slave],
0456             addr,
0457             PALMAS_DEV_CTRL_DEV_ON,
0458             0);
0459 
0460     if (ret)
0461         pr_err("%s: Unable to write to DEV_CTRL_DEV_ON: %d\n",
0462                 __func__, ret);
0463 }
0464 
0465 static unsigned int palmas_features = PALMAS_PMIC_FEATURE_SMPS10_BOOST;
0466 static unsigned int tps659038_features;
0467 
0468 struct palmas_driver_data {
0469     unsigned int *features;
0470     struct regmap_irq_chip *irq_chip;
0471 };
0472 
0473 static struct palmas_driver_data palmas_data = {
0474     .features = &palmas_features,
0475     .irq_chip = &palmas_irq_chip,
0476 };
0477 
0478 static struct palmas_driver_data tps659038_data = {
0479     .features = &tps659038_features,
0480     .irq_chip = &palmas_irq_chip,
0481 };
0482 
0483 static struct palmas_driver_data tps65917_data = {
0484     .features = &tps659038_features,
0485     .irq_chip = &tps65917_irq_chip,
0486 };
0487 
0488 static const struct of_device_id of_palmas_match_tbl[] = {
0489     {
0490         .compatible = "ti,palmas",
0491         .data = &palmas_data,
0492     },
0493     {
0494         .compatible = "ti,tps659038",
0495         .data = &tps659038_data,
0496     },
0497     {
0498         .compatible = "ti,tps65917",
0499         .data = &tps65917_data,
0500     },
0501     { },
0502 };
0503 MODULE_DEVICE_TABLE(of, of_palmas_match_tbl);
0504 
0505 static int palmas_i2c_probe(struct i2c_client *i2c,
0506                 const struct i2c_device_id *id)
0507 {
0508     struct palmas *palmas;
0509     struct palmas_platform_data *pdata;
0510     struct palmas_driver_data *driver_data;
0511     struct device_node *node = i2c->dev.of_node;
0512     int ret = 0, i;
0513     unsigned int reg, addr;
0514     int slave;
0515     const struct of_device_id *match;
0516 
0517     pdata = dev_get_platdata(&i2c->dev);
0518 
0519     if (node && !pdata) {
0520         pdata = devm_kzalloc(&i2c->dev, sizeof(*pdata), GFP_KERNEL);
0521 
0522         if (!pdata)
0523             return -ENOMEM;
0524 
0525         palmas_dt_to_pdata(i2c, pdata);
0526     }
0527 
0528     if (!pdata)
0529         return -EINVAL;
0530 
0531     palmas = devm_kzalloc(&i2c->dev, sizeof(struct palmas), GFP_KERNEL);
0532     if (palmas == NULL)
0533         return -ENOMEM;
0534 
0535     i2c_set_clientdata(i2c, palmas);
0536     palmas->dev = &i2c->dev;
0537     palmas->irq = i2c->irq;
0538 
0539     match = of_match_device(of_palmas_match_tbl, &i2c->dev);
0540 
0541     if (!match)
0542         return -ENODATA;
0543 
0544     driver_data = (struct palmas_driver_data *)match->data;
0545     palmas->features = *driver_data->features;
0546 
0547     for (i = 0; i < PALMAS_NUM_CLIENTS; i++) {
0548         if (i == 0)
0549             palmas->i2c_clients[i] = i2c;
0550         else {
0551             palmas->i2c_clients[i] =
0552                     i2c_new_dummy_device(i2c->adapter,
0553                             i2c->addr + i);
0554             if (IS_ERR(palmas->i2c_clients[i])) {
0555                 dev_err(palmas->dev,
0556                     "can't attach client %d\n", i);
0557                 ret = PTR_ERR(palmas->i2c_clients[i]);
0558                 goto err_i2c;
0559             }
0560             palmas->i2c_clients[i]->dev.of_node = of_node_get(node);
0561         }
0562         palmas->regmap[i] = devm_regmap_init_i2c(palmas->i2c_clients[i],
0563                 &palmas_regmap_config[i]);
0564         if (IS_ERR(palmas->regmap[i])) {
0565             ret = PTR_ERR(palmas->regmap[i]);
0566             dev_err(palmas->dev,
0567                 "Failed to allocate regmap %d, err: %d\n",
0568                 i, ret);
0569             goto err_i2c;
0570         }
0571     }
0572 
0573     if (!palmas->irq) {
0574         dev_warn(palmas->dev, "IRQ missing: skipping irq request\n");
0575         goto no_irq;
0576     }
0577 
0578     /* Change interrupt line output polarity */
0579     if (pdata->irq_flags & IRQ_TYPE_LEVEL_HIGH)
0580         reg = PALMAS_POLARITY_CTRL_INT_POLARITY;
0581     else
0582         reg = 0;
0583     ret = palmas_update_bits(palmas, PALMAS_PU_PD_OD_BASE,
0584             PALMAS_POLARITY_CTRL, PALMAS_POLARITY_CTRL_INT_POLARITY,
0585             reg);
0586     if (ret < 0) {
0587         dev_err(palmas->dev, "POLARITY_CTRL update failed: %d\n", ret);
0588         goto err_i2c;
0589     }
0590 
0591     /* Change IRQ into clear on read mode for efficiency */
0592     slave = PALMAS_BASE_TO_SLAVE(PALMAS_INTERRUPT_BASE);
0593     addr = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE, PALMAS_INT_CTRL);
0594     reg = PALMAS_INT_CTRL_INT_CLEAR;
0595 
0596     regmap_write(palmas->regmap[slave], addr, reg);
0597 
0598     ret = regmap_add_irq_chip(palmas->regmap[slave], palmas->irq,
0599                   IRQF_ONESHOT | pdata->irq_flags, 0,
0600                   driver_data->irq_chip, &palmas->irq_data);
0601     if (ret < 0)
0602         goto err_i2c;
0603 
0604 no_irq:
0605     slave = PALMAS_BASE_TO_SLAVE(PALMAS_PU_PD_OD_BASE);
0606     addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
0607             PALMAS_PRIMARY_SECONDARY_PAD1);
0608 
0609     if (pdata->mux_from_pdata) {
0610         reg = pdata->pad1;
0611         ret = regmap_write(palmas->regmap[slave], addr, reg);
0612         if (ret)
0613             goto err_irq;
0614     } else {
0615         ret = regmap_read(palmas->regmap[slave], addr, &reg);
0616         if (ret)
0617             goto err_irq;
0618     }
0619 
0620     if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0))
0621         palmas->gpio_muxed |= PALMAS_GPIO_0_MUXED;
0622     if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK))
0623         palmas->gpio_muxed |= PALMAS_GPIO_1_MUXED;
0624     else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) ==
0625             (2 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT))
0626         palmas->led_muxed |= PALMAS_LED1_MUXED;
0627     else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) ==
0628             (3 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT))
0629         palmas->pwm_muxed |= PALMAS_PWM1_MUXED;
0630     if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK))
0631         palmas->gpio_muxed |= PALMAS_GPIO_2_MUXED;
0632     else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) ==
0633             (2 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT))
0634         palmas->led_muxed |= PALMAS_LED2_MUXED;
0635     else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) ==
0636             (3 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT))
0637         palmas->pwm_muxed |= PALMAS_PWM2_MUXED;
0638     if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3))
0639         palmas->gpio_muxed |= PALMAS_GPIO_3_MUXED;
0640 
0641     addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
0642             PALMAS_PRIMARY_SECONDARY_PAD2);
0643 
0644     if (pdata->mux_from_pdata) {
0645         reg = pdata->pad2;
0646         ret = regmap_write(palmas->regmap[slave], addr, reg);
0647         if (ret)
0648             goto err_irq;
0649     } else {
0650         ret = regmap_read(palmas->regmap[slave], addr, &reg);
0651         if (ret)
0652             goto err_irq;
0653     }
0654 
0655     if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4))
0656         palmas->gpio_muxed |= PALMAS_GPIO_4_MUXED;
0657     if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK))
0658         palmas->gpio_muxed |= PALMAS_GPIO_5_MUXED;
0659     if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6))
0660         palmas->gpio_muxed |= PALMAS_GPIO_6_MUXED;
0661     if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK))
0662         palmas->gpio_muxed |= PALMAS_GPIO_7_MUXED;
0663 
0664     dev_info(palmas->dev, "Muxing GPIO %x, PWM %x, LED %x\n",
0665             palmas->gpio_muxed, palmas->pwm_muxed,
0666             palmas->led_muxed);
0667 
0668     reg = pdata->power_ctrl;
0669 
0670     slave = PALMAS_BASE_TO_SLAVE(PALMAS_PMU_CONTROL_BASE);
0671     addr = PALMAS_BASE_TO_REG(PALMAS_PMU_CONTROL_BASE, PALMAS_POWER_CTRL);
0672 
0673     ret = regmap_write(palmas->regmap[slave], addr, reg);
0674     if (ret)
0675         goto err_irq;
0676 
0677     /*
0678      * If we are probing with DT do this the DT way and return here
0679      * otherwise continue and add devices using mfd helpers.
0680      */
0681     if (node) {
0682         ret = devm_of_platform_populate(&i2c->dev);
0683         if (ret < 0) {
0684             goto err_irq;
0685         } else if (pdata->pm_off && !pm_power_off) {
0686             palmas_dev = palmas;
0687             pm_power_off = palmas_power_off;
0688         }
0689     }
0690 
0691     return ret;
0692 
0693 err_irq:
0694     regmap_del_irq_chip(palmas->irq, palmas->irq_data);
0695 err_i2c:
0696     for (i = 1; i < PALMAS_NUM_CLIENTS; i++) {
0697         if (palmas->i2c_clients[i])
0698             i2c_unregister_device(palmas->i2c_clients[i]);
0699     }
0700     return ret;
0701 }
0702 
0703 static int palmas_i2c_remove(struct i2c_client *i2c)
0704 {
0705     struct palmas *palmas = i2c_get_clientdata(i2c);
0706     int i;
0707 
0708     regmap_del_irq_chip(palmas->irq, palmas->irq_data);
0709 
0710     for (i = 1; i < PALMAS_NUM_CLIENTS; i++) {
0711         if (palmas->i2c_clients[i])
0712             i2c_unregister_device(palmas->i2c_clients[i]);
0713     }
0714 
0715     if (palmas == palmas_dev) {
0716         pm_power_off = NULL;
0717         palmas_dev = NULL;
0718     }
0719 
0720     return 0;
0721 }
0722 
0723 static const struct i2c_device_id palmas_i2c_id[] = {
0724     { "palmas", },
0725     { "twl6035", },
0726     { "twl6037", },
0727     { "tps65913", },
0728     { /* end */ }
0729 };
0730 MODULE_DEVICE_TABLE(i2c, palmas_i2c_id);
0731 
0732 static struct i2c_driver palmas_i2c_driver = {
0733     .driver = {
0734            .name = "palmas",
0735            .of_match_table = of_palmas_match_tbl,
0736     },
0737     .probe = palmas_i2c_probe,
0738     .remove = palmas_i2c_remove,
0739     .id_table = palmas_i2c_id,
0740 };
0741 
0742 static int __init palmas_i2c_init(void)
0743 {
0744     return i2c_add_driver(&palmas_i2c_driver);
0745 }
0746 /* init early so consumer devices can complete system boot */
0747 subsys_initcall(palmas_i2c_init);
0748 
0749 static void __exit palmas_i2c_exit(void)
0750 {
0751     i2c_del_driver(&palmas_i2c_driver);
0752 }
0753 module_exit(palmas_i2c_exit);
0754 
0755 MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
0756 MODULE_DESCRIPTION("Palmas chip family multi-function driver");
0757 MODULE_LICENSE("GPL");
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