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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI
0004  *
0005  * Copyright (C) 2011-2013 Texas Instruments Incorporated - https://www.ti.com
0006  * Author: Keshava Munegowda <keshava_mgowda@ti.com>
0007  * Author: Roger Quadros <rogerq@ti.com>
0008  */
0009 #include <linux/kernel.h>
0010 #include <linux/module.h>
0011 #include <linux/types.h>
0012 #include <linux/slab.h>
0013 #include <linux/delay.h>
0014 #include <linux/clk.h>
0015 #include <linux/dma-mapping.h>
0016 #include <linux/gpio.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/platform_data/usb-omap.h>
0019 #include <linux/pm_runtime.h>
0020 #include <linux/of.h>
0021 #include <linux/of_platform.h>
0022 #include <linux/err.h>
0023 
0024 #include "omap-usb.h"
0025 
0026 #define USBHS_DRIVER_NAME   "usbhs_omap"
0027 #define OMAP_EHCI_DEVICE    "ehci-omap"
0028 #define OMAP_OHCI_DEVICE    "ohci-omap3"
0029 
0030 /* OMAP USBHOST Register addresses  */
0031 
0032 /* UHH Register Set */
0033 #define OMAP_UHH_REVISION               (0x00)
0034 #define OMAP_UHH_SYSCONFIG              (0x10)
0035 #define OMAP_UHH_SYSCONFIG_MIDLEMODE            (1 << 12)
0036 #define OMAP_UHH_SYSCONFIG_CACTIVITY            (1 << 8)
0037 #define OMAP_UHH_SYSCONFIG_SIDLEMODE            (1 << 3)
0038 #define OMAP_UHH_SYSCONFIG_ENAWAKEUP            (1 << 2)
0039 #define OMAP_UHH_SYSCONFIG_SOFTRESET            (1 << 1)
0040 #define OMAP_UHH_SYSCONFIG_AUTOIDLE         (1 << 0)
0041 
0042 #define OMAP_UHH_SYSSTATUS              (0x14)
0043 #define OMAP_UHH_HOSTCONFIG             (0x40)
0044 #define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS         (1 << 0)
0045 #define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS      (1 << 0)
0046 #define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS      (1 << 11)
0047 #define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS      (1 << 12)
0048 #define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN      (1 << 2)
0049 #define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN      (1 << 3)
0050 #define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN     (1 << 4)
0051 #define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN      (1 << 5)
0052 #define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS       (1 << 8)
0053 #define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS       (1 << 9)
0054 #define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS       (1 << 10)
0055 #define OMAP4_UHH_HOSTCONFIG_APP_START_CLK      (1 << 31)
0056 
0057 /* OMAP4-specific defines */
0058 #define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR      (3 << 2)
0059 #define OMAP4_UHH_SYSCONFIG_NOIDLE          (1 << 2)
0060 #define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR     (3 << 4)
0061 #define OMAP4_UHH_SYSCONFIG_NOSTDBY         (1 << 4)
0062 #define OMAP4_UHH_SYSCONFIG_SOFTRESET           (1 << 0)
0063 
0064 #define OMAP4_P1_MODE_CLEAR             (3 << 16)
0065 #define OMAP4_P1_MODE_TLL               (1 << 16)
0066 #define OMAP4_P1_MODE_HSIC              (3 << 16)
0067 #define OMAP4_P2_MODE_CLEAR             (3 << 18)
0068 #define OMAP4_P2_MODE_TLL               (1 << 18)
0069 #define OMAP4_P2_MODE_HSIC              (3 << 18)
0070 
0071 #define OMAP_UHH_DEBUG_CSR              (0x44)
0072 
0073 /* Values of UHH_REVISION - Note: these are not given in the TRM */
0074 #define OMAP_USBHS_REV1     0x00000010  /* OMAP3 */
0075 #define OMAP_USBHS_REV2     0x50700100  /* OMAP4 */
0076 
0077 #define is_omap_usbhs_rev1(x)   (x->usbhs_rev == OMAP_USBHS_REV1)
0078 #define is_omap_usbhs_rev2(x)   (x->usbhs_rev == OMAP_USBHS_REV2)
0079 
0080 #define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY)
0081 #define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL)
0082 #define is_ehci_hsic_mode(x)    (x == OMAP_EHCI_PORT_MODE_HSIC)
0083 
0084 
0085 struct usbhs_hcd_omap {
0086     int             nports;
0087     struct clk          **utmi_clk;
0088     struct clk          **hsic60m_clk;
0089     struct clk          **hsic480m_clk;
0090 
0091     struct clk          *xclk60mhsp1_ck;
0092     struct clk          *xclk60mhsp2_ck;
0093     struct clk          *utmi_p1_gfclk;
0094     struct clk          *utmi_p2_gfclk;
0095     struct clk          *init_60m_fclk;
0096     struct clk          *ehci_logic_fck;
0097 
0098     void __iomem            *uhh_base;
0099 
0100     struct usbhs_omap_platform_data *pdata;
0101 
0102     u32             usbhs_rev;
0103 };
0104 /*-------------------------------------------------------------------------*/
0105 
0106 static const char usbhs_driver_name[] = USBHS_DRIVER_NAME;
0107 static u64 usbhs_dmamask = DMA_BIT_MASK(32);
0108 
0109 /*-------------------------------------------------------------------------*/
0110 
0111 static inline void usbhs_write(void __iomem *base, u32 reg, u32 val)
0112 {
0113     writel_relaxed(val, base + reg);
0114 }
0115 
0116 static inline u32 usbhs_read(void __iomem *base, u32 reg)
0117 {
0118     return readl_relaxed(base + reg);
0119 }
0120 
0121 /*-------------------------------------------------------------------------*/
0122 
0123 /*
0124  * Map 'enum usbhs_omap_port_mode' found in <linux/platform_data/usb-omap.h>
0125  * to the device tree binding portN-mode found in
0126  * 'Documentation/devicetree/bindings/mfd/omap-usb-host.txt'
0127  */
0128 static const char * const port_modes[] = {
0129     [OMAP_USBHS_PORT_MODE_UNUSED]   = "",
0130     [OMAP_EHCI_PORT_MODE_PHY]   = "ehci-phy",
0131     [OMAP_EHCI_PORT_MODE_TLL]   = "ehci-tll",
0132     [OMAP_EHCI_PORT_MODE_HSIC]  = "ehci-hsic",
0133     [OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0]   = "ohci-phy-6pin-datse0",
0134     [OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM] = "ohci-phy-6pin-dpdm",
0135     [OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0]   = "ohci-phy-3pin-datse0",
0136     [OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM] = "ohci-phy-4pin-dpdm",
0137     [OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0]   = "ohci-tll-6pin-datse0",
0138     [OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM] = "ohci-tll-6pin-dpdm",
0139     [OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0]   = "ohci-tll-3pin-datse0",
0140     [OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM] = "ohci-tll-4pin-dpdm",
0141     [OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0]   = "ohci-tll-2pin-datse0",
0142     [OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM] = "ohci-tll-2pin-dpdm",
0143 };
0144 
0145 static struct platform_device *omap_usbhs_alloc_child(const char *name,
0146             struct resource *res, int num_resources, void *pdata,
0147             size_t pdata_size, struct device *dev)
0148 {
0149     struct platform_device  *child;
0150     int         ret;
0151 
0152     child = platform_device_alloc(name, 0);
0153 
0154     if (!child) {
0155         dev_err(dev, "platform_device_alloc %s failed\n", name);
0156         goto err_end;
0157     }
0158 
0159     ret = platform_device_add_resources(child, res, num_resources);
0160     if (ret) {
0161         dev_err(dev, "platform_device_add_resources failed\n");
0162         goto err_alloc;
0163     }
0164 
0165     ret = platform_device_add_data(child, pdata, pdata_size);
0166     if (ret) {
0167         dev_err(dev, "platform_device_add_data failed\n");
0168         goto err_alloc;
0169     }
0170 
0171     child->dev.dma_mask     = &usbhs_dmamask;
0172     dma_set_coherent_mask(&child->dev, DMA_BIT_MASK(32));
0173     child->dev.parent       = dev;
0174 
0175     ret = platform_device_add(child);
0176     if (ret) {
0177         dev_err(dev, "platform_device_add failed\n");
0178         goto err_alloc;
0179     }
0180 
0181     return child;
0182 
0183 err_alloc:
0184     platform_device_put(child);
0185 
0186 err_end:
0187     return NULL;
0188 }
0189 
0190 static int omap_usbhs_alloc_children(struct platform_device *pdev)
0191 {
0192     struct device               *dev = &pdev->dev;
0193     struct usbhs_omap_platform_data     *pdata = dev_get_platdata(dev);
0194     struct platform_device          *ehci;
0195     struct platform_device          *ohci;
0196     struct resource             *res;
0197     struct resource             resources[2];
0198     int                 ret;
0199 
0200     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci");
0201     if (!res) {
0202         dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n");
0203         ret = -ENODEV;
0204         goto err_end;
0205     }
0206     resources[0] = *res;
0207 
0208     res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq");
0209     if (!res) {
0210         dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n");
0211         ret = -ENODEV;
0212         goto err_end;
0213     }
0214     resources[1] = *res;
0215 
0216     ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, pdata,
0217         sizeof(*pdata), dev);
0218 
0219     if (!ehci) {
0220         dev_err(dev, "omap_usbhs_alloc_child failed\n");
0221         ret = -ENOMEM;
0222         goto err_end;
0223     }
0224 
0225     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci");
0226     if (!res) {
0227         dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n");
0228         ret = -ENODEV;
0229         goto err_ehci;
0230     }
0231     resources[0] = *res;
0232 
0233     res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq");
0234     if (!res) {
0235         dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n");
0236         ret = -ENODEV;
0237         goto err_ehci;
0238     }
0239     resources[1] = *res;
0240 
0241     ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, pdata,
0242         sizeof(*pdata), dev);
0243     if (!ohci) {
0244         dev_err(dev, "omap_usbhs_alloc_child failed\n");
0245         ret = -ENOMEM;
0246         goto err_ehci;
0247     }
0248 
0249     return 0;
0250 
0251 err_ehci:
0252     platform_device_unregister(ehci);
0253 
0254 err_end:
0255     return ret;
0256 }
0257 
0258 static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
0259 {
0260     switch (pmode) {
0261     case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
0262     case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
0263     case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
0264     case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
0265     case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
0266     case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
0267     case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
0268     case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
0269     case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
0270     case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
0271         return true;
0272 
0273     default:
0274         return false;
0275     }
0276 }
0277 
0278 static int usbhs_runtime_resume(struct device *dev)
0279 {
0280     struct usbhs_hcd_omap       *omap = dev_get_drvdata(dev);
0281     struct usbhs_omap_platform_data *pdata = omap->pdata;
0282     int i, r;
0283 
0284     dev_dbg(dev, "usbhs_runtime_resume\n");
0285 
0286     omap_tll_enable(pdata);
0287 
0288     if (!IS_ERR(omap->ehci_logic_fck))
0289         clk_prepare_enable(omap->ehci_logic_fck);
0290 
0291     for (i = 0; i < omap->nports; i++) {
0292         switch (pdata->port_mode[i]) {
0293         case OMAP_EHCI_PORT_MODE_HSIC:
0294             if (!IS_ERR(omap->hsic60m_clk[i])) {
0295                 r = clk_prepare_enable(omap->hsic60m_clk[i]);
0296                 if (r) {
0297                     dev_err(dev,
0298                      "Can't enable port %d hsic60m clk:%d\n",
0299                      i, r);
0300                 }
0301             }
0302 
0303             if (!IS_ERR(omap->hsic480m_clk[i])) {
0304                 r = clk_prepare_enable(omap->hsic480m_clk[i]);
0305                 if (r) {
0306                     dev_err(dev,
0307                      "Can't enable port %d hsic480m clk:%d\n",
0308                      i, r);
0309                 }
0310             }
0311             fallthrough;    /* as HSIC mode needs utmi_clk */
0312 
0313         case OMAP_EHCI_PORT_MODE_TLL:
0314             if (!IS_ERR(omap->utmi_clk[i])) {
0315                 r = clk_prepare_enable(omap->utmi_clk[i]);
0316                 if (r) {
0317                     dev_err(dev,
0318                      "Can't enable port %d clk : %d\n",
0319                      i, r);
0320                 }
0321             }
0322             break;
0323         default:
0324             break;
0325         }
0326     }
0327 
0328     return 0;
0329 }
0330 
0331 static int usbhs_runtime_suspend(struct device *dev)
0332 {
0333     struct usbhs_hcd_omap       *omap = dev_get_drvdata(dev);
0334     struct usbhs_omap_platform_data *pdata = omap->pdata;
0335     int i;
0336 
0337     dev_dbg(dev, "usbhs_runtime_suspend\n");
0338 
0339     for (i = 0; i < omap->nports; i++) {
0340         switch (pdata->port_mode[i]) {
0341         case OMAP_EHCI_PORT_MODE_HSIC:
0342             if (!IS_ERR(omap->hsic60m_clk[i]))
0343                 clk_disable_unprepare(omap->hsic60m_clk[i]);
0344 
0345             if (!IS_ERR(omap->hsic480m_clk[i]))
0346                 clk_disable_unprepare(omap->hsic480m_clk[i]);
0347             fallthrough;    /* as utmi_clks were used in HSIC mode */
0348 
0349         case OMAP_EHCI_PORT_MODE_TLL:
0350             if (!IS_ERR(omap->utmi_clk[i]))
0351                 clk_disable_unprepare(omap->utmi_clk[i]);
0352             break;
0353         default:
0354             break;
0355         }
0356     }
0357 
0358     if (!IS_ERR(omap->ehci_logic_fck))
0359         clk_disable_unprepare(omap->ehci_logic_fck);
0360 
0361     omap_tll_disable(pdata);
0362 
0363     return 0;
0364 }
0365 
0366 static unsigned omap_usbhs_rev1_hostconfig(struct usbhs_hcd_omap *omap,
0367                         unsigned reg)
0368 {
0369     struct usbhs_omap_platform_data *pdata = omap->pdata;
0370     int i;
0371 
0372     for (i = 0; i < omap->nports; i++) {
0373         switch (pdata->port_mode[i]) {
0374         case OMAP_USBHS_PORT_MODE_UNUSED:
0375             reg &= ~(OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS << i);
0376             break;
0377         case OMAP_EHCI_PORT_MODE_PHY:
0378             if (pdata->single_ulpi_bypass)
0379                 break;
0380 
0381             if (i == 0)
0382                 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
0383             else
0384                 reg &= ~(OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS
0385                                 << (i-1));
0386             break;
0387         default:
0388             if (pdata->single_ulpi_bypass)
0389                 break;
0390 
0391             if (i == 0)
0392                 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
0393             else
0394                 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS
0395                                 << (i-1);
0396             break;
0397         }
0398     }
0399 
0400     if (pdata->single_ulpi_bypass) {
0401         /* bypass ULPI only if none of the ports use PHY mode */
0402         reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
0403 
0404         for (i = 0; i < omap->nports; i++) {
0405             if (is_ehci_phy_mode(pdata->port_mode[i])) {
0406                 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
0407                 break;
0408             }
0409         }
0410     }
0411 
0412     return reg;
0413 }
0414 
0415 static unsigned omap_usbhs_rev2_hostconfig(struct usbhs_hcd_omap *omap,
0416                         unsigned reg)
0417 {
0418     struct usbhs_omap_platform_data *pdata = omap->pdata;
0419     int i;
0420 
0421     for (i = 0; i < omap->nports; i++) {
0422         /* Clear port mode fields for PHY mode */
0423         reg &= ~(OMAP4_P1_MODE_CLEAR << 2 * i);
0424 
0425         if (is_ehci_tll_mode(pdata->port_mode[i]) ||
0426                 (is_ohci_port(pdata->port_mode[i])))
0427             reg |= OMAP4_P1_MODE_TLL << 2 * i;
0428         else if (is_ehci_hsic_mode(pdata->port_mode[i]))
0429             reg |= OMAP4_P1_MODE_HSIC << 2 * i;
0430     }
0431 
0432     return reg;
0433 }
0434 
0435 static void omap_usbhs_init(struct device *dev)
0436 {
0437     struct usbhs_hcd_omap       *omap = dev_get_drvdata(dev);
0438     unsigned            reg;
0439 
0440     dev_dbg(dev, "starting TI HSUSB Controller\n");
0441 
0442     pm_runtime_get_sync(dev);
0443 
0444     reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
0445     /* setup ULPI bypass and burst configurations */
0446     reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
0447             | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
0448             | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
0449     reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK;
0450     reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
0451 
0452     switch (omap->usbhs_rev) {
0453     case OMAP_USBHS_REV1:
0454         reg = omap_usbhs_rev1_hostconfig(omap, reg);
0455         break;
0456 
0457     case OMAP_USBHS_REV2:
0458         reg = omap_usbhs_rev2_hostconfig(omap, reg);
0459         break;
0460 
0461     default:    /* newer revisions */
0462         reg = omap_usbhs_rev2_hostconfig(omap, reg);
0463         break;
0464     }
0465 
0466     usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
0467     dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
0468 
0469     pm_runtime_put_sync(dev);
0470 }
0471 
0472 static int usbhs_omap_get_dt_pdata(struct device *dev,
0473                     struct usbhs_omap_platform_data *pdata)
0474 {
0475     int ret, i;
0476     struct device_node *node = dev->of_node;
0477 
0478     ret = of_property_read_u32(node, "num-ports", &pdata->nports);
0479     if (ret)
0480         pdata->nports = 0;
0481 
0482     if (pdata->nports > OMAP3_HS_USB_PORTS) {
0483         dev_warn(dev, "Too many num_ports <%d> in device tree. Max %d\n",
0484                 pdata->nports, OMAP3_HS_USB_PORTS);
0485         return -ENODEV;
0486     }
0487 
0488     /* get port modes */
0489     for (i = 0; i < OMAP3_HS_USB_PORTS; i++) {
0490         char prop[11];
0491         const char *mode;
0492 
0493         pdata->port_mode[i] = OMAP_USBHS_PORT_MODE_UNUSED;
0494 
0495         snprintf(prop, sizeof(prop), "port%d-mode", i + 1);
0496         ret = of_property_read_string(node, prop, &mode);
0497         if (ret < 0)
0498             continue;
0499 
0500         /* get 'enum usbhs_omap_port_mode' from port mode string */
0501         ret = match_string(port_modes, ARRAY_SIZE(port_modes), mode);
0502         if (ret < 0) {
0503             dev_warn(dev, "Invalid port%d-mode \"%s\" in device tree\n",
0504                     i, mode);
0505             return -ENODEV;
0506         }
0507 
0508         dev_dbg(dev, "port%d-mode: %s -> %d\n", i, mode, ret);
0509         pdata->port_mode[i] = ret;
0510     }
0511 
0512     /* get flags */
0513     pdata->single_ulpi_bypass = of_property_read_bool(node,
0514                         "single-ulpi-bypass");
0515 
0516     return 0;
0517 }
0518 
0519 static const struct of_device_id usbhs_child_match_table[] = {
0520     { .compatible = "ti,ehci-omap", },
0521     { .compatible = "ti,ohci-omap3", },
0522     { }
0523 };
0524 
0525 /**
0526  * usbhs_omap_probe - initialize TI-based HCDs
0527  *
0528  * Allocates basic resources for this USB host controller.
0529  *
0530  * @pdev: Pointer to this device's platform device structure
0531  */
0532 static int usbhs_omap_probe(struct platform_device *pdev)
0533 {
0534     struct device           *dev =  &pdev->dev;
0535     struct usbhs_omap_platform_data *pdata = dev_get_platdata(dev);
0536     struct usbhs_hcd_omap       *omap;
0537     struct resource         *res;
0538     int             ret = 0;
0539     int             i;
0540     bool                need_logic_fck;
0541 
0542     if (dev->of_node) {
0543         /* For DT boot we populate platform data from OF node */
0544         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
0545         if (!pdata)
0546             return -ENOMEM;
0547 
0548         ret = usbhs_omap_get_dt_pdata(dev, pdata);
0549         if (ret)
0550             return ret;
0551 
0552         dev->platform_data = pdata;
0553     }
0554 
0555     if (!pdata) {
0556         dev_err(dev, "Missing platform data\n");
0557         return -ENODEV;
0558     }
0559 
0560     if (pdata->nports > OMAP3_HS_USB_PORTS) {
0561         dev_info(dev, "Too many num_ports <%d> in platform_data. Max %d\n",
0562                 pdata->nports, OMAP3_HS_USB_PORTS);
0563         return -ENODEV;
0564     }
0565 
0566     omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
0567     if (!omap) {
0568         dev_err(dev, "Memory allocation failed\n");
0569         return -ENOMEM;
0570     }
0571 
0572     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0573     omap->uhh_base = devm_ioremap_resource(dev, res);
0574     if (IS_ERR(omap->uhh_base))
0575         return PTR_ERR(omap->uhh_base);
0576 
0577     omap->pdata = pdata;
0578 
0579     /* Initialize the TLL subsystem */
0580     omap_tll_init(pdata);
0581 
0582     pm_runtime_enable(dev);
0583 
0584     platform_set_drvdata(pdev, omap);
0585     pm_runtime_get_sync(dev);
0586 
0587     omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION);
0588 
0589     /* we need to call runtime suspend before we update omap->nports
0590      * to prevent unbalanced clk_disable()
0591      */
0592     pm_runtime_put_sync(dev);
0593 
0594     /*
0595      * If platform data contains nports then use that
0596      * else make out number of ports from USBHS revision
0597      */
0598     if (pdata->nports) {
0599         omap->nports = pdata->nports;
0600     } else {
0601         switch (omap->usbhs_rev) {
0602         case OMAP_USBHS_REV1:
0603             omap->nports = 3;
0604             break;
0605         case OMAP_USBHS_REV2:
0606             omap->nports = 2;
0607             break;
0608         default:
0609             omap->nports = OMAP3_HS_USB_PORTS;
0610             dev_dbg(dev,
0611              "USB HOST Rev:0x%x not recognized, assuming %d ports\n",
0612              omap->usbhs_rev, omap->nports);
0613             break;
0614         }
0615         pdata->nports = omap->nports;
0616     }
0617 
0618     i = sizeof(struct clk *) * omap->nports;
0619     omap->utmi_clk = devm_kzalloc(dev, i, GFP_KERNEL);
0620     omap->hsic480m_clk = devm_kzalloc(dev, i, GFP_KERNEL);
0621     omap->hsic60m_clk = devm_kzalloc(dev, i, GFP_KERNEL);
0622 
0623     if (!omap->utmi_clk || !omap->hsic480m_clk || !omap->hsic60m_clk) {
0624         dev_err(dev, "Memory allocation failed\n");
0625         ret = -ENOMEM;
0626         goto err_mem;
0627     }
0628 
0629     /* Set all clocks as invalid to begin with */
0630     omap->ehci_logic_fck = ERR_PTR(-ENODEV);
0631     omap->init_60m_fclk = ERR_PTR(-ENODEV);
0632     omap->utmi_p1_gfclk = ERR_PTR(-ENODEV);
0633     omap->utmi_p2_gfclk = ERR_PTR(-ENODEV);
0634     omap->xclk60mhsp1_ck = ERR_PTR(-ENODEV);
0635     omap->xclk60mhsp2_ck = ERR_PTR(-ENODEV);
0636 
0637     for (i = 0; i < omap->nports; i++) {
0638         omap->utmi_clk[i] = ERR_PTR(-ENODEV);
0639         omap->hsic480m_clk[i] = ERR_PTR(-ENODEV);
0640         omap->hsic60m_clk[i] = ERR_PTR(-ENODEV);
0641     }
0642 
0643     /* for OMAP3 i.e. USBHS REV1 */
0644     if (omap->usbhs_rev == OMAP_USBHS_REV1) {
0645         need_logic_fck = false;
0646         for (i = 0; i < omap->nports; i++) {
0647             if (is_ehci_phy_mode(pdata->port_mode[i]) ||
0648                 is_ehci_tll_mode(pdata->port_mode[i]) ||
0649                 is_ehci_hsic_mode(pdata->port_mode[i]))
0650 
0651                 need_logic_fck |= true;
0652         }
0653 
0654         if (need_logic_fck) {
0655             omap->ehci_logic_fck = devm_clk_get(dev,
0656                                 "usbhost_120m_fck");
0657             if (IS_ERR(omap->ehci_logic_fck)) {
0658                 ret = PTR_ERR(omap->ehci_logic_fck);
0659                 dev_err(dev, "usbhost_120m_fck failed:%d\n",
0660                     ret);
0661                 goto err_mem;
0662             }
0663         }
0664         goto initialize;
0665     }
0666 
0667     /* for OMAP4+ i.e. USBHS REV2+ */
0668     omap->utmi_p1_gfclk = devm_clk_get(dev, "utmi_p1_gfclk");
0669     if (IS_ERR(omap->utmi_p1_gfclk)) {
0670         ret = PTR_ERR(omap->utmi_p1_gfclk);
0671         dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret);
0672         goto err_mem;
0673     }
0674 
0675     omap->utmi_p2_gfclk = devm_clk_get(dev, "utmi_p2_gfclk");
0676     if (IS_ERR(omap->utmi_p2_gfclk)) {
0677         ret = PTR_ERR(omap->utmi_p2_gfclk);
0678         dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
0679         goto err_mem;
0680     }
0681 
0682     omap->xclk60mhsp1_ck = devm_clk_get(dev, "refclk_60m_ext_p1");
0683     if (IS_ERR(omap->xclk60mhsp1_ck)) {
0684         ret = PTR_ERR(omap->xclk60mhsp1_ck);
0685         dev_err(dev, "refclk_60m_ext_p1 failed error:%d\n", ret);
0686         goto err_mem;
0687     }
0688 
0689     omap->xclk60mhsp2_ck = devm_clk_get(dev, "refclk_60m_ext_p2");
0690     if (IS_ERR(omap->xclk60mhsp2_ck)) {
0691         ret = PTR_ERR(omap->xclk60mhsp2_ck);
0692         dev_err(dev, "refclk_60m_ext_p2 failed error:%d\n", ret);
0693         goto err_mem;
0694     }
0695 
0696     omap->init_60m_fclk = devm_clk_get(dev, "refclk_60m_int");
0697     if (IS_ERR(omap->init_60m_fclk)) {
0698         ret = PTR_ERR(omap->init_60m_fclk);
0699         dev_err(dev, "refclk_60m_int failed error:%d\n", ret);
0700         goto err_mem;
0701     }
0702 
0703     for (i = 0; i < omap->nports; i++) {
0704         char clkname[30];
0705 
0706         /* clock names are indexed from 1*/
0707         snprintf(clkname, sizeof(clkname),
0708                 "usb_host_hs_utmi_p%d_clk", i + 1);
0709 
0710         /* If a clock is not found we won't bail out as not all
0711          * platforms have all clocks and we can function without
0712          * them
0713          */
0714         omap->utmi_clk[i] = devm_clk_get(dev, clkname);
0715         if (IS_ERR(omap->utmi_clk[i])) {
0716             ret = PTR_ERR(omap->utmi_clk[i]);
0717             dev_err(dev, "Failed to get clock : %s : %d\n",
0718                 clkname, ret);
0719             goto err_mem;
0720         }
0721 
0722         snprintf(clkname, sizeof(clkname),
0723                 "usb_host_hs_hsic480m_p%d_clk", i + 1);
0724         omap->hsic480m_clk[i] = devm_clk_get(dev, clkname);
0725         if (IS_ERR(omap->hsic480m_clk[i])) {
0726             ret = PTR_ERR(omap->hsic480m_clk[i]);
0727             dev_err(dev, "Failed to get clock : %s : %d\n",
0728                 clkname, ret);
0729             goto err_mem;
0730         }
0731 
0732         snprintf(clkname, sizeof(clkname),
0733                 "usb_host_hs_hsic60m_p%d_clk", i + 1);
0734         omap->hsic60m_clk[i] = devm_clk_get(dev, clkname);
0735         if (IS_ERR(omap->hsic60m_clk[i])) {
0736             ret = PTR_ERR(omap->hsic60m_clk[i]);
0737             dev_err(dev, "Failed to get clock : %s : %d\n",
0738                 clkname, ret);
0739             goto err_mem;
0740         }
0741     }
0742 
0743     if (is_ehci_phy_mode(pdata->port_mode[0])) {
0744         ret = clk_set_parent(omap->utmi_p1_gfclk,
0745                     omap->xclk60mhsp1_ck);
0746         if (ret != 0) {
0747             dev_err(dev, "xclk60mhsp1_ck set parent failed: %d\n",
0748                 ret);
0749             goto err_mem;
0750         }
0751     } else if (is_ehci_tll_mode(pdata->port_mode[0])) {
0752         ret = clk_set_parent(omap->utmi_p1_gfclk,
0753                     omap->init_60m_fclk);
0754         if (ret != 0) {
0755             dev_err(dev, "P0 init_60m_fclk set parent failed: %d\n",
0756                 ret);
0757             goto err_mem;
0758         }
0759     }
0760 
0761     if (is_ehci_phy_mode(pdata->port_mode[1])) {
0762         ret = clk_set_parent(omap->utmi_p2_gfclk,
0763                     omap->xclk60mhsp2_ck);
0764         if (ret != 0) {
0765             dev_err(dev, "xclk60mhsp2_ck set parent failed: %d\n",
0766                 ret);
0767             goto err_mem;
0768         }
0769     } else if (is_ehci_tll_mode(pdata->port_mode[1])) {
0770         ret = clk_set_parent(omap->utmi_p2_gfclk,
0771                         omap->init_60m_fclk);
0772         if (ret != 0) {
0773             dev_err(dev, "P1 init_60m_fclk set parent failed: %d\n",
0774                 ret);
0775             goto err_mem;
0776         }
0777     }
0778 
0779 initialize:
0780     omap_usbhs_init(dev);
0781 
0782     if (dev->of_node) {
0783         ret = of_platform_populate(dev->of_node,
0784                 usbhs_child_match_table, NULL, dev);
0785 
0786         if (ret) {
0787             dev_err(dev, "Failed to create DT children: %d\n", ret);
0788             goto err_mem;
0789         }
0790 
0791     } else {
0792         ret = omap_usbhs_alloc_children(pdev);
0793         if (ret) {
0794             dev_err(dev, "omap_usbhs_alloc_children failed: %d\n",
0795                         ret);
0796             goto err_mem;
0797         }
0798     }
0799 
0800     return 0;
0801 
0802 err_mem:
0803     pm_runtime_disable(dev);
0804 
0805     return ret;
0806 }
0807 
0808 static int usbhs_omap_remove_child(struct device *dev, void *data)
0809 {
0810     dev_info(dev, "unregistering\n");
0811     platform_device_unregister(to_platform_device(dev));
0812     return 0;
0813 }
0814 
0815 /**
0816  * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
0817  * @pdev: USB Host Controller being removed
0818  *
0819  * Reverses the effect of usbhs_omap_probe().
0820  */
0821 static int usbhs_omap_remove(struct platform_device *pdev)
0822 {
0823     pm_runtime_disable(&pdev->dev);
0824 
0825     /* remove children */
0826     device_for_each_child(&pdev->dev, NULL, usbhs_omap_remove_child);
0827     return 0;
0828 }
0829 
0830 static const struct dev_pm_ops usbhsomap_dev_pm_ops = {
0831     .runtime_suspend    = usbhs_runtime_suspend,
0832     .runtime_resume     = usbhs_runtime_resume,
0833 };
0834 
0835 static const struct of_device_id usbhs_omap_dt_ids[] = {
0836     { .compatible = "ti,usbhs-host" },
0837     { }
0838 };
0839 
0840 MODULE_DEVICE_TABLE(of, usbhs_omap_dt_ids);
0841 
0842 
0843 static struct platform_driver usbhs_omap_driver = {
0844     .driver = {
0845         .name       = usbhs_driver_name,
0846         .pm     = &usbhsomap_dev_pm_ops,
0847         .of_match_table = usbhs_omap_dt_ids,
0848     },
0849     .probe      = usbhs_omap_probe,
0850     .remove     = usbhs_omap_remove,
0851 };
0852 
0853 MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
0854 MODULE_AUTHOR("Roger Quadros <rogerq@ti.com>");
0855 MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
0856 MODULE_LICENSE("GPL v2");
0857 MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI");
0858 
0859 static int omap_usbhs_drvinit(void)
0860 {
0861     return platform_driver_register(&usbhs_omap_driver);
0862 }
0863 
0864 /*
0865  * init before ehci and ohci drivers;
0866  * The usbhs core driver should be initialized much before
0867  * the omap ehci and ohci probe functions are called.
0868  * This usbhs core driver should be initialized after
0869  * usb tll driver
0870  */
0871 fs_initcall_sync(omap_usbhs_drvinit);
0872 
0873 static void omap_usbhs_drvexit(void)
0874 {
0875     platform_driver_unregister(&usbhs_omap_driver);
0876 }
0877 module_exit(omap_usbhs_drvexit);
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