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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright 2009-2010 Pengutronix
0004  * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
0005  *
0006  * loosely based on an earlier driver that has
0007  * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
0008  */
0009 
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/of_device.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/mfd/core.h>
0015 
0016 #include "mc13xxx.h"
0017 
0018 #define MC13XXX_IRQSTAT0    0
0019 #define MC13XXX_IRQMASK0    1
0020 #define MC13XXX_IRQSTAT1    3
0021 #define MC13XXX_IRQMASK1    4
0022 
0023 #define MC13XXX_REVISION    7
0024 #define MC13XXX_REVISION_REVMETAL   (0x07 <<  0)
0025 #define MC13XXX_REVISION_REVFULL    (0x03 <<  3)
0026 #define MC13XXX_REVISION_ICID       (0x07 <<  6)
0027 #define MC13XXX_REVISION_FIN        (0x03 <<  9)
0028 #define MC13XXX_REVISION_FAB        (0x03 << 11)
0029 #define MC13XXX_REVISION_ICIDCODE   (0x3f << 13)
0030 
0031 #define MC34708_REVISION_REVMETAL   (0x07 <<  0)
0032 #define MC34708_REVISION_REVFULL    (0x07 <<  3)
0033 #define MC34708_REVISION_FIN        (0x07 <<  6)
0034 #define MC34708_REVISION_FAB        (0x07 <<  9)
0035 
0036 #define MC13XXX_PWRCTRL     15
0037 #define MC13XXX_PWRCTRL_WDIRESET    (1 << 12)
0038 
0039 #define MC13XXX_ADC1        44
0040 #define MC13XXX_ADC1_ADEN       (1 << 0)
0041 #define MC13XXX_ADC1_RAND       (1 << 1)
0042 #define MC13XXX_ADC1_ADSEL      (1 << 3)
0043 #define MC13XXX_ADC1_ASC        (1 << 20)
0044 #define MC13XXX_ADC1_ADTRIGIGN      (1 << 21)
0045 
0046 #define MC13XXX_ADC2        45
0047 
0048 void mc13xxx_lock(struct mc13xxx *mc13xxx)
0049 {
0050     if (!mutex_trylock(&mc13xxx->lock)) {
0051         dev_dbg(mc13xxx->dev, "wait for %s from %ps\n",
0052                 __func__, __builtin_return_address(0));
0053 
0054         mutex_lock(&mc13xxx->lock);
0055     }
0056     dev_dbg(mc13xxx->dev, "%s from %ps\n",
0057             __func__, __builtin_return_address(0));
0058 }
0059 EXPORT_SYMBOL(mc13xxx_lock);
0060 
0061 void mc13xxx_unlock(struct mc13xxx *mc13xxx)
0062 {
0063     dev_dbg(mc13xxx->dev, "%s from %ps\n",
0064             __func__, __builtin_return_address(0));
0065     mutex_unlock(&mc13xxx->lock);
0066 }
0067 EXPORT_SYMBOL(mc13xxx_unlock);
0068 
0069 int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
0070 {
0071     int ret;
0072 
0073     ret = regmap_read(mc13xxx->regmap, offset, val);
0074     dev_vdbg(mc13xxx->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
0075 
0076     return ret;
0077 }
0078 EXPORT_SYMBOL(mc13xxx_reg_read);
0079 
0080 int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
0081 {
0082     dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x\n", offset, val);
0083 
0084     if (val >= BIT(24))
0085         return -EINVAL;
0086 
0087     return regmap_write(mc13xxx->regmap, offset, val);
0088 }
0089 EXPORT_SYMBOL(mc13xxx_reg_write);
0090 
0091 int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
0092         u32 mask, u32 val)
0093 {
0094     BUG_ON(val & ~mask);
0095     dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x (mask: 0x%06x)\n",
0096             offset, val, mask);
0097 
0098     return regmap_update_bits(mc13xxx->regmap, offset, mask, val);
0099 }
0100 EXPORT_SYMBOL(mc13xxx_reg_rmw);
0101 
0102 int mc13xxx_irq_mask(struct mc13xxx *mc13xxx, int irq)
0103 {
0104     int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);
0105 
0106     disable_irq_nosync(virq);
0107 
0108     return 0;
0109 }
0110 EXPORT_SYMBOL(mc13xxx_irq_mask);
0111 
0112 int mc13xxx_irq_unmask(struct mc13xxx *mc13xxx, int irq)
0113 {
0114     int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);
0115 
0116     enable_irq(virq);
0117 
0118     return 0;
0119 }
0120 EXPORT_SYMBOL(mc13xxx_irq_unmask);
0121 
0122 int mc13xxx_irq_status(struct mc13xxx *mc13xxx, int irq,
0123         int *enabled, int *pending)
0124 {
0125     int ret;
0126     unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
0127     unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
0128     u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
0129 
0130     if (irq < 0 || irq >= ARRAY_SIZE(mc13xxx->irqs))
0131         return -EINVAL;
0132 
0133     if (enabled) {
0134         u32 mask;
0135 
0136         ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
0137         if (ret)
0138             return ret;
0139 
0140         *enabled = mask & irqbit;
0141     }
0142 
0143     if (pending) {
0144         u32 stat;
0145 
0146         ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
0147         if (ret)
0148             return ret;
0149 
0150         *pending = stat & irqbit;
0151     }
0152 
0153     return 0;
0154 }
0155 EXPORT_SYMBOL(mc13xxx_irq_status);
0156 
0157 int mc13xxx_irq_request(struct mc13xxx *mc13xxx, int irq,
0158         irq_handler_t handler, const char *name, void *dev)
0159 {
0160     int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);
0161 
0162     return devm_request_threaded_irq(mc13xxx->dev, virq, NULL, handler,
0163                      IRQF_ONESHOT, name, dev);
0164 }
0165 EXPORT_SYMBOL(mc13xxx_irq_request);
0166 
0167 int mc13xxx_irq_free(struct mc13xxx *mc13xxx, int irq, void *dev)
0168 {
0169     int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);
0170 
0171     devm_free_irq(mc13xxx->dev, virq, dev);
0172 
0173     return 0;
0174 }
0175 EXPORT_SYMBOL(mc13xxx_irq_free);
0176 
0177 #define maskval(reg, mask)  (((reg) & (mask)) >> __ffs(mask))
0178 static void mc13xxx_print_revision(struct mc13xxx *mc13xxx, u32 revision)
0179 {
0180     dev_info(mc13xxx->dev, "%s: rev: %d.%d, "
0181             "fin: %d, fab: %d, icid: %d/%d\n",
0182             mc13xxx->variant->name,
0183             maskval(revision, MC13XXX_REVISION_REVFULL),
0184             maskval(revision, MC13XXX_REVISION_REVMETAL),
0185             maskval(revision, MC13XXX_REVISION_FIN),
0186             maskval(revision, MC13XXX_REVISION_FAB),
0187             maskval(revision, MC13XXX_REVISION_ICID),
0188             maskval(revision, MC13XXX_REVISION_ICIDCODE));
0189 }
0190 
0191 static void mc34708_print_revision(struct mc13xxx *mc13xxx, u32 revision)
0192 {
0193     dev_info(mc13xxx->dev, "%s: rev %d.%d, fin: %d, fab: %d\n",
0194             mc13xxx->variant->name,
0195             maskval(revision, MC34708_REVISION_REVFULL),
0196             maskval(revision, MC34708_REVISION_REVMETAL),
0197             maskval(revision, MC34708_REVISION_FIN),
0198             maskval(revision, MC34708_REVISION_FAB));
0199 }
0200 
0201 /* These are only exported for mc13xxx-i2c and mc13xxx-spi */
0202 struct mc13xxx_variant mc13xxx_variant_mc13783 = {
0203     .name = "mc13783",
0204     .print_revision = mc13xxx_print_revision,
0205 };
0206 EXPORT_SYMBOL_GPL(mc13xxx_variant_mc13783);
0207 
0208 struct mc13xxx_variant mc13xxx_variant_mc13892 = {
0209     .name = "mc13892",
0210     .print_revision = mc13xxx_print_revision,
0211 };
0212 EXPORT_SYMBOL_GPL(mc13xxx_variant_mc13892);
0213 
0214 struct mc13xxx_variant mc13xxx_variant_mc34708 = {
0215     .name = "mc34708",
0216     .print_revision = mc34708_print_revision,
0217 };
0218 EXPORT_SYMBOL_GPL(mc13xxx_variant_mc34708);
0219 
0220 static const char *mc13xxx_get_chipname(struct mc13xxx *mc13xxx)
0221 {
0222     return mc13xxx->variant->name;
0223 }
0224 
0225 int mc13xxx_get_flags(struct mc13xxx *mc13xxx)
0226 {
0227     return mc13xxx->flags;
0228 }
0229 EXPORT_SYMBOL(mc13xxx_get_flags);
0230 
0231 #define MC13XXX_ADC1_CHAN0_SHIFT    5
0232 #define MC13XXX_ADC1_CHAN1_SHIFT    8
0233 #define MC13783_ADC1_ATO_SHIFT      11
0234 #define MC13783_ADC1_ATOX       (1 << 19)
0235 
0236 struct mc13xxx_adcdone_data {
0237     struct mc13xxx *mc13xxx;
0238     struct completion done;
0239 };
0240 
0241 static irqreturn_t mc13xxx_handler_adcdone(int irq, void *data)
0242 {
0243     struct mc13xxx_adcdone_data *adcdone_data = data;
0244 
0245     complete_all(&adcdone_data->done);
0246 
0247     return IRQ_HANDLED;
0248 }
0249 
0250 #define MC13XXX_ADC_WORKING (1 << 0)
0251 
0252 int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, unsigned int mode,
0253         unsigned int channel, u8 ato, bool atox,
0254         unsigned int *sample)
0255 {
0256     u32 adc0, adc1, old_adc0;
0257     int i, ret;
0258     struct mc13xxx_adcdone_data adcdone_data = {
0259         .mc13xxx = mc13xxx,
0260     };
0261     init_completion(&adcdone_data.done);
0262 
0263     dev_dbg(mc13xxx->dev, "%s\n", __func__);
0264 
0265     mc13xxx_lock(mc13xxx);
0266 
0267     if (mc13xxx->adcflags & MC13XXX_ADC_WORKING) {
0268         ret = -EBUSY;
0269         goto out;
0270     }
0271 
0272     mc13xxx->adcflags |= MC13XXX_ADC_WORKING;
0273 
0274     ret = mc13xxx_reg_read(mc13xxx, MC13XXX_ADC0, &old_adc0);
0275     if (ret)
0276         goto out;
0277 
0278     adc0 = MC13XXX_ADC0_ADINC1 | MC13XXX_ADC0_ADINC2 |
0279            MC13XXX_ADC0_CHRGRAWDIV;
0280     adc1 = MC13XXX_ADC1_ADEN | MC13XXX_ADC1_ADTRIGIGN | MC13XXX_ADC1_ASC;
0281 
0282     /*
0283      * Channels mapped through ADIN7:
0284      * 7  - General purpose ADIN7
0285      * 16 - UID
0286      * 17 - Die temperature
0287      */
0288     if (channel > 7 && channel < 16) {
0289         adc1 |= MC13XXX_ADC1_ADSEL;
0290     } else if (channel == 16) {
0291         adc0 |= MC13XXX_ADC0_ADIN7SEL_UID;
0292         channel = 7;
0293     } else if (channel == 17) {
0294         adc0 |= MC13XXX_ADC0_ADIN7SEL_DIE;
0295         channel = 7;
0296     }
0297 
0298     switch (mode) {
0299     case MC13XXX_ADC_MODE_TS:
0300         adc0 |= MC13XXX_ADC0_ADREFEN | MC13XXX_ADC0_TSMOD0 |
0301             MC13XXX_ADC0_TSMOD1;
0302         adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
0303         break;
0304 
0305     case MC13XXX_ADC_MODE_SINGLE_CHAN:
0306         adc0 |= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
0307         adc1 |= (channel & 0x7) << MC13XXX_ADC1_CHAN0_SHIFT;
0308         adc1 |= MC13XXX_ADC1_RAND;
0309         break;
0310 
0311     case MC13XXX_ADC_MODE_MULT_CHAN:
0312         adc0 |= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
0313         adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
0314         break;
0315 
0316     default:
0317         mc13xxx_unlock(mc13xxx);
0318         return -EINVAL;
0319     }
0320 
0321     adc1 |= ato << MC13783_ADC1_ATO_SHIFT;
0322     if (atox)
0323         adc1 |= MC13783_ADC1_ATOX;
0324 
0325     dev_dbg(mc13xxx->dev, "%s: request irq\n", __func__);
0326     ret = mc13xxx_irq_request(mc13xxx, MC13XXX_IRQ_ADCDONE,
0327             mc13xxx_handler_adcdone, __func__, &adcdone_data);
0328     if (ret)
0329         goto out;
0330 
0331     mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, adc0);
0332     mc13xxx_reg_write(mc13xxx, MC13XXX_ADC1, adc1);
0333 
0334     mc13xxx_unlock(mc13xxx);
0335 
0336     ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);
0337 
0338     if (!ret)
0339         ret = -ETIMEDOUT;
0340 
0341     mc13xxx_lock(mc13xxx);
0342 
0343     mc13xxx_irq_free(mc13xxx, MC13XXX_IRQ_ADCDONE, &adcdone_data);
0344 
0345     if (ret > 0)
0346         for (i = 0; i < 4; ++i) {
0347             ret = mc13xxx_reg_read(mc13xxx,
0348                     MC13XXX_ADC2, &sample[i]);
0349             if (ret)
0350                 break;
0351         }
0352 
0353     if (mode == MC13XXX_ADC_MODE_TS)
0354         /* restore TSMOD */
0355         mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, old_adc0);
0356 
0357     mc13xxx->adcflags &= ~MC13XXX_ADC_WORKING;
0358 out:
0359     mc13xxx_unlock(mc13xxx);
0360 
0361     return ret;
0362 }
0363 EXPORT_SYMBOL_GPL(mc13xxx_adc_do_conversion);
0364 
0365 static int mc13xxx_add_subdevice_pdata(struct mc13xxx *mc13xxx,
0366         const char *format, void *pdata, size_t pdata_size)
0367 {
0368     char buf[30];
0369     const char *name = mc13xxx_get_chipname(mc13xxx);
0370 
0371     struct mfd_cell cell = {
0372         .platform_data = pdata,
0373         .pdata_size = pdata_size,
0374     };
0375 
0376     /* there is no asnprintf in the kernel :-( */
0377     if (snprintf(buf, sizeof(buf), format, name) > sizeof(buf))
0378         return -E2BIG;
0379 
0380     cell.name = kmemdup(buf, strlen(buf) + 1, GFP_KERNEL);
0381     if (!cell.name)
0382         return -ENOMEM;
0383 
0384     return mfd_add_devices(mc13xxx->dev, -1, &cell, 1, NULL, 0,
0385                    regmap_irq_get_domain(mc13xxx->irq_data));
0386 }
0387 
0388 static int mc13xxx_add_subdevice(struct mc13xxx *mc13xxx, const char *format)
0389 {
0390     return mc13xxx_add_subdevice_pdata(mc13xxx, format, NULL, 0);
0391 }
0392 
0393 #ifdef CONFIG_OF
0394 static int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
0395 {
0396     struct device_node *np = mc13xxx->dev->of_node;
0397 
0398     if (!np)
0399         return -ENODEV;
0400 
0401     if (of_property_read_bool(np, "fsl,mc13xxx-uses-adc"))
0402         mc13xxx->flags |= MC13XXX_USE_ADC;
0403 
0404     if (of_property_read_bool(np, "fsl,mc13xxx-uses-codec"))
0405         mc13xxx->flags |= MC13XXX_USE_CODEC;
0406 
0407     if (of_property_read_bool(np, "fsl,mc13xxx-uses-rtc"))
0408         mc13xxx->flags |= MC13XXX_USE_RTC;
0409 
0410     if (of_property_read_bool(np, "fsl,mc13xxx-uses-touch"))
0411         mc13xxx->flags |= MC13XXX_USE_TOUCHSCREEN;
0412 
0413     return 0;
0414 }
0415 #else
0416 static inline int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
0417 {
0418     return -ENODEV;
0419 }
0420 #endif
0421 
0422 int mc13xxx_common_init(struct device *dev)
0423 {
0424     struct mc13xxx_platform_data *pdata = dev_get_platdata(dev);
0425     struct mc13xxx *mc13xxx = dev_get_drvdata(dev);
0426     u32 revision;
0427     int i, ret;
0428 
0429     mc13xxx->dev = dev;
0430 
0431     ret = mc13xxx_reg_read(mc13xxx, MC13XXX_REVISION, &revision);
0432     if (ret)
0433         return ret;
0434 
0435     mc13xxx->variant->print_revision(mc13xxx, revision);
0436 
0437     ret = mc13xxx_reg_rmw(mc13xxx, MC13XXX_PWRCTRL,
0438             MC13XXX_PWRCTRL_WDIRESET, MC13XXX_PWRCTRL_WDIRESET);
0439     if (ret)
0440         return ret;
0441 
0442     for (i = 0; i < ARRAY_SIZE(mc13xxx->irqs); i++) {
0443         mc13xxx->irqs[i].reg_offset = i / MC13XXX_IRQ_PER_REG;
0444         mc13xxx->irqs[i].mask = BIT(i % MC13XXX_IRQ_PER_REG);
0445     }
0446 
0447     mc13xxx->irq_chip.name = dev_name(dev);
0448     mc13xxx->irq_chip.status_base = MC13XXX_IRQSTAT0;
0449     mc13xxx->irq_chip.mask_base = MC13XXX_IRQMASK0;
0450     mc13xxx->irq_chip.ack_base = MC13XXX_IRQSTAT0;
0451     mc13xxx->irq_chip.irq_reg_stride = MC13XXX_IRQSTAT1 - MC13XXX_IRQSTAT0;
0452     mc13xxx->irq_chip.init_ack_masked = true;
0453     mc13xxx->irq_chip.use_ack = true;
0454     mc13xxx->irq_chip.num_regs = MC13XXX_IRQ_REG_CNT;
0455     mc13xxx->irq_chip.irqs = mc13xxx->irqs;
0456     mc13xxx->irq_chip.num_irqs = ARRAY_SIZE(mc13xxx->irqs);
0457 
0458     ret = regmap_add_irq_chip(mc13xxx->regmap, mc13xxx->irq, IRQF_ONESHOT,
0459                   0, &mc13xxx->irq_chip, &mc13xxx->irq_data);
0460     if (ret)
0461         return ret;
0462 
0463     mutex_init(&mc13xxx->lock);
0464 
0465     if (mc13xxx_probe_flags_dt(mc13xxx) < 0 && pdata)
0466         mc13xxx->flags = pdata->flags;
0467 
0468     if (pdata) {
0469         mc13xxx_add_subdevice_pdata(mc13xxx, "%s-regulator",
0470             &pdata->regulators, sizeof(pdata->regulators));
0471         mc13xxx_add_subdevice_pdata(mc13xxx, "%s-led",
0472                 pdata->leds, sizeof(*pdata->leds));
0473         mc13xxx_add_subdevice_pdata(mc13xxx, "%s-pwrbutton",
0474                 pdata->buttons, sizeof(*pdata->buttons));
0475         if (mc13xxx->flags & MC13XXX_USE_CODEC)
0476             mc13xxx_add_subdevice_pdata(mc13xxx, "%s-codec",
0477                 pdata->codec, sizeof(*pdata->codec));
0478         if (mc13xxx->flags & MC13XXX_USE_TOUCHSCREEN)
0479             mc13xxx_add_subdevice_pdata(mc13xxx, "%s-ts",
0480                 &pdata->touch, sizeof(pdata->touch));
0481     } else {
0482         mc13xxx_add_subdevice(mc13xxx, "%s-regulator");
0483         mc13xxx_add_subdevice(mc13xxx, "%s-led");
0484         mc13xxx_add_subdevice(mc13xxx, "%s-pwrbutton");
0485         if (mc13xxx->flags & MC13XXX_USE_CODEC)
0486             mc13xxx_add_subdevice(mc13xxx, "%s-codec");
0487         if (mc13xxx->flags & MC13XXX_USE_TOUCHSCREEN)
0488             mc13xxx_add_subdevice(mc13xxx, "%s-ts");
0489     }
0490 
0491     if (mc13xxx->flags & MC13XXX_USE_ADC)
0492         mc13xxx_add_subdevice(mc13xxx, "%s-adc");
0493 
0494     if (mc13xxx->flags & MC13XXX_USE_RTC)
0495         mc13xxx_add_subdevice(mc13xxx, "%s-rtc");
0496 
0497     return 0;
0498 }
0499 EXPORT_SYMBOL_GPL(mc13xxx_common_init);
0500 
0501 void mc13xxx_common_exit(struct device *dev)
0502 {
0503     struct mc13xxx *mc13xxx = dev_get_drvdata(dev);
0504 
0505     mfd_remove_devices(dev);
0506     regmap_del_irq_chip(mc13xxx->irq, mc13xxx->irq_data);
0507     mutex_destroy(&mc13xxx->lock);
0508 }
0509 EXPORT_SYMBOL_GPL(mc13xxx_common_exit);
0510 
0511 MODULE_DESCRIPTION("Core driver for Freescale MC13XXX PMIC");
0512 MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
0513 MODULE_LICENSE("GPL v2");
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