drivers/mfd/max8997-irq.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // max8997-irq.c - Interrupt controller support for MAX8997
0004 //
0005 // Copyright (C) 2011 Samsung Electronics Co.Ltd
0006 // MyungJoo Ham <myungjoo.ham@samsung.com>
0007 //
0008 // This driver is based on max8998-irq.c
0009
0010 #include <linux/err.h>
0011 #include <linux/irq.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/mfd/max8997.h>
0014 #include <linux/mfd/max8997-private.h>
0015
0016 static const u8 max8997_mask_reg[] = {
0017     [PMIC_INT1] = MAX8997_REG_INT1MSK,
0018     [PMIC_INT2] = MAX8997_REG_INT2MSK,
0019     [PMIC_INT3] = MAX8997_REG_INT3MSK,
0020     [PMIC_INT4] = MAX8997_REG_INT4MSK,
0021     [FUEL_GAUGE] = MAX8997_REG_INVALID,
0022     [MUIC_INT1] = MAX8997_MUIC_REG_INTMASK1,
0023     [MUIC_INT2] = MAX8997_MUIC_REG_INTMASK2,
0024     [MUIC_INT3] = MAX8997_MUIC_REG_INTMASK3,
0025     [GPIO_LOW] = MAX8997_REG_INVALID,
0026     [GPIO_HI] = MAX8997_REG_INVALID,
0027     [FLASH_STATUS] = MAX8997_REG_INVALID,
0028 };
0029
0030 static struct i2c_client *get_i2c(struct max8997_dev *max8997,
0031                 enum max8997_irq_source src)
0032 {
0033     switch (src) {
0034     case PMIC_INT1 ... PMIC_INT4:
0035         return max8997->i2c;
0036     case FUEL_GAUGE:
0037         return NULL;
0038     case MUIC_INT1 ... MUIC_INT3:
0039         return max8997->muic;
0040     case GPIO_LOW ... GPIO_HI:
0041         return max8997->i2c;
0042     case FLASH_STATUS:
0043         return max8997->i2c;
0044     default:
0045         return ERR_PTR(-EINVAL);
0046     }
0047 }
0048
0049 struct max8997_irq_data {
0050     int mask;
0051     enum max8997_irq_source group;
0052 };
0053
0054 #define DECLARE_IRQ(idx, _group, _mask)     \
0055     [(idx)] = { .group = (_group), .mask = (_mask) }
0056 static const struct max8997_irq_data max8997_irqs[] = {
0057     DECLARE_IRQ(MAX8997_PMICIRQ_PWRONR, PMIC_INT1, 1 << 0),
0058     DECLARE_IRQ(MAX8997_PMICIRQ_PWRONF, PMIC_INT1, 1 << 1),
0059     DECLARE_IRQ(MAX8997_PMICIRQ_PWRON1SEC,  PMIC_INT1, 1 << 3),
0060     DECLARE_IRQ(MAX8997_PMICIRQ_JIGONR, PMIC_INT1, 1 << 4),
0061     DECLARE_IRQ(MAX8997_PMICIRQ_JIGONF, PMIC_INT1, 1 << 5),
0062     DECLARE_IRQ(MAX8997_PMICIRQ_LOWBAT2,    PMIC_INT1, 1 << 6),
0063     DECLARE_IRQ(MAX8997_PMICIRQ_LOWBAT1,    PMIC_INT1, 1 << 7),
0064
0065     DECLARE_IRQ(MAX8997_PMICIRQ_JIGR,   PMIC_INT2, 1 << 0),
0066     DECLARE_IRQ(MAX8997_PMICIRQ_JIGF,   PMIC_INT2, 1 << 1),
0067     DECLARE_IRQ(MAX8997_PMICIRQ_MR,     PMIC_INT2, 1 << 2),
0068     DECLARE_IRQ(MAX8997_PMICIRQ_DVS1OK, PMIC_INT2, 1 << 3),
0069     DECLARE_IRQ(MAX8997_PMICIRQ_DVS2OK, PMIC_INT2, 1 << 4),
0070     DECLARE_IRQ(MAX8997_PMICIRQ_DVS3OK, PMIC_INT2, 1 << 5),
0071     DECLARE_IRQ(MAX8997_PMICIRQ_DVS4OK, PMIC_INT2, 1 << 6),
0072
0073     DECLARE_IRQ(MAX8997_PMICIRQ_CHGINS, PMIC_INT3, 1 << 0),
0074     DECLARE_IRQ(MAX8997_PMICIRQ_CHGRM,  PMIC_INT3, 1 << 1),
0075     DECLARE_IRQ(MAX8997_PMICIRQ_DCINOVP,    PMIC_INT3, 1 << 2),
0076     DECLARE_IRQ(MAX8997_PMICIRQ_TOPOFFR,    PMIC_INT3, 1 << 3),
0077     DECLARE_IRQ(MAX8997_PMICIRQ_CHGRSTF,    PMIC_INT3, 1 << 5),
0078     DECLARE_IRQ(MAX8997_PMICIRQ_MBCHGTMEXPD,    PMIC_INT3, 1 << 7),
0079
0080     DECLARE_IRQ(MAX8997_PMICIRQ_RTC60S, PMIC_INT4, 1 << 0),
0081     DECLARE_IRQ(MAX8997_PMICIRQ_RTCA1,  PMIC_INT4, 1 << 1),
0082     DECLARE_IRQ(MAX8997_PMICIRQ_RTCA2,  PMIC_INT4, 1 << 2),
0083     DECLARE_IRQ(MAX8997_PMICIRQ_SMPL_INT,   PMIC_INT4, 1 << 3),
0084     DECLARE_IRQ(MAX8997_PMICIRQ_RTC1S,  PMIC_INT4, 1 << 4),
0085     DECLARE_IRQ(MAX8997_PMICIRQ_WTSR,   PMIC_INT4, 1 << 5),
0086
0087     DECLARE_IRQ(MAX8997_MUICIRQ_ADCError,   MUIC_INT1, 1 << 2),
0088     DECLARE_IRQ(MAX8997_MUICIRQ_ADCLow, MUIC_INT1, 1 << 1),
0089     DECLARE_IRQ(MAX8997_MUICIRQ_ADC,    MUIC_INT1, 1 << 0),
0090
0091     DECLARE_IRQ(MAX8997_MUICIRQ_VBVolt, MUIC_INT2, 1 << 4),
0092     DECLARE_IRQ(MAX8997_MUICIRQ_DBChg,  MUIC_INT2, 1 << 3),
0093     DECLARE_IRQ(MAX8997_MUICIRQ_DCDTmr, MUIC_INT2, 1 << 2),
0094     DECLARE_IRQ(MAX8997_MUICIRQ_ChgDetRun,  MUIC_INT2, 1 << 1),
0095     DECLARE_IRQ(MAX8997_MUICIRQ_ChgTyp, MUIC_INT2, 1 << 0),
0096
0097     DECLARE_IRQ(MAX8997_MUICIRQ_OVP,    MUIC_INT3, 1 << 2),
0098 };
0099
0100 static void max8997_irq_lock(struct irq_data *data)
0101 {
0102     struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data);
0103
0104     mutex_lock(&max8997->irqlock);
0105 }
0106
0107 static void max8997_irq_sync_unlock(struct irq_data *data)
0108 {
0109     struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data);
0110     int i;
0111
0112     for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++) {
0113         u8 mask_reg = max8997_mask_reg[i];
0114         struct i2c_client *i2c = get_i2c(max8997, i);
0115
0116         if (mask_reg == MAX8997_REG_INVALID ||
0117                 IS_ERR_OR_NULL(i2c))
0118             continue;
0119         max8997->irq_masks_cache[i] = max8997->irq_masks_cur[i];
0120
0121         max8997_write_reg(i2c, max8997_mask_reg[i],
0122                 max8997->irq_masks_cur[i]);
0123     }
0124
0125     mutex_unlock(&max8997->irqlock);
0126 }
0127
0128 inline static const struct max8997_irq_data *
0129 irq_to_max8997_irq(struct max8997_dev *max8997, struct irq_data *data)
0130 {
0131     return &max8997_irqs[data->hwirq];
0132 }
0133
0134 static void max8997_irq_mask(struct irq_data *data)
0135 {
0136     struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data);
0137     const struct max8997_irq_data *irq_data = irq_to_max8997_irq(max8997,
0138                                      data);
0139
0140     max8997->irq_masks_cur[irq_data->group] |= irq_data->mask;
0141 }
0142
0143 static void max8997_irq_unmask(struct irq_data *data)
0144 {
0145     struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data);
0146     const struct max8997_irq_data *irq_data = irq_to_max8997_irq(max8997,
0147                                      data);
0148
0149     max8997->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
0150 }
0151
0152 static struct irq_chip max8997_irq_chip = {
0153     .name           = "max8997",
0154     .irq_bus_lock       = max8997_irq_lock,
0155     .irq_bus_sync_unlock    = max8997_irq_sync_unlock,
0156     .irq_mask       = max8997_irq_mask,
0157     .irq_unmask     = max8997_irq_unmask,
0158 };
0159
0160 #define MAX8997_IRQSRC_PMIC     (1 << 1)
0161 #define MAX8997_IRQSRC_FUELGAUGE    (1 << 2)
0162 #define MAX8997_IRQSRC_MUIC     (1 << 3)
0163 #define MAX8997_IRQSRC_GPIO     (1 << 4)
0164 #define MAX8997_IRQSRC_FLASH        (1 << 5)
0165 static irqreturn_t max8997_irq_thread(int irq, void *data)
0166 {
0167     struct max8997_dev *max8997 = data;
0168     u8 irq_reg[MAX8997_IRQ_GROUP_NR] = {};
0169     u8 irq_src;
0170     int ret;
0171     int i, cur_irq;
0172
0173     ret = max8997_read_reg(max8997->i2c, MAX8997_REG_INTSRC, &irq_src);
0174     if (ret < 0) {
0175         dev_err(max8997->dev, "Failed to read interrupt source: %d\n",
0176                 ret);
0177         return IRQ_NONE;
0178     }
0179
0180     if (irq_src & MAX8997_IRQSRC_PMIC) {
0181         /* PMIC INT1 ~ INT4 */
0182         max8997_bulk_read(max8997->i2c, MAX8997_REG_INT1, 4,
0183                 &irq_reg[PMIC_INT1]);
0184     }
0185     if (irq_src & MAX8997_IRQSRC_FUELGAUGE) {
0186         /*
0187          * TODO: FUEL GAUGE
0188          *
0189          * This is to be supported by Max17042 driver. When
0190          * an interrupt incurs here, it should be relayed to a
0191          * Max17042 device that is connected (probably by
0192          * platform-data). However, we do not have interrupt
0193          * handling in Max17042 driver currently. The Max17042 IRQ
0194          * driver should be ready to be used as a stand-alone device and
0195          * a Max8997-dependent device. Because it is not ready in
0196          * Max17042-side and it is not too critical in operating
0197          * Max8997, we do not implement this in initial releases.
0198          */
0199         irq_reg[FUEL_GAUGE] = 0;
0200     }
0201     if (irq_src & MAX8997_IRQSRC_MUIC) {
0202         /* MUIC INT1 ~ INT3 */
0203         max8997_bulk_read(max8997->muic, MAX8997_MUIC_REG_INT1, 3,
0204                 &irq_reg[MUIC_INT1]);
0205     }
0206     if (irq_src & MAX8997_IRQSRC_GPIO) {
0207         /* GPIO Interrupt */
0208         u8 gpio_info[MAX8997_NUM_GPIO];
0209
0210         irq_reg[GPIO_LOW] = 0;
0211         irq_reg[GPIO_HI] = 0;
0212
0213         max8997_bulk_read(max8997->i2c, MAX8997_REG_GPIOCNTL1,
0214                 MAX8997_NUM_GPIO, gpio_info);
0215         for (i = 0; i < MAX8997_NUM_GPIO; i++) {
0216             bool interrupt = false;
0217
0218             switch (gpio_info[i] & MAX8997_GPIO_INT_MASK) {
0219             case MAX8997_GPIO_INT_BOTH:
0220                 if (max8997->gpio_status[i] != gpio_info[i])
0221                     interrupt = true;
0222                 break;
0223             case MAX8997_GPIO_INT_RISE:
0224                 if ((max8997->gpio_status[i] != gpio_info[i]) &&
0225                     (gpio_info[i] & MAX8997_GPIO_DATA_MASK))
0226                     interrupt = true;
0227                 break;
0228             case MAX8997_GPIO_INT_FALL:
0229                 if ((max8997->gpio_status[i] != gpio_info[i]) &&
0230                     !(gpio_info[i] & MAX8997_GPIO_DATA_MASK))
0231                     interrupt = true;
0232                 break;
0233             default:
0234                 break;
0235             }
0236
0237             if (interrupt) {
0238                 if (i < 8)
0239                     irq_reg[GPIO_LOW] |= (1 << i);
0240                 else
0241                     irq_reg[GPIO_HI] |= (1 << (i - 8));
0242             }
0243
0244         }
0245     }
0246     if (irq_src & MAX8997_IRQSRC_FLASH) {
0247         /* Flash Status Interrupt */
0248         ret = max8997_read_reg(max8997->i2c, MAX8997_REG_FLASHSTATUS,
0249                 &irq_reg[FLASH_STATUS]);
0250     }
0251
0252     /* Apply masking */
0253     for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++)
0254         irq_reg[i] &= ~max8997->irq_masks_cur[i];
0255
0256     /* Report */
0257     for (i = 0; i < MAX8997_IRQ_NR; i++) {
0258         if (irq_reg[max8997_irqs[i].group] & max8997_irqs[i].mask) {
0259             cur_irq = irq_find_mapping(max8997->irq_domain, i);
0260             if (cur_irq)
0261                 handle_nested_irq(cur_irq);
0262         }
0263     }
0264
0265     return IRQ_HANDLED;
0266 }
0267
0268 int max8997_irq_resume(struct max8997_dev *max8997)
0269 {
0270     if (max8997->irq && max8997->irq_domain)
0271         max8997_irq_thread(0, max8997);
0272     return 0;
0273 }
0274
0275 static int max8997_irq_domain_map(struct irq_domain *d, unsigned int irq,
0276                     irq_hw_number_t hw)
0277 {
0278     struct max8997_dev *max8997 = d->host_data;
0279
0280     irq_set_chip_data(irq, max8997);
0281     irq_set_chip_and_handler(irq, &max8997_irq_chip, handle_edge_irq);
0282     irq_set_nested_thread(irq, 1);
0283     irq_set_noprobe(irq);
0284
0285     return 0;
0286 }
0287
0288 static const struct irq_domain_ops max8997_irq_domain_ops = {
0289     .map = max8997_irq_domain_map,
0290 };
0291
0292 int max8997_irq_init(struct max8997_dev *max8997)
0293 {
0294     struct irq_domain *domain;
0295     int i;
0296     int ret;
0297     u8 val;
0298
0299     if (!max8997->irq) {
0300         dev_warn(max8997->dev, "No interrupt specified.\n");
0301         return 0;
0302     }
0303
0304     mutex_init(&max8997->irqlock);
0305
0306     /* Mask individual interrupt sources */
0307     for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++) {
0308         struct i2c_client *i2c;
0309
0310         max8997->irq_masks_cur[i] = 0xff;
0311         max8997->irq_masks_cache[i] = 0xff;
0312         i2c = get_i2c(max8997, i);
0313
0314         if (IS_ERR_OR_NULL(i2c))
0315             continue;
0316         if (max8997_mask_reg[i] == MAX8997_REG_INVALID)
0317             continue;
0318
0319         max8997_write_reg(i2c, max8997_mask_reg[i], 0xff);
0320     }
0321
0322     for (i = 0; i < MAX8997_NUM_GPIO; i++) {
0323         max8997->gpio_status[i] = (max8997_read_reg(max8997->i2c,
0324                         MAX8997_REG_GPIOCNTL1 + i,
0325                         &val)
0326                     & MAX8997_GPIO_DATA_MASK) ?
0327                     true : false;
0328     }
0329
0330     domain = irq_domain_add_linear(NULL, MAX8997_IRQ_NR,
0331                     &max8997_irq_domain_ops, max8997);
0332     if (!domain) {
0333         dev_err(max8997->dev, "could not create irq domain\n");
0334         return -ENODEV;
0335     }
0336     max8997->irq_domain = domain;
0337
0338     ret = request_threaded_irq(max8997->irq, NULL, max8997_irq_thread,
0339             IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
0340             "max8997-irq", max8997);
0341
0342     if (ret) {
0343         dev_err(max8997->dev, "Failed to request IRQ %d: %d\n",
0344                 max8997->irq, ret);
0345         return ret;
0346     }
0347
0348     if (!max8997->ono)
0349         return 0;
0350
0351     ret = request_threaded_irq(max8997->ono, NULL, max8997_irq_thread,
0352             IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
0353             IRQF_ONESHOT, "max8997-ono", max8997);
0354
0355     if (ret)
0356         dev_err(max8997->dev, "Failed to request ono-IRQ %d: %d\n",
0357                 max8997->ono, ret);
0358
0359     return 0;
0360 }
0361
0362 void max8997_irq_exit(struct max8997_dev *max8997)
0363 {
0364     if (max8997->ono)
0365         free_irq(max8997->ono, max8997);
0366
0367     if (max8997->irq)
0368         free_irq(max8997->irq, max8997);
0369 }