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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  lpc_ich.c - LPC interface for Intel ICH
0004  *
0005  *  LPC bridge function of the Intel ICH contains many other
0006  *  functional units, such as Interrupt controllers, Timers,
0007  *  Power Management, System Management, GPIO, RTC, and LPC
0008  *  Configuration Registers.
0009  *
0010  *  This driver is derived from lpc_sch.
0011  *
0012  *  Copyright (c) 2017, 2021-2022 Intel Corporation
0013  *  Copyright (c) 2011 Extreme Engineering Solution, Inc.
0014  *  Author: Aaron Sierra <asierra@xes-inc.com>
0015  *
0016  *  This driver supports the following I/O Controller hubs:
0017  *  (See the intel documentation on http://developer.intel.com.)
0018  *  document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
0019  *  document number 290687-002, 298242-027: 82801BA (ICH2)
0020  *  document number 290733-003, 290739-013: 82801CA (ICH3-S)
0021  *  document number 290716-001, 290718-007: 82801CAM (ICH3-M)
0022  *  document number 290744-001, 290745-025: 82801DB (ICH4)
0023  *  document number 252337-001, 252663-008: 82801DBM (ICH4-M)
0024  *  document number 273599-001, 273645-002: 82801E (C-ICH)
0025  *  document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
0026  *  document number 300641-004, 300884-013: 6300ESB
0027  *  document number 301473-002, 301474-026: 82801F (ICH6)
0028  *  document number 313082-001, 313075-006: 631xESB, 632xESB
0029  *  document number 307013-003, 307014-024: 82801G (ICH7)
0030  *  document number 322896-001, 322897-001: NM10
0031  *  document number 313056-003, 313057-017: 82801H (ICH8)
0032  *  document number 316972-004, 316973-012: 82801I (ICH9)
0033  *  document number 319973-002, 319974-002: 82801J (ICH10)
0034  *  document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
0035  *  document number 320066-003, 320257-008: EP80597 (IICH)
0036  *  document number 324645-001, 324646-001: Cougar Point (CPT)
0037  */
0038 
0039 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0040 
0041 #include <linux/kernel.h>
0042 #include <linux/module.h>
0043 #include <linux/errno.h>
0044 #include <linux/acpi.h>
0045 #include <linux/pci.h>
0046 #include <linux/pinctrl/pinctrl.h>
0047 #include <linux/mfd/core.h>
0048 #include <linux/mfd/lpc_ich.h>
0049 #include <linux/platform_data/itco_wdt.h>
0050 #include <linux/platform_data/x86/p2sb.h>
0051 
0052 #define ACPIBASE        0x40
0053 #define ACPIBASE_GPE_OFF    0x28
0054 #define ACPIBASE_GPE_END    0x2f
0055 #define ACPIBASE_SMI_OFF    0x30
0056 #define ACPIBASE_SMI_END    0x33
0057 #define ACPIBASE_PMC_OFF    0x08
0058 #define ACPIBASE_PMC_END    0x0c
0059 #define ACPIBASE_TCO_OFF    0x60
0060 #define ACPIBASE_TCO_END    0x7f
0061 #define ACPICTRL_PMCBASE    0x44
0062 
0063 #define ACPIBASE_GCS_OFF    0x3410
0064 #define ACPIBASE_GCS_END    0x3414
0065 
0066 #define SPIBASE_BYT     0x54
0067 #define SPIBASE_BYT_SZ      512
0068 #define SPIBASE_BYT_EN      BIT(1)
0069 #define BYT_BCR         0xfc
0070 #define BYT_BCR_WPD     BIT(0)
0071 
0072 #define SPIBASE_LPT     0x3800
0073 #define SPIBASE_LPT_SZ      512
0074 #define BCR         0xdc
0075 #define BCR_WPD         BIT(0)
0076 
0077 #define GPIOBASE_ICH0       0x58
0078 #define GPIOCTRL_ICH0       0x5C
0079 #define GPIOBASE_ICH6       0x48
0080 #define GPIOCTRL_ICH6       0x4C
0081 
0082 #define RCBABASE        0xf0
0083 
0084 #define wdt_io_res(i) wdt_res(0, i)
0085 #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i)
0086 #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)])
0087 
0088 struct lpc_ich_priv {
0089     int chipset;
0090 
0091     int abase;      /* ACPI base */
0092     int actrl_pbase;    /* ACPI control or PMC base */
0093     int gbase;      /* GPIO base */
0094     int gctrl;      /* GPIO control */
0095 
0096     int abase_save;     /* Cached ACPI base value */
0097     int actrl_pbase_save;       /* Cached ACPI control or PMC base value */
0098     int gctrl_save;     /* Cached GPIO control value */
0099 };
0100 
0101 static struct resource wdt_ich_res[] = {
0102     /* ACPI - TCO */
0103     {
0104         .flags = IORESOURCE_IO,
0105     },
0106     /* ACPI - SMI */
0107     {
0108         .flags = IORESOURCE_IO,
0109     },
0110     /* GCS or PMC */
0111     {
0112         .flags = IORESOURCE_MEM,
0113     },
0114 };
0115 
0116 static struct resource gpio_ich_res[] = {
0117     /* GPIO */
0118     {
0119         .flags = IORESOURCE_IO,
0120     },
0121     /* ACPI - GPE0 */
0122     {
0123         .flags = IORESOURCE_IO,
0124     },
0125 };
0126 
0127 static struct resource intel_spi_res[] = {
0128     {
0129         .flags = IORESOURCE_MEM,
0130     }
0131 };
0132 
0133 static struct mfd_cell lpc_ich_wdt_cell = {
0134     .name = "iTCO_wdt",
0135     .num_resources = ARRAY_SIZE(wdt_ich_res),
0136     .resources = wdt_ich_res,
0137     .ignore_resource_conflicts = true,
0138 };
0139 
0140 static struct mfd_cell lpc_ich_gpio_cell = {
0141     .name = "gpio_ich",
0142     .num_resources = ARRAY_SIZE(gpio_ich_res),
0143     .resources = gpio_ich_res,
0144     .ignore_resource_conflicts = true,
0145 };
0146 
0147 #define APL_GPIO_NORTH      0
0148 #define APL_GPIO_NORTHWEST  1
0149 #define APL_GPIO_WEST       2
0150 #define APL_GPIO_SOUTHWEST  3
0151 #define APL_GPIO_NR_DEVICES 4
0152 
0153 /* Offset data for Apollo Lake GPIO controllers */
0154 static resource_size_t apl_gpio_offsets[APL_GPIO_NR_DEVICES] = {
0155     [APL_GPIO_NORTH]    = 0xc50000,
0156     [APL_GPIO_NORTHWEST]    = 0xc40000,
0157     [APL_GPIO_WEST]     = 0xc70000,
0158     [APL_GPIO_SOUTHWEST]    = 0xc00000,
0159 };
0160 
0161 #define APL_GPIO_RESOURCE_SIZE      0x1000
0162 
0163 #define APL_GPIO_IRQ            14
0164 
0165 static struct resource apl_gpio_resources[APL_GPIO_NR_DEVICES][2] = {
0166     [APL_GPIO_NORTH] = {
0167         DEFINE_RES_MEM(0, 0),
0168         DEFINE_RES_IRQ(APL_GPIO_IRQ),
0169     },
0170     [APL_GPIO_NORTHWEST] = {
0171         DEFINE_RES_MEM(0, 0),
0172         DEFINE_RES_IRQ(APL_GPIO_IRQ),
0173     },
0174     [APL_GPIO_WEST] = {
0175         DEFINE_RES_MEM(0, 0),
0176         DEFINE_RES_IRQ(APL_GPIO_IRQ),
0177     },
0178     [APL_GPIO_SOUTHWEST] = {
0179         DEFINE_RES_MEM(0, 0),
0180         DEFINE_RES_IRQ(APL_GPIO_IRQ),
0181     },
0182 };
0183 
0184 static const struct mfd_cell apl_gpio_devices[APL_GPIO_NR_DEVICES] = {
0185     [APL_GPIO_NORTH] = {
0186         .name = "apollolake-pinctrl",
0187         .id = APL_GPIO_NORTH,
0188         .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_NORTH]),
0189         .resources = apl_gpio_resources[APL_GPIO_NORTH],
0190         .ignore_resource_conflicts = true,
0191     },
0192     [APL_GPIO_NORTHWEST] = {
0193         .name = "apollolake-pinctrl",
0194         .id = APL_GPIO_NORTHWEST,
0195         .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_NORTHWEST]),
0196         .resources = apl_gpio_resources[APL_GPIO_NORTHWEST],
0197         .ignore_resource_conflicts = true,
0198     },
0199     [APL_GPIO_WEST] = {
0200         .name = "apollolake-pinctrl",
0201         .id = APL_GPIO_WEST,
0202         .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_WEST]),
0203         .resources = apl_gpio_resources[APL_GPIO_WEST],
0204         .ignore_resource_conflicts = true,
0205     },
0206     [APL_GPIO_SOUTHWEST] = {
0207         .name = "apollolake-pinctrl",
0208         .id = APL_GPIO_SOUTHWEST,
0209         .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_SOUTHWEST]),
0210         .resources = apl_gpio_resources[APL_GPIO_SOUTHWEST],
0211         .ignore_resource_conflicts = true,
0212     },
0213 };
0214 
0215 static struct mfd_cell lpc_ich_spi_cell = {
0216     .name = "intel-spi",
0217     .num_resources = ARRAY_SIZE(intel_spi_res),
0218     .resources = intel_spi_res,
0219     .ignore_resource_conflicts = true,
0220 };
0221 
0222 /* chipset related info */
0223 enum lpc_chipsets {
0224     LPC_ICH = 0,    /* ICH */
0225     LPC_ICH0,   /* ICH0 */
0226     LPC_ICH2,   /* ICH2 */
0227     LPC_ICH2M,  /* ICH2-M */
0228     LPC_ICH3,   /* ICH3-S */
0229     LPC_ICH3M,  /* ICH3-M */
0230     LPC_ICH4,   /* ICH4 */
0231     LPC_ICH4M,  /* ICH4-M */
0232     LPC_CICH,   /* C-ICH */
0233     LPC_ICH5,   /* ICH5 & ICH5R */
0234     LPC_6300ESB,    /* 6300ESB */
0235     LPC_ICH6,   /* ICH6 & ICH6R */
0236     LPC_ICH6M,  /* ICH6-M */
0237     LPC_ICH6W,  /* ICH6W & ICH6RW */
0238     LPC_631XESB,    /* 631xESB/632xESB */
0239     LPC_ICH7,   /* ICH7 & ICH7R */
0240     LPC_ICH7DH, /* ICH7DH */
0241     LPC_ICH7M,  /* ICH7-M & ICH7-U */
0242     LPC_ICH7MDH,    /* ICH7-M DH */
0243     LPC_NM10,   /* NM10 */
0244     LPC_ICH8,   /* ICH8 & ICH8R */
0245     LPC_ICH8DH, /* ICH8DH */
0246     LPC_ICH8DO, /* ICH8DO */
0247     LPC_ICH8M,  /* ICH8M */
0248     LPC_ICH8ME, /* ICH8M-E */
0249     LPC_ICH9,   /* ICH9 */
0250     LPC_ICH9R,  /* ICH9R */
0251     LPC_ICH9DH, /* ICH9DH */
0252     LPC_ICH9DO, /* ICH9DO */
0253     LPC_ICH9M,  /* ICH9M */
0254     LPC_ICH9ME, /* ICH9M-E */
0255     LPC_ICH10,  /* ICH10 */
0256     LPC_ICH10R, /* ICH10R */
0257     LPC_ICH10D, /* ICH10D */
0258     LPC_ICH10DO,    /* ICH10DO */
0259     LPC_PCH,    /* PCH Desktop Full Featured */
0260     LPC_PCHM,   /* PCH Mobile Full Featured */
0261     LPC_P55,    /* P55 */
0262     LPC_PM55,   /* PM55 */
0263     LPC_H55,    /* H55 */
0264     LPC_QM57,   /* QM57 */
0265     LPC_H57,    /* H57 */
0266     LPC_HM55,   /* HM55 */
0267     LPC_Q57,    /* Q57 */
0268     LPC_HM57,   /* HM57 */
0269     LPC_PCHMSFF,    /* PCH Mobile SFF Full Featured */
0270     LPC_QS57,   /* QS57 */
0271     LPC_3400,   /* 3400 */
0272     LPC_3420,   /* 3420 */
0273     LPC_3450,   /* 3450 */
0274     LPC_EP80579,    /* EP80579 */
0275     LPC_CPT,    /* Cougar Point */
0276     LPC_CPTD,   /* Cougar Point Desktop */
0277     LPC_CPTM,   /* Cougar Point Mobile */
0278     LPC_PBG,    /* Patsburg */
0279     LPC_DH89XXCC,   /* DH89xxCC */
0280     LPC_PPT,    /* Panther Point */
0281     LPC_LPT,    /* Lynx Point */
0282     LPC_LPT_LP, /* Lynx Point-LP */
0283     LPC_WBG,    /* Wellsburg */
0284     LPC_AVN,    /* Avoton SoC */
0285     LPC_BAYTRAIL,   /* Bay Trail SoC */
0286     LPC_COLETO, /* Coleto Creek */
0287     LPC_WPT_LP, /* Wildcat Point-LP */
0288     LPC_BRASWELL,   /* Braswell SoC */
0289     LPC_LEWISBURG,  /* Lewisburg */
0290     LPC_9S,     /* 9 Series */
0291     LPC_APL,    /* Apollo Lake SoC */
0292     LPC_GLK,    /* Gemini Lake SoC */
0293     LPC_COUGARMOUNTAIN,/* Cougar Mountain SoC*/
0294 };
0295 
0296 static struct lpc_ich_info lpc_chipset_info[] = {
0297     [LPC_ICH] = {
0298         .name = "ICH",
0299         .iTCO_version = 1,
0300     },
0301     [LPC_ICH0] = {
0302         .name = "ICH0",
0303         .iTCO_version = 1,
0304     },
0305     [LPC_ICH2] = {
0306         .name = "ICH2",
0307         .iTCO_version = 1,
0308     },
0309     [LPC_ICH2M] = {
0310         .name = "ICH2-M",
0311         .iTCO_version = 1,
0312     },
0313     [LPC_ICH3] = {
0314         .name = "ICH3-S",
0315         .iTCO_version = 1,
0316     },
0317     [LPC_ICH3M] = {
0318         .name = "ICH3-M",
0319         .iTCO_version = 1,
0320     },
0321     [LPC_ICH4] = {
0322         .name = "ICH4",
0323         .iTCO_version = 1,
0324     },
0325     [LPC_ICH4M] = {
0326         .name = "ICH4-M",
0327         .iTCO_version = 1,
0328     },
0329     [LPC_CICH] = {
0330         .name = "C-ICH",
0331         .iTCO_version = 1,
0332     },
0333     [LPC_ICH5] = {
0334         .name = "ICH5 or ICH5R",
0335         .iTCO_version = 1,
0336     },
0337     [LPC_6300ESB] = {
0338         .name = "6300ESB",
0339         .iTCO_version = 1,
0340     },
0341     [LPC_ICH6] = {
0342         .name = "ICH6 or ICH6R",
0343         .iTCO_version = 2,
0344         .gpio_version = ICH_V6_GPIO,
0345     },
0346     [LPC_ICH6M] = {
0347         .name = "ICH6-M",
0348         .iTCO_version = 2,
0349         .gpio_version = ICH_V6_GPIO,
0350     },
0351     [LPC_ICH6W] = {
0352         .name = "ICH6W or ICH6RW",
0353         .iTCO_version = 2,
0354         .gpio_version = ICH_V6_GPIO,
0355     },
0356     [LPC_631XESB] = {
0357         .name = "631xESB/632xESB",
0358         .iTCO_version = 2,
0359         .gpio_version = ICH_V6_GPIO,
0360     },
0361     [LPC_ICH7] = {
0362         .name = "ICH7 or ICH7R",
0363         .iTCO_version = 2,
0364         .gpio_version = ICH_V7_GPIO,
0365     },
0366     [LPC_ICH7DH] = {
0367         .name = "ICH7DH",
0368         .iTCO_version = 2,
0369         .gpio_version = ICH_V7_GPIO,
0370     },
0371     [LPC_ICH7M] = {
0372         .name = "ICH7-M or ICH7-U",
0373         .iTCO_version = 2,
0374         .gpio_version = ICH_V7_GPIO,
0375     },
0376     [LPC_ICH7MDH] = {
0377         .name = "ICH7-M DH",
0378         .iTCO_version = 2,
0379         .gpio_version = ICH_V7_GPIO,
0380     },
0381     [LPC_NM10] = {
0382         .name = "NM10",
0383         .iTCO_version = 2,
0384         .gpio_version = ICH_V7_GPIO,
0385     },
0386     [LPC_ICH8] = {
0387         .name = "ICH8 or ICH8R",
0388         .iTCO_version = 2,
0389         .gpio_version = ICH_V7_GPIO,
0390     },
0391     [LPC_ICH8DH] = {
0392         .name = "ICH8DH",
0393         .iTCO_version = 2,
0394         .gpio_version = ICH_V7_GPIO,
0395     },
0396     [LPC_ICH8DO] = {
0397         .name = "ICH8DO",
0398         .iTCO_version = 2,
0399         .gpio_version = ICH_V7_GPIO,
0400     },
0401     [LPC_ICH8M] = {
0402         .name = "ICH8M",
0403         .iTCO_version = 2,
0404         .gpio_version = ICH_V7_GPIO,
0405     },
0406     [LPC_ICH8ME] = {
0407         .name = "ICH8M-E",
0408         .iTCO_version = 2,
0409         .gpio_version = ICH_V7_GPIO,
0410     },
0411     [LPC_ICH9] = {
0412         .name = "ICH9",
0413         .iTCO_version = 2,
0414         .gpio_version = ICH_V9_GPIO,
0415     },
0416     [LPC_ICH9R] = {
0417         .name = "ICH9R",
0418         .iTCO_version = 2,
0419         .gpio_version = ICH_V9_GPIO,
0420     },
0421     [LPC_ICH9DH] = {
0422         .name = "ICH9DH",
0423         .iTCO_version = 2,
0424         .gpio_version = ICH_V9_GPIO,
0425     },
0426     [LPC_ICH9DO] = {
0427         .name = "ICH9DO",
0428         .iTCO_version = 2,
0429         .gpio_version = ICH_V9_GPIO,
0430     },
0431     [LPC_ICH9M] = {
0432         .name = "ICH9M",
0433         .iTCO_version = 2,
0434         .gpio_version = ICH_V9_GPIO,
0435     },
0436     [LPC_ICH9ME] = {
0437         .name = "ICH9M-E",
0438         .iTCO_version = 2,
0439         .gpio_version = ICH_V9_GPIO,
0440     },
0441     [LPC_ICH10] = {
0442         .name = "ICH10",
0443         .iTCO_version = 2,
0444         .gpio_version = ICH_V10CONS_GPIO,
0445     },
0446     [LPC_ICH10R] = {
0447         .name = "ICH10R",
0448         .iTCO_version = 2,
0449         .gpio_version = ICH_V10CONS_GPIO,
0450     },
0451     [LPC_ICH10D] = {
0452         .name = "ICH10D",
0453         .iTCO_version = 2,
0454         .gpio_version = ICH_V10CORP_GPIO,
0455     },
0456     [LPC_ICH10DO] = {
0457         .name = "ICH10DO",
0458         .iTCO_version = 2,
0459         .gpio_version = ICH_V10CORP_GPIO,
0460     },
0461     [LPC_PCH] = {
0462         .name = "PCH Desktop Full Featured",
0463         .iTCO_version = 2,
0464         .gpio_version = ICH_V5_GPIO,
0465     },
0466     [LPC_PCHM] = {
0467         .name = "PCH Mobile Full Featured",
0468         .iTCO_version = 2,
0469         .gpio_version = ICH_V5_GPIO,
0470     },
0471     [LPC_P55] = {
0472         .name = "P55",
0473         .iTCO_version = 2,
0474         .gpio_version = ICH_V5_GPIO,
0475     },
0476     [LPC_PM55] = {
0477         .name = "PM55",
0478         .iTCO_version = 2,
0479         .gpio_version = ICH_V5_GPIO,
0480     },
0481     [LPC_H55] = {
0482         .name = "H55",
0483         .iTCO_version = 2,
0484         .gpio_version = ICH_V5_GPIO,
0485     },
0486     [LPC_QM57] = {
0487         .name = "QM57",
0488         .iTCO_version = 2,
0489         .gpio_version = ICH_V5_GPIO,
0490     },
0491     [LPC_H57] = {
0492         .name = "H57",
0493         .iTCO_version = 2,
0494         .gpio_version = ICH_V5_GPIO,
0495     },
0496     [LPC_HM55] = {
0497         .name = "HM55",
0498         .iTCO_version = 2,
0499         .gpio_version = ICH_V5_GPIO,
0500     },
0501     [LPC_Q57] = {
0502         .name = "Q57",
0503         .iTCO_version = 2,
0504         .gpio_version = ICH_V5_GPIO,
0505     },
0506     [LPC_HM57] = {
0507         .name = "HM57",
0508         .iTCO_version = 2,
0509         .gpio_version = ICH_V5_GPIO,
0510     },
0511     [LPC_PCHMSFF] = {
0512         .name = "PCH Mobile SFF Full Featured",
0513         .iTCO_version = 2,
0514         .gpio_version = ICH_V5_GPIO,
0515     },
0516     [LPC_QS57] = {
0517         .name = "QS57",
0518         .iTCO_version = 2,
0519         .gpio_version = ICH_V5_GPIO,
0520     },
0521     [LPC_3400] = {
0522         .name = "3400",
0523         .iTCO_version = 2,
0524         .gpio_version = ICH_V5_GPIO,
0525     },
0526     [LPC_3420] = {
0527         .name = "3420",
0528         .iTCO_version = 2,
0529         .gpio_version = ICH_V5_GPIO,
0530     },
0531     [LPC_3450] = {
0532         .name = "3450",
0533         .iTCO_version = 2,
0534         .gpio_version = ICH_V5_GPIO,
0535     },
0536     [LPC_EP80579] = {
0537         .name = "EP80579",
0538         .iTCO_version = 2,
0539     },
0540     [LPC_CPT] = {
0541         .name = "Cougar Point",
0542         .iTCO_version = 2,
0543         .gpio_version = ICH_V5_GPIO,
0544     },
0545     [LPC_CPTD] = {
0546         .name = "Cougar Point Desktop",
0547         .iTCO_version = 2,
0548         .gpio_version = ICH_V5_GPIO,
0549     },
0550     [LPC_CPTM] = {
0551         .name = "Cougar Point Mobile",
0552         .iTCO_version = 2,
0553         .gpio_version = ICH_V5_GPIO,
0554     },
0555     [LPC_PBG] = {
0556         .name = "Patsburg",
0557         .iTCO_version = 2,
0558     },
0559     [LPC_DH89XXCC] = {
0560         .name = "DH89xxCC",
0561         .iTCO_version = 2,
0562         .gpio_version = ICH_V5_GPIO,
0563     },
0564     [LPC_PPT] = {
0565         .name = "Panther Point",
0566         .iTCO_version = 2,
0567         .gpio_version = ICH_V5_GPIO,
0568     },
0569     [LPC_LPT] = {
0570         .name = "Lynx Point",
0571         .iTCO_version = 2,
0572         .gpio_version = ICH_V5_GPIO,
0573         .spi_type = INTEL_SPI_LPT,
0574     },
0575     [LPC_LPT_LP] = {
0576         .name = "Lynx Point_LP",
0577         .iTCO_version = 2,
0578         .spi_type = INTEL_SPI_LPT,
0579     },
0580     [LPC_WBG] = {
0581         .name = "Wellsburg",
0582         .iTCO_version = 2,
0583     },
0584     [LPC_AVN] = {
0585         .name = "Avoton SoC",
0586         .iTCO_version = 3,
0587         .gpio_version = AVOTON_GPIO,
0588         .spi_type = INTEL_SPI_BYT,
0589     },
0590     [LPC_BAYTRAIL] = {
0591         .name = "Bay Trail SoC",
0592         .iTCO_version = 3,
0593         .spi_type = INTEL_SPI_BYT,
0594     },
0595     [LPC_COLETO] = {
0596         .name = "Coleto Creek",
0597         .iTCO_version = 2,
0598     },
0599     [LPC_WPT_LP] = {
0600         .name = "Wildcat Point_LP",
0601         .iTCO_version = 2,
0602         .spi_type = INTEL_SPI_LPT,
0603     },
0604     [LPC_BRASWELL] = {
0605         .name = "Braswell SoC",
0606         .iTCO_version = 3,
0607         .spi_type = INTEL_SPI_BYT,
0608     },
0609     [LPC_LEWISBURG] = {
0610         .name = "Lewisburg",
0611         .iTCO_version = 2,
0612     },
0613     [LPC_9S] = {
0614         .name = "9 Series",
0615         .iTCO_version = 2,
0616         .gpio_version = ICH_V5_GPIO,
0617     },
0618     [LPC_APL] = {
0619         .name = "Apollo Lake SoC",
0620         .iTCO_version = 5,
0621         .spi_type = INTEL_SPI_BXT,
0622     },
0623     [LPC_GLK] = {
0624         .name = "Gemini Lake SoC",
0625         .spi_type = INTEL_SPI_BXT,
0626     },
0627     [LPC_COUGARMOUNTAIN] = {
0628         .name = "Cougar Mountain SoC",
0629         .iTCO_version = 3,
0630     },
0631 };
0632 
0633 /*
0634  * This data only exists for exporting the supported PCI ids
0635  * via MODULE_DEVICE_TABLE.  We do not actually register a
0636  * pci_driver, because the I/O Controller Hub has also other
0637  * functions that probably will be registered by other drivers.
0638  */
0639 static const struct pci_device_id lpc_ich_ids[] = {
0640     { PCI_VDEVICE(INTEL, 0x0f1c), LPC_BAYTRAIL},
0641     { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT},
0642     { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD},
0643     { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM},
0644     { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT},
0645     { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT},
0646     { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT},
0647     { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT},
0648     { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT},
0649     { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT},
0650     { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT},
0651     { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT},
0652     { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT},
0653     { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT},
0654     { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT},
0655     { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT},
0656     { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT},
0657     { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT},
0658     { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT},
0659     { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT},
0660     { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT},
0661     { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT},
0662     { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT},
0663     { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT},
0664     { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT},
0665     { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT},
0666     { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT},
0667     { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT},
0668     { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT},
0669     { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT},
0670     { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT},
0671     { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT},
0672     { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG},
0673     { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG},
0674     { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT},
0675     { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT},
0676     { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT},
0677     { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT},
0678     { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT},
0679     { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT},
0680     { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT},
0681     { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT},
0682     { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT},
0683     { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT},
0684     { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT},
0685     { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT},
0686     { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT},
0687     { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT},
0688     { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT},
0689     { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT},
0690     { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT},
0691     { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT},
0692     { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT},
0693     { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT},
0694     { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT},
0695     { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT},
0696     { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT},
0697     { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT},
0698     { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT},
0699     { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT},
0700     { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT},
0701     { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT},
0702     { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT},
0703     { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT},
0704     { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT},
0705     { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT},
0706     { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN},
0707     { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN},
0708     { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN},
0709     { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN},
0710     { PCI_VDEVICE(INTEL, 0x229c), LPC_BRASWELL},
0711     { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC},
0712     { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO},
0713     { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH},
0714     { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0},
0715     { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2},
0716     { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M},
0717     { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH},
0718     { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3},
0719     { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M},
0720     { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4},
0721     { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M},
0722     { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5},
0723     { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB},
0724     { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6},
0725     { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M},
0726     { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W},
0727     { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB},
0728     { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB},
0729     { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB},
0730     { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB},
0731     { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB},
0732     { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB},
0733     { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB},
0734     { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB},
0735     { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB},
0736     { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB},
0737     { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB},
0738     { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB},
0739     { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB},
0740     { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB},
0741     { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB},
0742     { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB},
0743     { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH},
0744     { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7},
0745     { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M},
0746     { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10},
0747     { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH},
0748     { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8},
0749     { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME},
0750     { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH},
0751     { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO},
0752     { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M},
0753     { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH},
0754     { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO},
0755     { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R},
0756     { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME},
0757     { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9},
0758     { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M},
0759     { PCI_VDEVICE(INTEL, 0x3197), LPC_GLK},
0760     { PCI_VDEVICE(INTEL, 0x2b9c), LPC_COUGARMOUNTAIN},
0761     { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO},
0762     { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R},
0763     { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10},
0764     { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D},
0765     { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH},
0766     { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM},
0767     { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55},
0768     { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55},
0769     { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55},
0770     { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57},
0771     { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57},
0772     { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55},
0773     { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57},
0774     { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57},
0775     { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF},
0776     { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57},
0777     { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400},
0778     { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
0779     { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
0780     { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
0781     { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},
0782     { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
0783     { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
0784     { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
0785     { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT},
0786     { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT},
0787     { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT},
0788     { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT},
0789     { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT},
0790     { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT},
0791     { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT},
0792     { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT},
0793     { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT},
0794     { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT},
0795     { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT},
0796     { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT},
0797     { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT},
0798     { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT},
0799     { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT},
0800     { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT},
0801     { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT},
0802     { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT},
0803     { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT},
0804     { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT},
0805     { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT},
0806     { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT},
0807     { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT},
0808     { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT},
0809     { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT},
0810     { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT},
0811     { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT},
0812     { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT},
0813     { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT},
0814     { PCI_VDEVICE(INTEL, 0x8cc1), LPC_9S},
0815     { PCI_VDEVICE(INTEL, 0x8cc2), LPC_9S},
0816     { PCI_VDEVICE(INTEL, 0x8cc3), LPC_9S},
0817     { PCI_VDEVICE(INTEL, 0x8cc4), LPC_9S},
0818     { PCI_VDEVICE(INTEL, 0x8cc6), LPC_9S},
0819     { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG},
0820     { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG},
0821     { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG},
0822     { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG},
0823     { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG},
0824     { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG},
0825     { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG},
0826     { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG},
0827     { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG},
0828     { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG},
0829     { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG},
0830     { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG},
0831     { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG},
0832     { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG},
0833     { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG},
0834     { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG},
0835     { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG},
0836     { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG},
0837     { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG},
0838     { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG},
0839     { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG},
0840     { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG},
0841     { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG},
0842     { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG},
0843     { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG},
0844     { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG},
0845     { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG},
0846     { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG},
0847     { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG},
0848     { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG},
0849     { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG},
0850     { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG},
0851     { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP},
0852     { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP},
0853     { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP},
0854     { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP},
0855     { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP},
0856     { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP},
0857     { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP},
0858     { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP},
0859     { PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP},
0860     { PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP},
0861     { PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP},
0862     { PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP},
0863     { PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP},
0864     { PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP},
0865     { PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP},
0866     { PCI_VDEVICE(INTEL, 0xa1c1), LPC_LEWISBURG},
0867     { PCI_VDEVICE(INTEL, 0xa1c2), LPC_LEWISBURG},
0868     { PCI_VDEVICE(INTEL, 0xa1c3), LPC_LEWISBURG},
0869     { PCI_VDEVICE(INTEL, 0xa1c4), LPC_LEWISBURG},
0870     { PCI_VDEVICE(INTEL, 0xa1c5), LPC_LEWISBURG},
0871     { PCI_VDEVICE(INTEL, 0xa1c6), LPC_LEWISBURG},
0872     { PCI_VDEVICE(INTEL, 0xa1c7), LPC_LEWISBURG},
0873     { PCI_VDEVICE(INTEL, 0xa242), LPC_LEWISBURG},
0874     { PCI_VDEVICE(INTEL, 0xa243), LPC_LEWISBURG},
0875     { 0, },         /* End of list */
0876 };
0877 MODULE_DEVICE_TABLE(pci, lpc_ich_ids);
0878 
0879 static void lpc_ich_restore_config_space(struct pci_dev *dev)
0880 {
0881     struct lpc_ich_priv *priv = pci_get_drvdata(dev);
0882 
0883     if (priv->abase_save >= 0) {
0884         pci_write_config_byte(dev, priv->abase, priv->abase_save);
0885         priv->abase_save = -1;
0886     }
0887 
0888     if (priv->actrl_pbase_save >= 0) {
0889         pci_write_config_byte(dev, priv->actrl_pbase,
0890             priv->actrl_pbase_save);
0891         priv->actrl_pbase_save = -1;
0892     }
0893 
0894     if (priv->gctrl_save >= 0) {
0895         pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save);
0896         priv->gctrl_save = -1;
0897     }
0898 }
0899 
0900 static void lpc_ich_enable_acpi_space(struct pci_dev *dev)
0901 {
0902     struct lpc_ich_priv *priv = pci_get_drvdata(dev);
0903     u8 reg_save;
0904 
0905     switch (lpc_chipset_info[priv->chipset].iTCO_version) {
0906     case 3:
0907         /*
0908          * Some chipsets (eg Avoton) enable the ACPI space in the
0909          * ACPI BASE register.
0910          */
0911         pci_read_config_byte(dev, priv->abase, &reg_save);
0912         pci_write_config_byte(dev, priv->abase, reg_save | 0x2);
0913         priv->abase_save = reg_save;
0914         break;
0915     default:
0916         /*
0917          * Most chipsets enable the ACPI space in the ACPI control
0918          * register.
0919          */
0920         pci_read_config_byte(dev, priv->actrl_pbase, &reg_save);
0921         pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80);
0922         priv->actrl_pbase_save = reg_save;
0923         break;
0924     }
0925 }
0926 
0927 static void lpc_ich_enable_gpio_space(struct pci_dev *dev)
0928 {
0929     struct lpc_ich_priv *priv = pci_get_drvdata(dev);
0930     u8 reg_save;
0931 
0932     pci_read_config_byte(dev, priv->gctrl, &reg_save);
0933     pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10);
0934     priv->gctrl_save = reg_save;
0935 }
0936 
0937 static void lpc_ich_enable_pmc_space(struct pci_dev *dev)
0938 {
0939     struct lpc_ich_priv *priv = pci_get_drvdata(dev);
0940     u8 reg_save;
0941 
0942     pci_read_config_byte(dev, priv->actrl_pbase, &reg_save);
0943     pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2);
0944 
0945     priv->actrl_pbase_save = reg_save;
0946 }
0947 
0948 static int lpc_ich_finalize_wdt_cell(struct pci_dev *dev)
0949 {
0950     struct itco_wdt_platform_data *pdata;
0951     struct lpc_ich_priv *priv = pci_get_drvdata(dev);
0952     struct lpc_ich_info *info;
0953     struct mfd_cell *cell = &lpc_ich_wdt_cell;
0954 
0955     pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
0956     if (!pdata)
0957         return -ENOMEM;
0958 
0959     info = &lpc_chipset_info[priv->chipset];
0960 
0961     pdata->version = info->iTCO_version;
0962     strlcpy(pdata->name, info->name, sizeof(pdata->name));
0963 
0964     cell->platform_data = pdata;
0965     cell->pdata_size = sizeof(*pdata);
0966     return 0;
0967 }
0968 
0969 static void lpc_ich_finalize_gpio_cell(struct pci_dev *dev)
0970 {
0971     struct lpc_ich_priv *priv = pci_get_drvdata(dev);
0972     struct mfd_cell *cell = &lpc_ich_gpio_cell;
0973 
0974     cell->platform_data = &lpc_chipset_info[priv->chipset];
0975     cell->pdata_size = sizeof(struct lpc_ich_info);
0976 }
0977 
0978 /*
0979  * We don't check for resource conflict globally. There are 2 or 3 independent
0980  * GPIO groups and it's enough to have access to one of these to instantiate
0981  * the device.
0982  */
0983 static int lpc_ich_check_conflict_gpio(struct resource *res)
0984 {
0985     int ret;
0986     u8 use_gpio = 0;
0987 
0988     if (resource_size(res) >= 0x50 &&
0989         !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3"))
0990         use_gpio |= 1 << 2;
0991 
0992     if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2"))
0993         use_gpio |= 1 << 1;
0994 
0995     ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1");
0996     if (!ret)
0997         use_gpio |= 1 << 0;
0998 
0999     return use_gpio ? use_gpio : ret;
1000 }
1001 
1002 static int lpc_ich_init_gpio(struct pci_dev *dev)
1003 {
1004     struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1005     u32 base_addr_cfg;
1006     u32 base_addr;
1007     int ret;
1008     bool acpi_conflict = false;
1009     struct resource *res;
1010 
1011     /* Setup power management base register */
1012     pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
1013     base_addr = base_addr_cfg & 0x0000ff80;
1014     if (!base_addr) {
1015         dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
1016         lpc_ich_gpio_cell.num_resources--;
1017         goto gpe0_done;
1018     }
1019 
1020     res = &gpio_ich_res[ICH_RES_GPE0];
1021     res->start = base_addr + ACPIBASE_GPE_OFF;
1022     res->end = base_addr + ACPIBASE_GPE_END;
1023     ret = acpi_check_resource_conflict(res);
1024     if (ret) {
1025         /*
1026          * This isn't fatal for the GPIO, but we have to make sure that
1027          * the platform_device subsystem doesn't see this resource
1028          * or it will register an invalid region.
1029          */
1030         lpc_ich_gpio_cell.num_resources--;
1031         acpi_conflict = true;
1032     } else {
1033         lpc_ich_enable_acpi_space(dev);
1034     }
1035 
1036 gpe0_done:
1037     /* Setup GPIO base register */
1038     pci_read_config_dword(dev, priv->gbase, &base_addr_cfg);
1039     base_addr = base_addr_cfg & 0x0000ff80;
1040     if (!base_addr) {
1041         dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n");
1042         ret = -ENODEV;
1043         goto gpio_done;
1044     }
1045 
1046     /* Older devices provide fewer GPIO and have a smaller resource size. */
1047     res = &gpio_ich_res[ICH_RES_GPIO];
1048     res->start = base_addr;
1049     switch (lpc_chipset_info[priv->chipset].gpio_version) {
1050     case ICH_V5_GPIO:
1051     case ICH_V10CORP_GPIO:
1052         res->end = res->start + 128 - 1;
1053         break;
1054     default:
1055         res->end = res->start + 64 - 1;
1056         break;
1057     }
1058 
1059     ret = lpc_ich_check_conflict_gpio(res);
1060     if (ret < 0) {
1061         /* this isn't necessarily fatal for the GPIO */
1062         acpi_conflict = true;
1063         goto gpio_done;
1064     }
1065     lpc_chipset_info[priv->chipset].use_gpio = ret;
1066     lpc_ich_enable_gpio_space(dev);
1067 
1068     lpc_ich_finalize_gpio_cell(dev);
1069     ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
1070                   &lpc_ich_gpio_cell, 1, NULL, 0, NULL);
1071 
1072 gpio_done:
1073     if (acpi_conflict)
1074         pr_warn("Resource conflict(s) found affecting %s\n",
1075                 lpc_ich_gpio_cell.name);
1076     return ret;
1077 }
1078 
1079 static int lpc_ich_init_wdt(struct pci_dev *dev)
1080 {
1081     struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1082     u32 base_addr_cfg;
1083     u32 base_addr;
1084     int ret;
1085     struct resource *res;
1086 
1087     /* If we have ACPI based watchdog use that instead */
1088     if (acpi_has_watchdog())
1089         return -ENODEV;
1090 
1091     /* Setup power management base register */
1092     pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
1093     base_addr = base_addr_cfg & 0x0000ff80;
1094     if (!base_addr) {
1095         dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
1096         ret = -ENODEV;
1097         goto wdt_done;
1098     }
1099 
1100     res = wdt_io_res(ICH_RES_IO_TCO);
1101     res->start = base_addr + ACPIBASE_TCO_OFF;
1102     res->end = base_addr + ACPIBASE_TCO_END;
1103 
1104     res = wdt_io_res(ICH_RES_IO_SMI);
1105     res->start = base_addr + ACPIBASE_SMI_OFF;
1106     res->end = base_addr + ACPIBASE_SMI_END;
1107 
1108     lpc_ich_enable_acpi_space(dev);
1109 
1110     /*
1111      * iTCO v2:
1112      * Get the Memory-Mapped GCS register. To get access to it
1113      * we have to read RCBA from PCI Config space 0xf0 and use
1114      * it as base. GCS = RCBA + ICH6_GCS(0x3410).
1115      *
1116      * iTCO v3:
1117      * Get the Power Management Configuration register.  To get access
1118      * to it we have to read the PMC BASE from config space and address
1119      * the register at offset 0x8.
1120      */
1121     if (lpc_chipset_info[priv->chipset].iTCO_version == 1) {
1122         /* Don't register iomem for TCO ver 1 */
1123         lpc_ich_wdt_cell.num_resources--;
1124     } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) {
1125         pci_read_config_dword(dev, RCBABASE, &base_addr_cfg);
1126         base_addr = base_addr_cfg & 0xffffc000;
1127         if (!(base_addr_cfg & 1)) {
1128             dev_notice(&dev->dev, "RCBA is disabled by "
1129                     "hardware/BIOS, device disabled\n");
1130             ret = -ENODEV;
1131             goto wdt_done;
1132         }
1133         res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
1134         res->start = base_addr + ACPIBASE_GCS_OFF;
1135         res->end = base_addr + ACPIBASE_GCS_END;
1136     } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) {
1137         lpc_ich_enable_pmc_space(dev);
1138         pci_read_config_dword(dev, ACPICTRL_PMCBASE, &base_addr_cfg);
1139         base_addr = base_addr_cfg & 0xfffffe00;
1140 
1141         res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
1142         res->start = base_addr + ACPIBASE_PMC_OFF;
1143         res->end = base_addr + ACPIBASE_PMC_END;
1144     }
1145 
1146     ret = lpc_ich_finalize_wdt_cell(dev);
1147     if (ret)
1148         goto wdt_done;
1149 
1150     ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
1151                   &lpc_ich_wdt_cell, 1, NULL, 0, NULL);
1152 
1153 wdt_done:
1154     return ret;
1155 }
1156 
1157 static int lpc_ich_init_pinctrl(struct pci_dev *dev)
1158 {
1159     struct resource base;
1160     unsigned int i;
1161     int ret;
1162 
1163     /* Check, if GPIO has been exported as an ACPI device */
1164     if (acpi_dev_present("INT3452", NULL, -1))
1165         return -EEXIST;
1166 
1167     ret = p2sb_bar(dev->bus, 0, &base);
1168     if (ret)
1169         return ret;
1170 
1171     for (i = 0; i < ARRAY_SIZE(apl_gpio_devices); i++) {
1172         struct resource *mem = &apl_gpio_resources[i][0];
1173         resource_size_t offset = apl_gpio_offsets[i];
1174 
1175         /* Fill MEM resource */
1176         mem->start = base.start + offset;
1177         mem->end = base.start + offset + APL_GPIO_RESOURCE_SIZE - 1;
1178         mem->flags = base.flags;
1179     }
1180 
1181     return mfd_add_devices(&dev->dev, 0, apl_gpio_devices,
1182                    ARRAY_SIZE(apl_gpio_devices), NULL, 0, NULL);
1183 }
1184 
1185 static bool lpc_ich_byt_set_writeable(void __iomem *base, void *data)
1186 {
1187     u32 val;
1188 
1189     val = readl(base + BYT_BCR);
1190     if (!(val & BYT_BCR_WPD)) {
1191         val |= BYT_BCR_WPD;
1192         writel(val, base + BYT_BCR);
1193         val = readl(base + BYT_BCR);
1194     }
1195 
1196     return val & BYT_BCR_WPD;
1197 }
1198 
1199 static bool lpc_ich_set_writeable(struct pci_bus *bus, unsigned int devfn)
1200 {
1201     u32 bcr;
1202 
1203     pci_bus_read_config_dword(bus, devfn, BCR, &bcr);
1204     if (!(bcr & BCR_WPD)) {
1205         bcr |= BCR_WPD;
1206         pci_bus_write_config_dword(bus, devfn, BCR, bcr);
1207         pci_bus_read_config_dword(bus, devfn, BCR, &bcr);
1208     }
1209 
1210     return bcr & BCR_WPD;
1211 }
1212 
1213 static bool lpc_ich_lpt_set_writeable(void __iomem *base, void *data)
1214 {
1215     struct pci_dev *pdev = data;
1216 
1217     return lpc_ich_set_writeable(pdev->bus, pdev->devfn);
1218 }
1219 
1220 static bool lpc_ich_bxt_set_writeable(void __iomem *base, void *data)
1221 {
1222     struct pci_dev *pdev = data;
1223 
1224     return lpc_ich_set_writeable(pdev->bus, PCI_DEVFN(13, 2));
1225 }
1226 
1227 static int lpc_ich_init_spi(struct pci_dev *dev)
1228 {
1229     struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1230     struct resource *res = &intel_spi_res[0];
1231     struct intel_spi_boardinfo *info;
1232     u32 spi_base, rcba;
1233     int ret;
1234 
1235     info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL);
1236     if (!info)
1237         return -ENOMEM;
1238 
1239     info->type = lpc_chipset_info[priv->chipset].spi_type;
1240 
1241     switch (info->type) {
1242     case INTEL_SPI_BYT:
1243         pci_read_config_dword(dev, SPIBASE_BYT, &spi_base);
1244         if (spi_base & SPIBASE_BYT_EN) {
1245             res->start = spi_base & ~(SPIBASE_BYT_SZ - 1);
1246             res->end = res->start + SPIBASE_BYT_SZ - 1;
1247 
1248             info->set_writeable = lpc_ich_byt_set_writeable;
1249         }
1250         break;
1251 
1252     case INTEL_SPI_LPT:
1253         pci_read_config_dword(dev, RCBABASE, &rcba);
1254         if (rcba & 1) {
1255             spi_base = round_down(rcba, SPIBASE_LPT_SZ);
1256             res->start = spi_base + SPIBASE_LPT;
1257             res->end = res->start + SPIBASE_LPT_SZ - 1;
1258 
1259             info->set_writeable = lpc_ich_lpt_set_writeable;
1260             info->data = dev;
1261         }
1262         break;
1263 
1264     case INTEL_SPI_BXT:
1265         /*
1266          * The P2SB is hidden by BIOS and we need to unhide it in
1267          * order to read BAR of the SPI flash device. Once that is
1268          * done we hide it again.
1269          */
1270         ret = p2sb_bar(dev->bus, PCI_DEVFN(13, 2), res);
1271         if (ret)
1272             return ret;
1273 
1274         info->set_writeable = lpc_ich_bxt_set_writeable;
1275         info->data = dev;
1276         break;
1277 
1278     default:
1279         return -EINVAL;
1280     }
1281 
1282     if (!res->start)
1283         return -ENODEV;
1284 
1285     lpc_ich_spi_cell.platform_data = info;
1286     lpc_ich_spi_cell.pdata_size = sizeof(*info);
1287 
1288     return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE,
1289                    &lpc_ich_spi_cell, 1, NULL, 0, NULL);
1290 }
1291 
1292 static int lpc_ich_probe(struct pci_dev *dev,
1293                 const struct pci_device_id *id)
1294 {
1295     struct lpc_ich_priv *priv;
1296     int ret;
1297     bool cell_added = false;
1298 
1299     priv = devm_kzalloc(&dev->dev,
1300                 sizeof(struct lpc_ich_priv), GFP_KERNEL);
1301     if (!priv)
1302         return -ENOMEM;
1303 
1304     priv->chipset = id->driver_data;
1305 
1306     priv->actrl_pbase_save = -1;
1307     priv->abase_save = -1;
1308 
1309     priv->abase = ACPIBASE;
1310     priv->actrl_pbase = ACPICTRL_PMCBASE;
1311 
1312     priv->gctrl_save = -1;
1313     if (priv->chipset <= LPC_ICH5) {
1314         priv->gbase = GPIOBASE_ICH0;
1315         priv->gctrl = GPIOCTRL_ICH0;
1316     } else {
1317         priv->gbase = GPIOBASE_ICH6;
1318         priv->gctrl = GPIOCTRL_ICH6;
1319     }
1320 
1321     pci_set_drvdata(dev, priv);
1322 
1323     if (lpc_chipset_info[priv->chipset].iTCO_version) {
1324         ret = lpc_ich_init_wdt(dev);
1325         if (!ret)
1326             cell_added = true;
1327     }
1328 
1329     if (lpc_chipset_info[priv->chipset].gpio_version) {
1330         ret = lpc_ich_init_gpio(dev);
1331         if (!ret)
1332             cell_added = true;
1333     }
1334 
1335     if (priv->chipset == LPC_APL) {
1336         ret = lpc_ich_init_pinctrl(dev);
1337         if (!ret)
1338             cell_added = true;
1339     }
1340 
1341     if (lpc_chipset_info[priv->chipset].spi_type) {
1342         ret = lpc_ich_init_spi(dev);
1343         if (!ret)
1344             cell_added = true;
1345     }
1346 
1347     /*
1348      * We only care if at least one or none of the cells registered
1349      * successfully.
1350      */
1351     if (!cell_added) {
1352         dev_warn(&dev->dev, "No MFD cells added\n");
1353         lpc_ich_restore_config_space(dev);
1354         return -ENODEV;
1355     }
1356 
1357     return 0;
1358 }
1359 
1360 static void lpc_ich_remove(struct pci_dev *dev)
1361 {
1362     mfd_remove_devices(&dev->dev);
1363     lpc_ich_restore_config_space(dev);
1364 }
1365 
1366 static struct pci_driver lpc_ich_driver = {
1367     .name       = "lpc_ich",
1368     .id_table   = lpc_ich_ids,
1369     .probe      = lpc_ich_probe,
1370     .remove     = lpc_ich_remove,
1371 };
1372 
1373 module_pci_driver(lpc_ich_driver);
1374 
1375 MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>");
1376 MODULE_DESCRIPTION("LPC interface for Intel ICH");
1377 MODULE_LICENSE("GPL");
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