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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * SGI IOC3 multifunction device driver
0004  *
0005  * Copyright (C) 2018, 2019 Thomas Bogendoerfer <tbogendoerfer@suse.de>
0006  *
0007  * Based on work by:
0008  *   Stanislaw Skowronek <skylark@unaligned.org>
0009  *   Joshua Kinard <kumba@gentoo.org>
0010  *   Brent Casavant <bcasavan@sgi.com> - IOC4 master driver
0011  *   Pat Gefre <pfg@sgi.com> - IOC3 serial port IRQ demuxer
0012  */
0013 
0014 #include <linux/delay.h>
0015 #include <linux/errno.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/irqdomain.h>
0018 #include <linux/mfd/core.h>
0019 #include <linux/module.h>
0020 #include <linux/pci.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/platform_data/sgi-w1.h>
0023 #include <linux/rtc/ds1685.h>
0024 
0025 #include <asm/pci/bridge.h>
0026 #include <asm/sn/ioc3.h>
0027 
0028 #define IOC3_IRQ_SERIAL_A   6
0029 #define IOC3_IRQ_SERIAL_B   15
0030 #define IOC3_IRQ_KBD        22
0031 
0032 /* Bitmask for selecting which IRQs are level triggered */
0033 #define IOC3_LVL_MASK   (BIT(IOC3_IRQ_SERIAL_A) | BIT(IOC3_IRQ_SERIAL_B))
0034 
0035 #define M48T35_REG_SIZE 32768   /* size of m48t35 registers */
0036 
0037 /* 1.2 us latency timer (40 cycles at 33 MHz) */
0038 #define IOC3_LATENCY    40
0039 
0040 struct ioc3_priv_data {
0041     struct irq_domain *domain;
0042     struct ioc3 __iomem *regs;
0043     struct pci_dev *pdev;
0044     int domain_irq;
0045 };
0046 
0047 static void ioc3_irq_ack(struct irq_data *d)
0048 {
0049     struct ioc3_priv_data *ipd = irq_data_get_irq_chip_data(d);
0050     unsigned int hwirq = irqd_to_hwirq(d);
0051 
0052     writel(BIT(hwirq), &ipd->regs->sio_ir);
0053 }
0054 
0055 static void ioc3_irq_mask(struct irq_data *d)
0056 {
0057     struct ioc3_priv_data *ipd = irq_data_get_irq_chip_data(d);
0058     unsigned int hwirq = irqd_to_hwirq(d);
0059 
0060     writel(BIT(hwirq), &ipd->regs->sio_iec);
0061 }
0062 
0063 static void ioc3_irq_unmask(struct irq_data *d)
0064 {
0065     struct ioc3_priv_data *ipd = irq_data_get_irq_chip_data(d);
0066     unsigned int hwirq = irqd_to_hwirq(d);
0067 
0068     writel(BIT(hwirq), &ipd->regs->sio_ies);
0069 }
0070 
0071 static struct irq_chip ioc3_irq_chip = {
0072     .name       = "IOC3",
0073     .irq_ack    = ioc3_irq_ack,
0074     .irq_mask   = ioc3_irq_mask,
0075     .irq_unmask = ioc3_irq_unmask,
0076 };
0077 
0078 static int ioc3_irq_domain_map(struct irq_domain *d, unsigned int irq,
0079                   irq_hw_number_t hwirq)
0080 {
0081     /* Set level IRQs for every interrupt contained in IOC3_LVL_MASK */
0082     if (BIT(hwirq) & IOC3_LVL_MASK)
0083         irq_set_chip_and_handler(irq, &ioc3_irq_chip, handle_level_irq);
0084     else
0085         irq_set_chip_and_handler(irq, &ioc3_irq_chip, handle_edge_irq);
0086 
0087     irq_set_chip_data(irq, d->host_data);
0088     return 0;
0089 }
0090 
0091 static void ioc3_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
0092 {
0093     irq_set_chip_and_handler(irq, NULL, NULL);
0094     irq_set_chip_data(irq, NULL);
0095 }
0096 
0097 static const struct irq_domain_ops ioc3_irq_domain_ops = {
0098     .map = ioc3_irq_domain_map,
0099     .unmap = ioc3_irq_domain_unmap,
0100 };
0101 
0102 static void ioc3_irq_handler(struct irq_desc *desc)
0103 {
0104     struct irq_domain *domain = irq_desc_get_handler_data(desc);
0105     struct ioc3_priv_data *ipd = domain->host_data;
0106     struct ioc3 __iomem *regs = ipd->regs;
0107     u32 pending, mask;
0108 
0109     pending = readl(&regs->sio_ir);
0110     mask = readl(&regs->sio_ies);
0111     pending &= mask; /* Mask off not enabled interrupts */
0112 
0113     if (pending)
0114         generic_handle_domain_irq(domain, __ffs(pending));
0115     else
0116         spurious_interrupt();
0117 }
0118 
0119 /*
0120  * System boards/BaseIOs use more interrupt pins of the bridge ASIC
0121  * to which the IOC3 is connected. Since the IOC3 MFD driver
0122  * knows wiring of these extra pins, we use the map_irq function
0123  * to get interrupts activated
0124  */
0125 static int ioc3_map_irq(struct pci_dev *pdev, int slot, int pin)
0126 {
0127     struct pci_host_bridge *hbrg = pci_find_host_bridge(pdev->bus);
0128 
0129     return hbrg->map_irq(pdev, slot, pin);
0130 }
0131 
0132 static int ioc3_irq_domain_setup(struct ioc3_priv_data *ipd, int irq)
0133 {
0134     struct irq_domain *domain;
0135     struct fwnode_handle *fn;
0136 
0137     fn = irq_domain_alloc_named_fwnode("IOC3");
0138     if (!fn)
0139         goto err;
0140 
0141     domain = irq_domain_create_linear(fn, 24, &ioc3_irq_domain_ops, ipd);
0142     if (!domain) {
0143         irq_domain_free_fwnode(fn);
0144         goto err;
0145     }
0146 
0147     ipd->domain = domain;
0148 
0149     irq_set_chained_handler_and_data(irq, ioc3_irq_handler, domain);
0150     ipd->domain_irq = irq;
0151     return 0;
0152 
0153 err:
0154     dev_err(&ipd->pdev->dev, "irq domain setup failed\n");
0155     return -ENOMEM;
0156 }
0157 
0158 static const struct resource ioc3_uarta_resources[] = {
0159     DEFINE_RES_MEM(offsetof(struct ioc3, sregs.uarta),
0160                sizeof_field(struct ioc3, sregs.uarta)),
0161     DEFINE_RES_IRQ(IOC3_IRQ_SERIAL_A)
0162 };
0163 
0164 static const struct resource ioc3_uartb_resources[] = {
0165     DEFINE_RES_MEM(offsetof(struct ioc3, sregs.uartb),
0166                sizeof_field(struct ioc3, sregs.uartb)),
0167     DEFINE_RES_IRQ(IOC3_IRQ_SERIAL_B)
0168 };
0169 
0170 static struct mfd_cell ioc3_serial_cells[] = {
0171     {
0172         .name = "ioc3-serial8250",
0173         .resources = ioc3_uarta_resources,
0174         .num_resources = ARRAY_SIZE(ioc3_uarta_resources),
0175     },
0176     {
0177         .name = "ioc3-serial8250",
0178         .resources = ioc3_uartb_resources,
0179         .num_resources = ARRAY_SIZE(ioc3_uartb_resources),
0180     }
0181 };
0182 
0183 static int ioc3_serial_setup(struct ioc3_priv_data *ipd)
0184 {
0185     int ret;
0186 
0187     /* Set gpio pins for RS232/RS422 mode selection */
0188     writel(GPCR_UARTA_MODESEL | GPCR_UARTB_MODESEL,
0189         &ipd->regs->gpcr_s);
0190     /* Select RS232 mode for uart a */
0191     writel(0, &ipd->regs->gppr[6]);
0192     /* Select RS232 mode for uart b */
0193     writel(0, &ipd->regs->gppr[7]);
0194 
0195     /* Switch both ports to 16650 mode */
0196     writel(readl(&ipd->regs->port_a.sscr) & ~SSCR_DMA_EN,
0197            &ipd->regs->port_a.sscr);
0198     writel(readl(&ipd->regs->port_b.sscr) & ~SSCR_DMA_EN,
0199            &ipd->regs->port_b.sscr);
0200     udelay(1000); /* Wait until mode switch is done */
0201 
0202     ret = mfd_add_devices(&ipd->pdev->dev, PLATFORM_DEVID_AUTO,
0203                   ioc3_serial_cells, ARRAY_SIZE(ioc3_serial_cells),
0204                   &ipd->pdev->resource[0], 0, ipd->domain);
0205     if (ret) {
0206         dev_err(&ipd->pdev->dev, "Failed to add 16550 subdevs\n");
0207         return ret;
0208     }
0209 
0210     return 0;
0211 }
0212 
0213 static const struct resource ioc3_kbd_resources[] = {
0214     DEFINE_RES_MEM(offsetof(struct ioc3, serio),
0215                sizeof_field(struct ioc3, serio)),
0216     DEFINE_RES_IRQ(IOC3_IRQ_KBD)
0217 };
0218 
0219 static struct mfd_cell ioc3_kbd_cells[] = {
0220     {
0221         .name = "ioc3-kbd",
0222         .resources = ioc3_kbd_resources,
0223         .num_resources = ARRAY_SIZE(ioc3_kbd_resources),
0224     }
0225 };
0226 
0227 static int ioc3_kbd_setup(struct ioc3_priv_data *ipd)
0228 {
0229     int ret;
0230 
0231     ret = mfd_add_devices(&ipd->pdev->dev, PLATFORM_DEVID_AUTO,
0232                   ioc3_kbd_cells, ARRAY_SIZE(ioc3_kbd_cells),
0233                   &ipd->pdev->resource[0], 0, ipd->domain);
0234     if (ret) {
0235         dev_err(&ipd->pdev->dev, "Failed to add 16550 subdevs\n");
0236         return ret;
0237     }
0238 
0239     return 0;
0240 }
0241 
0242 static const struct resource ioc3_eth_resources[] = {
0243     DEFINE_RES_MEM(offsetof(struct ioc3, eth),
0244                sizeof_field(struct ioc3, eth)),
0245     DEFINE_RES_MEM(offsetof(struct ioc3, ssram),
0246                sizeof_field(struct ioc3, ssram)),
0247     DEFINE_RES_IRQ(0)
0248 };
0249 
0250 static const struct resource ioc3_w1_resources[] = {
0251     DEFINE_RES_MEM(offsetof(struct ioc3, mcr),
0252                sizeof_field(struct ioc3, mcr)),
0253 };
0254 static struct sgi_w1_platform_data ioc3_w1_platform_data;
0255 
0256 static struct mfd_cell ioc3_eth_cells[] = {
0257     {
0258         .name = "ioc3-eth",
0259         .resources = ioc3_eth_resources,
0260         .num_resources = ARRAY_SIZE(ioc3_eth_resources),
0261     },
0262     {
0263         .name = "sgi_w1",
0264         .resources = ioc3_w1_resources,
0265         .num_resources = ARRAY_SIZE(ioc3_w1_resources),
0266         .platform_data = &ioc3_w1_platform_data,
0267         .pdata_size = sizeof(ioc3_w1_platform_data),
0268     }
0269 };
0270 
0271 static int ioc3_eth_setup(struct ioc3_priv_data *ipd)
0272 {
0273     int ret;
0274 
0275     /* Enable One-Wire bus */
0276     writel(GPCR_MLAN_EN, &ipd->regs->gpcr_s);
0277 
0278     /* Generate unique identifier */
0279     snprintf(ioc3_w1_platform_data.dev_id,
0280          sizeof(ioc3_w1_platform_data.dev_id), "ioc3-%012llx",
0281          ipd->pdev->resource->start);
0282 
0283     ret = mfd_add_devices(&ipd->pdev->dev, PLATFORM_DEVID_AUTO,
0284                   ioc3_eth_cells, ARRAY_SIZE(ioc3_eth_cells),
0285                   &ipd->pdev->resource[0], ipd->pdev->irq, NULL);
0286     if (ret) {
0287         dev_err(&ipd->pdev->dev, "Failed to add ETH/W1 subdev\n");
0288         return ret;
0289     }
0290 
0291     return 0;
0292 }
0293 
0294 static const struct resource ioc3_m48t35_resources[] = {
0295     DEFINE_RES_MEM(IOC3_BYTEBUS_DEV0, M48T35_REG_SIZE)
0296 };
0297 
0298 static struct mfd_cell ioc3_m48t35_cells[] = {
0299     {
0300         .name = "rtc-m48t35",
0301         .resources = ioc3_m48t35_resources,
0302         .num_resources = ARRAY_SIZE(ioc3_m48t35_resources),
0303     }
0304 };
0305 
0306 static int ioc3_m48t35_setup(struct ioc3_priv_data *ipd)
0307 {
0308     int ret;
0309 
0310     ret = mfd_add_devices(&ipd->pdev->dev, PLATFORM_DEVID_AUTO,
0311                   ioc3_m48t35_cells, ARRAY_SIZE(ioc3_m48t35_cells),
0312                   &ipd->pdev->resource[0], 0, ipd->domain);
0313     if (ret)
0314         dev_err(&ipd->pdev->dev, "Failed to add M48T35 subdev\n");
0315 
0316     return ret;
0317 }
0318 
0319 static struct ds1685_rtc_platform_data ip30_rtc_platform_data = {
0320     .bcd_mode = false,
0321     .no_irq = false,
0322     .uie_unsupported = true,
0323     .access_type = ds1685_reg_indirect,
0324 };
0325 
0326 static const struct resource ioc3_rtc_ds1685_resources[] = {
0327     DEFINE_RES_MEM(IOC3_BYTEBUS_DEV1, 1),
0328     DEFINE_RES_MEM(IOC3_BYTEBUS_DEV2, 1),
0329     DEFINE_RES_IRQ(0)
0330 };
0331 
0332 static struct mfd_cell ioc3_ds1685_cells[] = {
0333     {
0334         .name = "rtc-ds1685",
0335         .resources = ioc3_rtc_ds1685_resources,
0336         .num_resources = ARRAY_SIZE(ioc3_rtc_ds1685_resources),
0337         .platform_data = &ip30_rtc_platform_data,
0338         .pdata_size = sizeof(ip30_rtc_platform_data),
0339         .id = PLATFORM_DEVID_NONE,
0340     }
0341 };
0342 
0343 static int ioc3_ds1685_setup(struct ioc3_priv_data *ipd)
0344 {
0345     int ret, irq;
0346 
0347     irq = ioc3_map_irq(ipd->pdev, 6, 0);
0348 
0349     ret = mfd_add_devices(&ipd->pdev->dev, 0, ioc3_ds1685_cells,
0350                   ARRAY_SIZE(ioc3_ds1685_cells),
0351                   &ipd->pdev->resource[0], irq, NULL);
0352     if (ret)
0353         dev_err(&ipd->pdev->dev, "Failed to add DS1685 subdev\n");
0354 
0355     return ret;
0356 };
0357 
0358 
0359 static const struct resource ioc3_leds_resources[] = {
0360     DEFINE_RES_MEM(offsetof(struct ioc3, gppr[0]),
0361                sizeof_field(struct ioc3, gppr[0])),
0362     DEFINE_RES_MEM(offsetof(struct ioc3, gppr[1]),
0363                sizeof_field(struct ioc3, gppr[1])),
0364 };
0365 
0366 static struct mfd_cell ioc3_led_cells[] = {
0367     {
0368         .name = "ip30-leds",
0369         .resources = ioc3_leds_resources,
0370         .num_resources = ARRAY_SIZE(ioc3_leds_resources),
0371         .id = PLATFORM_DEVID_NONE,
0372     }
0373 };
0374 
0375 static int ioc3_led_setup(struct ioc3_priv_data *ipd)
0376 {
0377     int ret;
0378 
0379     ret = mfd_add_devices(&ipd->pdev->dev, 0, ioc3_led_cells,
0380                   ARRAY_SIZE(ioc3_led_cells),
0381                   &ipd->pdev->resource[0], 0, ipd->domain);
0382     if (ret)
0383         dev_err(&ipd->pdev->dev, "Failed to add LED subdev\n");
0384 
0385     return ret;
0386 }
0387 
0388 static int ip27_baseio_setup(struct ioc3_priv_data *ipd)
0389 {
0390     int ret, io_irq;
0391 
0392     io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
0393                   PCI_INTERRUPT_INTB);
0394     ret = ioc3_irq_domain_setup(ipd, io_irq);
0395     if (ret)
0396         return ret;
0397 
0398     ret = ioc3_eth_setup(ipd);
0399     if (ret)
0400         return ret;
0401 
0402     ret = ioc3_serial_setup(ipd);
0403     if (ret)
0404         return ret;
0405 
0406     return ioc3_m48t35_setup(ipd);
0407 }
0408 
0409 static int ip27_baseio6g_setup(struct ioc3_priv_data *ipd)
0410 {
0411     int ret, io_irq;
0412 
0413     io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
0414                   PCI_INTERRUPT_INTB);
0415     ret = ioc3_irq_domain_setup(ipd, io_irq);
0416     if (ret)
0417         return ret;
0418 
0419     ret = ioc3_eth_setup(ipd);
0420     if (ret)
0421         return ret;
0422 
0423     ret = ioc3_serial_setup(ipd);
0424     if (ret)
0425         return ret;
0426 
0427     ret = ioc3_m48t35_setup(ipd);
0428     if (ret)
0429         return ret;
0430 
0431     return ioc3_kbd_setup(ipd);
0432 }
0433 
0434 static int ip27_mio_setup(struct ioc3_priv_data *ipd)
0435 {
0436     int ret;
0437 
0438     ret = ioc3_irq_domain_setup(ipd, ipd->pdev->irq);
0439     if (ret)
0440         return ret;
0441 
0442     ret = ioc3_serial_setup(ipd);
0443     if (ret)
0444         return ret;
0445 
0446     return ioc3_kbd_setup(ipd);
0447 }
0448 
0449 static int ip30_sysboard_setup(struct ioc3_priv_data *ipd)
0450 {
0451     int ret, io_irq;
0452 
0453     io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
0454                   PCI_INTERRUPT_INTB);
0455     ret = ioc3_irq_domain_setup(ipd, io_irq);
0456     if (ret)
0457         return ret;
0458 
0459     ret = ioc3_eth_setup(ipd);
0460     if (ret)
0461         return ret;
0462 
0463     ret = ioc3_serial_setup(ipd);
0464     if (ret)
0465         return ret;
0466 
0467     ret = ioc3_kbd_setup(ipd);
0468     if (ret)
0469         return ret;
0470 
0471     ret = ioc3_ds1685_setup(ipd);
0472     if (ret)
0473         return ret;
0474 
0475     return ioc3_led_setup(ipd);
0476 }
0477 
0478 static int ioc3_menet_setup(struct ioc3_priv_data *ipd)
0479 {
0480     int ret, io_irq;
0481 
0482     io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
0483                   PCI_INTERRUPT_INTB);
0484     ret = ioc3_irq_domain_setup(ipd, io_irq);
0485     if (ret)
0486         return ret;
0487 
0488     ret = ioc3_eth_setup(ipd);
0489     if (ret)
0490         return ret;
0491 
0492     return ioc3_serial_setup(ipd);
0493 }
0494 
0495 static int ioc3_menet4_setup(struct ioc3_priv_data *ipd)
0496 {
0497     return ioc3_eth_setup(ipd);
0498 }
0499 
0500 static int ioc3_cad_duo_setup(struct ioc3_priv_data *ipd)
0501 {
0502     int ret, io_irq;
0503 
0504     io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
0505                   PCI_INTERRUPT_INTB);
0506     ret = ioc3_irq_domain_setup(ipd, io_irq);
0507     if (ret)
0508         return ret;
0509 
0510     ret = ioc3_eth_setup(ipd);
0511     if (ret)
0512         return ret;
0513 
0514     return ioc3_kbd_setup(ipd);
0515 }
0516 
0517 /* Helper macro for filling ioc3_info array */
0518 #define IOC3_SID(_name, _sid, _setup) \
0519     {                                  \
0520         .name = _name,                         \
0521         .sid = PCI_VENDOR_ID_SGI | (IOC3_SUBSYS_ ## _sid << 16),   \
0522         .setup = _setup,                       \
0523     }
0524 
0525 static struct {
0526     const char *name;
0527     u32 sid;
0528     int (*setup)(struct ioc3_priv_data *ipd);
0529 } ioc3_infos[] = {
0530     IOC3_SID("IP27 BaseIO6G", IP27_BASEIO6G, &ip27_baseio6g_setup),
0531     IOC3_SID("IP27 MIO", IP27_MIO, &ip27_mio_setup),
0532     IOC3_SID("IP27 BaseIO", IP27_BASEIO, &ip27_baseio_setup),
0533     IOC3_SID("IP29 System Board", IP29_SYSBOARD, &ip27_baseio6g_setup),
0534     IOC3_SID("IP30 System Board", IP30_SYSBOARD, &ip30_sysboard_setup),
0535     IOC3_SID("MENET", MENET, &ioc3_menet_setup),
0536     IOC3_SID("MENET4", MENET4, &ioc3_menet4_setup)
0537 };
0538 #undef IOC3_SID
0539 
0540 static int ioc3_setup(struct ioc3_priv_data *ipd)
0541 {
0542     u32 sid;
0543     int i;
0544 
0545     /* Clear IRQs */
0546     writel(~0, &ipd->regs->sio_iec);
0547     writel(~0, &ipd->regs->sio_ir);
0548     writel(0, &ipd->regs->eth.eier);
0549     writel(~0, &ipd->regs->eth.eisr);
0550 
0551     /* Read subsystem vendor id and subsystem id */
0552     pci_read_config_dword(ipd->pdev, PCI_SUBSYSTEM_VENDOR_ID, &sid);
0553 
0554     for (i = 0; i < ARRAY_SIZE(ioc3_infos); i++)
0555         if (sid == ioc3_infos[i].sid) {
0556             pr_info("ioc3: %s\n", ioc3_infos[i].name);
0557             return ioc3_infos[i].setup(ipd);
0558         }
0559 
0560     /* Treat everything not identified by PCI subid as CAD DUO */
0561     pr_info("ioc3: CAD DUO\n");
0562     return ioc3_cad_duo_setup(ipd);
0563 }
0564 
0565 static int ioc3_mfd_probe(struct pci_dev *pdev,
0566               const struct pci_device_id *pci_id)
0567 {
0568     struct ioc3_priv_data *ipd;
0569     struct ioc3 __iomem *regs;
0570     int ret;
0571 
0572     ret = pci_enable_device(pdev);
0573     if (ret)
0574         return ret;
0575 
0576     pci_write_config_byte(pdev, PCI_LATENCY_TIMER, IOC3_LATENCY);
0577     pci_set_master(pdev);
0578 
0579     ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
0580     if (ret) {
0581         pr_err("%s: No usable DMA configuration, aborting.\n",
0582                pci_name(pdev));
0583         goto out_disable_device;
0584     }
0585 
0586     /* Set up per-IOC3 data */
0587     ipd = devm_kzalloc(&pdev->dev, sizeof(struct ioc3_priv_data),
0588                GFP_KERNEL);
0589     if (!ipd) {
0590         ret = -ENOMEM;
0591         goto out_disable_device;
0592     }
0593     ipd->pdev = pdev;
0594 
0595     /*
0596      * Map all IOC3 registers.  These are shared between subdevices
0597      * so the main IOC3 module manages them.
0598      */
0599     regs = pci_ioremap_bar(pdev, 0);
0600     if (!regs) {
0601         dev_warn(&pdev->dev, "ioc3: Unable to remap PCI BAR for %s.\n",
0602              pci_name(pdev));
0603         ret = -ENOMEM;
0604         goto out_disable_device;
0605     }
0606     ipd->regs = regs;
0607 
0608     /* Track PCI-device specific data */
0609     pci_set_drvdata(pdev, ipd);
0610 
0611     ret = ioc3_setup(ipd);
0612     if (ret) {
0613         /* Remove all already added MFD devices */
0614         mfd_remove_devices(&ipd->pdev->dev);
0615         if (ipd->domain) {
0616             struct fwnode_handle *fn = ipd->domain->fwnode;
0617 
0618             irq_domain_remove(ipd->domain);
0619             irq_domain_free_fwnode(fn);
0620             free_irq(ipd->domain_irq, (void *)ipd);
0621         }
0622         pci_iounmap(pdev, regs);
0623         goto out_disable_device;
0624     }
0625 
0626     return 0;
0627 
0628 out_disable_device:
0629     pci_disable_device(pdev);
0630     return ret;
0631 }
0632 
0633 static void ioc3_mfd_remove(struct pci_dev *pdev)
0634 {
0635     struct ioc3_priv_data *ipd;
0636 
0637     ipd = pci_get_drvdata(pdev);
0638 
0639     /* Clear and disable all IRQs */
0640     writel(~0, &ipd->regs->sio_iec);
0641     writel(~0, &ipd->regs->sio_ir);
0642 
0643     /* Release resources */
0644     mfd_remove_devices(&ipd->pdev->dev);
0645     if (ipd->domain) {
0646         struct fwnode_handle *fn = ipd->domain->fwnode;
0647 
0648         irq_domain_remove(ipd->domain);
0649         irq_domain_free_fwnode(fn);
0650         free_irq(ipd->domain_irq, (void *)ipd);
0651     }
0652     pci_iounmap(pdev, ipd->regs);
0653     pci_disable_device(pdev);
0654 }
0655 
0656 static struct pci_device_id ioc3_mfd_id_table[] = {
0657     { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, PCI_ANY_ID, PCI_ANY_ID },
0658     { 0, },
0659 };
0660 MODULE_DEVICE_TABLE(pci, ioc3_mfd_id_table);
0661 
0662 static struct pci_driver ioc3_mfd_driver = {
0663     .name = "IOC3",
0664     .id_table = ioc3_mfd_id_table,
0665     .probe = ioc3_mfd_probe,
0666     .remove = ioc3_mfd_remove,
0667 };
0668 
0669 module_pci_driver(ioc3_mfd_driver);
0670 
0671 MODULE_AUTHOR("Thomas Bogendoerfer <tbogendoerfer@suse.de>");
0672 MODULE_DESCRIPTION("SGI IOC3 MFD driver");
0673 MODULE_LICENSE("GPL v2");
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